; Run the multiplexer channel diagnostic (D422A). ; Set up the log(s). set -n console log=zmpx.log set -n console debug=debug.log ; Configuration locations: ; ; Location Default Value Contents ; ------------- ------------- --------------------------------------------------- ; DB+0 045624 000000 Switch Register setting ; DB+1 045625 077777 Section Select Register setting ; DB+2 045626 000000 Version and update level ; DB+3 045627 000177 127 Multiplexer channel DRT number ; DB+4 045630 001747 999 Maximum error print count ; DB+5 045631 000101 65 SCMB #1 DRT number ; DB+6 045632 000102 66 SCMB #2 DRT number ; DB+7 045633 000003 3 Clock DRT number ; DB+10 045634 000000 0 Upper bank number (0-3 for 30036A, 0-15 for 30036B) ; DB+11 045635 177777 Upper address within upper bank (30036A only) ; Configure the CPU for the diagnostic. ; ; Reduce the memory size to allow testing of XFERERR on illegal memory address. set cpu 512K ; Boot the I/O diagnostics tape. attach -r ms0 30000-11017_Rev-2640_IO.tape boot ms0 ; Load the tape file containing the diagnostic. ; ; The I/O tape contains these files: ; ; DIAGNOSTIC FILE REV %FILE ; ------------------- ------ ----- ---- ; SLEUTH PD411A 01.05 (01) ; CART DISC-7905A PD419A 01.04 (02) ; MEMORY PATTERN PD421A 01.00 (03) ; MULTIPLEXOR CHAN PD422A 01.02 (04) ; DISC FILE-2888A PD423A 01.00 (05) ; CART DISC-7900A PD424A 01.00 (06) ; SYSTEM CLOCK II/III PD425A 01.00 (07) ; SYS CLK/FLI III-LC PD426A 00.00 (10) ; TERMINAL DATA PD427A 01.01 (11) ; FIXED HEAD DISC PD428A 01.00 (12) ; SELECTOR CHAN PD429A 01.01 (13) ; FLT.CORR.MEM SER-II PD430A 01.01 (14) ; FLT.CORR.MEM SER-III PD430B 00.00 (15) ; EXTEND INSTRUC SET PD431A 01.00 (16) ; HSI DIAG. PD432A 01.00 (17) ; MAGNETIC TAPE PD433A 01.04 (20) ; SSLC INTERFACE PD434A 01.03 (21) ; ASLC INTERFACE PD434B 01.04 (22) ; UI DIAG PD435A 01.01 (23) ; TERMINAL CONTROL PD438A 01.00 (24) ; CALCOMP PLOTTER PD439A 01.01 (25) ; COBOLII A F/W DIAG PD441A 00.00 (26) ; COBOLII B F/W DIAG PD442A 00.00 (27) ; STAND ALONE DISC SADUTIL 01.00 (30) deposit SWCH 04 ; Connect the SCMBs to the multiplexer channel. set scmb1 enable set scmb2 enable set scmb1 mx set scmb2 mx ; Set the system clock into diagnostic mode. set clk realtime ; Run the diagnostic. echo echo Press to start the diagnostic. echo Expect halt 0 if successful. go ; Verify HALT 0 and respond to Q01 SELECT SWITCH REGISTER OPTIONS. assert CIR=030360 ; Set the Switch Register options: ; ; + bit 0 = select the external switch register ; + bit 1 = modify the Section Select Register ; bit 2 = bypass section (AREG) ; bit 3 = bypass section (OREG) ; bit 4 = bypass section (SIOTEST steps 63-68) ; bit 5 = loop on the current section ; bit 6 = bypass section (SIOTEST steps 75-78) ; bit 7 = output to the line printer (if configured) ; bit 8 = not used ; bit 9 = suppress non-error messages ; bit 10 = suppress error messages ; bit 11 = loop on the last step ; bit 12 = halt on error ; bit 13 = halt at the end of each step ; bit 14 = halt at the end of each section ; bit 15 = halt at the end of each diagnostic pass deposit SWCH 140000 echo echo Configuring the switch register. echo Expect halt 1 if successful. echo go ; Verify HALT 1 and respond to Q02 SELECT SECTION OPTIONS. assert CIR=030361 ; Set the Section Select options: ; ; + bit 0 = reconfigure ; + bit 1 = execute IORES section ; + bit 2 = execute ARADDR section ; + bit 3 = execute ARDATA section ; + bit 4 = execute ARCPP section ; + bit 5 = execute ORADDR section ; + bit 6 = execute ORDATA section ; + bit 7 = execute ORCP section ; + bit 8 = execute AREG section ; + bit 9 = execute OREG section ; + bit 10 = execute NSGP1 section ; + bit 11 = execute NSGP2 section ; + bit 12 = execute NSGP3 section ; + bit 13 = execute NSGP4 section ; + bit 14 = execute STPAR section ; + bit 15 = execute SIOTEST section deposit SWCH 177777 ;deposit SWCH 100001 echo echo Configuring the section select register. echo Expect halt 2 if successful. echo go ; Verify HALT 2 and respond to Q03 RESTORE REGISTER OPTIONS. assert CIR=030362 ; Set the Switch Register options: ; ; + bit 0 = select the external switch register ; bit 1 = modify the Section Select Register ; bit 2 = bypass section (AREG) ; bit 3 = bypass section (OREG) ; bit 4 = bypass section (SIOTEST steps 63-68) ; bit 5 = loop on the current section ; bit 6 = bypass section (SIOTEST steps 75-78) ; bit 7 = output to the line printer (if configured) ; bit 8 = not used ; bit 9 = suppress non-error messages ; bit 10 = suppress error messages ; bit 11 = loop on the last step ; + bit 12 = halt on error ; bit 13 = halt at the end of each step ; bit 14 = halt at the end of each section ; + bit 15 = halt at the end of each diagnostic pass deposit SWCH 100011 ; Set the debugging options. ;set cpu debug set iop debug=dio;irq,filter=7 ;set clk debug ;set atcd debug=xfer set scmb1 debug set scmb2 debug set mpx debug ; Run the diagnostic. echo echo Reconfiguring the switch register and executing the diagnostic. echo Expect halt 15 for successful completion. echo set console delay=10000 set -a -i console halt=Q04 ENTER MPX DEVICE #= go ; Respond to "Q04 ENTER MPX DEVICE #= " set console response=127~m set -a -i console halt=Q05 ENTER MAXIMUM ERROR COUNT# = go ; Respond to "Q05 ENTER MAXIMUM ERROR COUNT# = " set console response=999~m set -a console halt=P11 OTHERWISE INSERT BOARD,CONNECT POLLS,AND RE-COLD LOAD go ; Respond to "P11 IF SEL. CHAN. MAINTENANCE BOARD ALREADY IN THEN HIT * CR*" ; "P11 OTHERWISE INSERT BOARD,CONNECT POLLS,AND RE-COLD LOAD" set console response=~m set -a -i console halt=Q06 ENTER SEL. CHAN. MAINTENANCE BOARD DRT# = go ; Respond to "Q06 ENTER SEL. CHAN. MAINTENANCE BOARD DRT# =" set console response=65~m set -a -i console halt=Q07 ENTER 2ND SCMB DRT# = go ; Respond to "Q07 ENTER 2ND SCMB DRT# =" set console response=66~m set -a -i console halt=Q08 ENTER CLOCK/CONSOLE DRT# = go ; Respond to "Q08 ENTER CLOCK/CONSOLE DRT# = " set console response=3~m set -a -i console halt=Q09 ENTER UPPER BANK # (DECIMAL) = go ; Respond to "Q09 ENTER UPPER BANK # (DECIMAL) = " set console response=7~m set console nohalt go ; End the of diagnostic. ; ; Verify HALT 15 for a successful pass. assert CIR=030375