>>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000007 absolute read >>CPP cmd: Channel processor executing SLFT >>CPP data: 00.000772 000000 absolute write >>CPP serv: Completion delay 389 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000005 absolute read >>CPP cmd: Channel processor executing IOCL >>CPP data: 00.000013 000000 absolute write >>IMBA imbus: Channel 1 received opcode I/O Write command IOCL register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command IOCL register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000004 absolute read >>CPP cmd: Channel processor executing SED2 >>CPP data: 00.000771 000001 absolute read >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000004 absolute read >>CPP cmd: Channel processor executing SED2 >>CPP data: 00.000771 000001 absolute read >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000003 absolute read >>CPP cmd: Channel processor executing WIOC >>CPP data: 00.000771 100000 absolute read >>CPP data: 00.000772 000000 absolute read >>CPP data: 00.000003 000000 absolute read >>IMBA imbus: Channel 1 received opcode I/O Write command SMSK register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command SMSK register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000004 absolute read >>CPP cmd: Channel processor executing SED2 >>CPP data: 00.000771 000000 absolute read >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000004 absolute read >>CPP cmd: Channel processor executing SED2 >>CPP data: 00.000771 000001 absolute read >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000004 absolute read >>CPP cmd: Channel processor executing SED2 >>CPP data: 00.000771 000001 absolute read >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000002 absolute read >>CPP cmd: Channel processor executing RIOC >>CPP data: 00.000771 120010 absolute read >>CPP data: 00.000043 000000 absolute read >>IMBA imbus: Channel 1 received opcode I/O Read command ROCL register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command ROCL register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | PRO >>CPP data: 00.000772 000020 absolute write >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000002 absolute read >>CPP cmd: Channel processor executing RIOC >>CPP data: 00.000771 120010 absolute read >>CPP data: 00.000043 000000 absolute read >>IMBA imbus: Channel 1 received opcode I/O Read command ROCL register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command ROCL register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | PRO >>CPP data: 00.000772 000020 absolute write >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000002 absolute read >>CPP cmd: Channel processor executing RIOC >>CPP data: 00.000771 120010 absolute read >>CPP data: 00.000043 000000 absolute read >>IMBA imbus: Channel 1 received opcode I/O Read command ROCL register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command ROCL register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | PRO >>CPP data: 00.000772 000020 absolute write >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000002 absolute read >>CPP cmd: Channel processor executing RIOC >>CPP data: 00.000771 120010 absolute read >>CPP data: 00.000043 000000 absolute read >>IMBA imbus: Channel 1 received opcode I/O Read command ROCL register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command ROCL register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | PRO >>CPP data: 00.000772 000020 absolute write >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000002 absolute read >>CPP cmd: Channel processor executing RIOC >>CPP data: 00.000771 120010 absolute read >>CPP data: 00.000043 000000 absolute read >>IMBA imbus: Channel 1 received opcode I/O Read command ROCL register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command ROCL register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | PRO >>CPP data: 00.000772 000020 absolute write >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000002 absolute read >>CPP cmd: Channel processor executing RIOC >>CPP data: 00.000771 120010 absolute read >>CPP data: 00.000043 000000 absolute read >>IMBA imbus: Channel 1 received opcode I/O Read command ROCL register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command ROCL register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | PRO >>CPP data: 00.000772 000020 absolute write >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000002 absolute read >>CPP cmd: Channel processor executing RIOC >>CPP data: 00.000771 120010 absolute read >>CPP data: 00.000043 000000 absolute read >>IMBA imbus: Channel 1 received opcode I/O Read command ROCL register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command ROCL register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | PRO >>CPP data: 00.000772 000020 absolute write >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000002 absolute read >>CPP cmd: Channel processor executing RIOC >>CPP data: 00.000771 120010 absolute read >>CPP data: 00.000043 000000 absolute read >>IMBA imbus: Channel 1 received opcode I/O Read command ROCL register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command ROCL register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | PRO >>CPP data: 00.000772 000020 absolute write >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000002 absolute read >>CPP cmd: Channel processor executing RIOC >>CPP data: 00.000771 120010 absolute read >>CPP data: 00.000043 000000 absolute read >>IMBA imbus: Channel 1 received opcode I/O Read command ROCL register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command ROCL register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | PRO >>CPP data: 00.000772 000020 absolute write >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000002 absolute read >>CPP cmd: Channel processor executing RIOC >>CPP data: 00.000771 120010 absolute read >>CPP data: 00.000043 000000 absolute read >>IMBA imbus: Channel 1 received opcode I/O Read command ROCL register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command ROCL register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | PRO >>CPP data: 00.000772 000020 absolute write >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000002 absolute read >>CPP cmd: Channel processor executing RIOC >>CPP data: 00.000771 120010 absolute read >>CPP data: 00.000043 000000 absolute read >>IMBA imbus: Channel 1 received opcode I/O Read command ROCL register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command ROCL register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | PRO >>CPP data: 00.000772 000020 absolute write >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000002 absolute read >>CPP cmd: Channel processor executing RIOC >>CPP data: 00.000771 007130 absolute read >>CPP data: 00.000543 000000 absolute read >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register E data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register E (DMA abort) status is S2 A | S1 CPU | channel ID 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000772 000000 absolute write >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000002 absolute read >>CPP cmd: Channel processor executing RIOC >>CPP data: 00.000771 007130 absolute read >>CPP data: 00.000543 000000 absolute read >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register E data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register E (DMA abort) status is S2 A | S1 CPU | channel ID 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000772 000000 absolute write >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000006 absolute read >>CPP cmd: Channel processor executing INIT >>CPP data: 00.000771 000130 absolute read >>CPP data: 00.000013 000000 absolute read >>CPP data: 00.000013 000000 absolute write >>CPP data: 00.000543 000000 absolute write >>CPP data: 00.000547 000000 absolute write >>CPP data: 00.000553 000000 absolute write >>CPP data: 00.000557 000000 absolute write >>CPP data: 00.000563 000000 absolute write >>CPP data: 00.000567 000000 absolute write >>CPP data: 00.000573 000000 absolute write >>CPP data: 00.000577 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command INIT register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register E data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register E (DMA abort) status is S2 A | S1 CPU | channel ID 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000010 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is poll response | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 7 data 000200 with signals ADO | DDO | PRI >>GIC csrw: Register 7 (Bus address) control is bus address 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000060 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is REN | IFC | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000040 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is REN | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 2 data 040301 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) control is parity error | status change | FIFO abort | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000001 absolute read >>CPP cmd: Channel processor executing HIOP >>CPP data: 00.000771 000130 absolute read >>CPP data: 00.000543 000000 absolute read >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000003 absolute read >>CPP cmd: Channel processor executing WIOC >>CPP data: 00.000771 100000 absolute read >>CPP data: 00.000772 000020 absolute read >>CPP data: 00.000103 000000 absolute read >>IMBA imbus: Channel 1 received opcode I/O Write command SMSK register 0 data 000020 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command SMSK register 0 data 000020 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000000 absolute read >>CPP cmd: Channel processor executing SIOP >>CPP data: 00.000771 000130 absolute read >>CPP data: 00.000773 101140 absolute read >>CPP data: 00.000543 000000 absolute read >>CPP data: 00.000540 101140 absolute write >>CPP data: 00.000543 140000 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command SIOP register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>CPP opnd: 00.101140 003000 Identify | response FFFF >>CPP opnd: 00.101142 000601 Interrupt/Halt 0001 | CPVA 1 >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor rescheduled >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | CSRQ1 | PRO >>CPP cmd: Channel processor servicing channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBSI register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 001130 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.000543 140000 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command SIOP register 0 data 000010 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000140 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is parity freeze | REN | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 4 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 4 (Poll mask) status is (none) >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 4 data 000200 with signals ADO | DDO | PRI >>GIC csrw: Register 4 (Poll mask) control is PP 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register F data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register F (Service info) control is DMA inbound | device 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000543 100000 absolute write >>CPP data: 00.000540 101140 absolute read >>CPP data: 00.101140 003000 absolute read >>CPP data: 00.101141 177777 absolute read >>CPP cmd: Executing Identify | response FFFF >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040076 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 076 sent to bus >>GIC buf: Command byte 076 loaded into outbound FIFO count 1 >>GIC buf: Command byte 076 unloaded from outbound FIFO count 0 >>GIC xfer: DIO | ATN | EOI | NRFD | REN | IFC | HP-IB Mnemonic >>GIC xfer: 3EH | ATN | | | | | Listen 30 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040137 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 137 sent to bus >>GIC buf: Command byte 137 loaded into outbound FIFO count 1 >>GIC buf: Command byte 137 unloaded from outbound FIFO count 0 >>GIC xfer: 5FH | ATN | | | | | Untalk >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040140 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 140 sent to bus >>GIC buf: Command byte 140 loaded into outbound FIFO count 1 >>GIC buf: Command byte 140 unloaded from outbound FIFO count 0 >>GIC xfer: 60H | ATN | | | | | Secondary 00H >>GIC xfer: 01H | | | | | | Data (device 30 accepts) >>GIC buf: Data byte 001 loaded into inbound FIFO count 1 >>GIC xfer: 76H | | EOI | | | | Data (device 30 accepts) >>GIC buf: Tagged data byte 166 loaded into inbound FIFO count 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 140002 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Reception enabled >>GIC buf: Transfer count 002 loaded into outbound FIFO count 1 >>GIC buf: Transfer count 002 unloaded from outbound FIFO count 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 100004 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is IRQ | data >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register F data 000200 with signals ADO | DDO | PRI >>GIC csrw: Register F (Service info) control is inhibit CSRQ | DMA inbound | device 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.000543 100000 absolute read >>CPP data: 00.000543 100010 absolute write >>CPP data: 00.000540 101140 absolute write >>CPP serv: Channel processor rescheduled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | CSRQ1 | PRO >>CPP cmd: Channel processor servicing channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBSI register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000530 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>CPP data: 00.000543 100010 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register F data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register F (Service info) control is DMA inbound | device 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000543 100000 absolute write >>CPP data: 00.000540 101140 absolute read >>CPP data: 00.101140 003000 absolute read >>CPP data: 00.101141 177777 absolute read >>CPP cmd: Executing Identify | response FFFF >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is data | empty >>GIC imbus: Channel 11 returned data 000006 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 0 data 000000 with signals ADO | DDO | PRI >>GIC buf: Data byte 001 unloaded from inbound FIFO count 1 >>GIC csrw: Register 0 (FIFO) Data 001 received from bus >>GIC imbus: Channel 11 returned data 000001 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 0 data 000000 with signals ADO | DDO | PRI >>GIC buf: Tagged data byte 166 unloaded from inbound FIFO count 0 >>GIC csrw: Register 0 (FIFO) Data Tagged | 166 received from bus >>GIC imbus: Channel 11 returned data 140166 with signals ADN | DDN | PRO >>CPP data: 00.101141 000566 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040077 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 077 sent to bus >>GIC buf: Command byte 077 loaded into outbound FIFO count 1 >>GIC buf: Command byte 077 unloaded from outbound FIFO count 0 >>GIC xfer: 3FH | ATN | | | | | Unlisten >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040136 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 136 sent to bus >>GIC buf: Command byte 136 loaded into outbound FIFO count 1 >>GIC buf: Command byte 136 unloaded from outbound FIFO count 0 >>GIC xfer: 5EH | ATN | | | | | Talk 30 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101142 000601 absolute read >>CPP data: 00.101143 000001 absolute read >>CPP cmd: Executing Interrupt/Halt 0001 | CPVA 1 >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>CPP data: 00.000542 101104 absolute read >>CPP data: 00.101105 100001 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register C data 000010 with signals ADO | DDO | PRI >>GIC csrw: Register C (Interrupt) control is set | device 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | IRQ | PRO >>GIC imbus: Channel 11 asserts IRQ >>CPP serv: Program delay 1 service scheduled >>CPP data: 00.000543 100000 absolute read >>CPP data: 00.000543 000000 absolute write >>CPP data: 00.000540 101144 absolute write >>CPP serv: Channel processor rescheduled >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command IPOLL register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | IRQ | PRO >>CPP cmd: Channel processor interrupted by channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBII register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000130 with signals ADN | DDN | IRQ | PRO >>IMBA imbus: Channel 1 received opcode I/O Write command WIOC register 0 data 000130 with signals ADO | DDO | PRI >>IOP irq: Device number 125 asserted INTREQ at priority 12 >>IMBA imbus: Channel 1 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register C data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register C (Interrupt) control is clear | device 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Channel processor idled >>IMBA iobus: Received data 000000 with signals INTPOLLIN >>IMBA iobus: Returned data 000130 with signals INTACK >>IOP irq: Device number 125 acknowledged interrupt request at priority 12 >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000004 absolute read >>CPP cmd: Channel processor executing SED2 >>CPP data: 00.000771 000001 absolute read >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Reset Interrupt order sent to device number 88 >>IMBA iobus: Received data 000000 with signals DRESETINT >>IMBA iobus: Returned data 000000 with signals (none) >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000002 absolute read >>CPP cmd: Channel processor executing RIOC >>CPP data: 00.000771 007131 absolute read >>CPP data: 00.000547 000000 absolute read >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register E data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register E (DMA abort) status is S2 A | S1 CPU | channel ID 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000772 000000 absolute write >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000006 absolute read >>CPP cmd: Channel processor executing INIT >>CPP data: 00.000771 000130 absolute read >>CPP data: 00.000013 000020 absolute read >>CPP data: 00.000013 000000 absolute write >>CPP data: 00.000543 000000 absolute write >>CPP data: 00.000547 000000 absolute write >>CPP data: 00.000553 000000 absolute write >>CPP data: 00.000557 000000 absolute write >>CPP data: 00.000563 000000 absolute write >>CPP data: 00.000567 000000 absolute write >>CPP data: 00.000573 000000 absolute write >>CPP data: 00.000577 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command INIT register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register E data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register E (DMA abort) status is S2 A | S1 CPU | channel ID 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000010 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is poll response | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 7 data 000200 with signals ADO | DDO | PRI >>GIC csrw: Register 7 (Bus address) control is bus address 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000060 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is REN | IFC | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000040 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is REN | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 2 data 040301 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) control is parity error | status change | FIFO abort | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000001 absolute read >>CPP cmd: Channel processor executing HIOP >>CPP data: 00.000771 000131 absolute read >>CPP data: 00.000547 000000 absolute read >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000003 absolute read >>CPP cmd: Channel processor executing WIOC >>CPP data: 00.000771 100000 absolute read >>CPP data: 00.000772 000020 absolute read >>CPP data: 00.000103 000000 absolute read >>IMBA imbus: Channel 1 received opcode I/O Write command SMSK register 0 data 000020 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command SMSK register 0 data 000020 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000000 absolute read >>CPP cmd: Channel processor executing SIOP >>CPP data: 00.000771 000131 absolute read >>CPP data: 00.000773 101140 absolute read >>CPP data: 00.000547 000000 absolute read >>CPP data: 00.000544 101140 absolute write >>CPP data: 00.000547 140000 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command SIOP register 0 data 000001 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>CPP opnd: 00.101140 003000 Identify | response FFFF >>CPP opnd: 00.101142 000601 Interrupt/Halt 0001 | CPVA 1 >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor rescheduled >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | CSRQ1 | PRO >>CPP cmd: Channel processor servicing channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBSI register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 001131 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.000547 140000 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command SIOP register 0 data 000011 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000140 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is parity freeze | REN | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 4 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 4 (Poll mask) status is PP 0 >>GIC imbus: Channel 11 returned data 000200 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 4 data 000300 with signals ADO | DDO | PRI >>GIC csrw: Register 4 (Poll mask) control is PP 0 | PP 1 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register F data 000001 with signals ADO | DDO | PRI >>GIC csrw: Register F (Service info) control is DMA inbound | device 1 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000547 100000 absolute write >>CPP data: 00.000544 101140 absolute read >>CPP data: 00.101140 003000 absolute read >>CPP data: 00.101141 177777 absolute read >>CPP cmd: Executing Identify | response FFFF >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040076 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 076 sent to bus >>GIC buf: Command byte 076 loaded into outbound FIFO count 1 >>GIC buf: Command byte 076 unloaded from outbound FIFO count 0 >>GIC xfer: 3EH | ATN | | | | | Listen 30 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040137 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 137 sent to bus >>GIC buf: Command byte 137 loaded into outbound FIFO count 1 >>GIC buf: Command byte 137 unloaded from outbound FIFO count 0 >>GIC xfer: 5FH | ATN | | | | | Untalk >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040141 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 141 sent to bus >>GIC buf: Command byte 141 loaded into outbound FIFO count 1 >>GIC buf: Command byte 141 unloaded from outbound FIFO count 0 >>GIC xfer: 61H | ATN | | | | | Secondary 01H >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 140002 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Reception enabled >>GIC buf: Transfer count 002 loaded into outbound FIFO count 1 >>GIC buf: Transfer count 002 unloaded from outbound FIFO count 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 100004 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is IRQ | data >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register F data 000201 with signals ADO | DDO | PRI >>GIC csrw: Register F (Service info) control is inhibit CSRQ | DMA inbound | device 1 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000547 100000 absolute read >>CPP data: 00.000547 100010 absolute write >>CPP data: 00.000544 101140 absolute write >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000001 absolute read >>CPP cmd: Channel processor executing HIOP >>CPP data: 00.000771 000131 absolute read >>CPP data: 00.000547 100010 absolute read >>CPP data: 00.000547 040000 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command HIOP register 0 data 000001 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor rescheduled >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | CSRQ1 | PRO >>CPP cmd: Channel processor servicing channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBSI register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 001131 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.000547 040000 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command HIOP register 0 data 000011 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000547 040000 absolute read >>CPP data: 00.000547 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 4 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 4 (Poll mask) status is PP 0 | PP 1 >>GIC imbus: Channel 11 returned data 000300 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 4 data 000300 with signals ADO | DDO | PRI >>GIC csrw: Register 4 (Poll mask) control is PP 0 | PP 1 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 100240 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is IRQ | status change | poll response >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100401 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000006 absolute read >>CPP cmd: Channel processor executing INIT >>CPP data: 00.000771 000130 absolute read >>CPP data: 00.000013 000020 absolute read >>CPP data: 00.000013 000000 absolute write >>CPP data: 00.000543 000000 absolute write >>CPP data: 00.000547 000000 absolute write >>CPP data: 00.000553 000000 absolute write >>CPP data: 00.000557 000000 absolute write >>CPP data: 00.000563 000000 absolute write >>CPP data: 00.000567 000000 absolute write >>CPP data: 00.000573 000000 absolute write >>CPP data: 00.000577 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command INIT register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register E data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register E (DMA abort) status is S2 A | S1 CPU | channel ID 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000010 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is poll response | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 7 data 000200 with signals ADO | DDO | PRI >>GIC csrw: Register 7 (Bus address) control is bus address 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000060 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is REN | IFC | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000040 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is REN | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 2 data 040301 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) control is parity error | status change | FIFO abort | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000002 absolute read >>CPP cmd: Channel processor executing RIOC >>CPP data: 00.000771 007132 absolute read >>CPP data: 00.000553 000000 absolute read >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register E data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register E (DMA abort) status is S2 A | S1 CPU | channel ID 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000772 000000 absolute write >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000006 absolute read >>CPP cmd: Channel processor executing INIT >>CPP data: 00.000771 000130 absolute read >>CPP data: 00.000013 000000 absolute read >>CPP data: 00.000013 000000 absolute write >>CPP data: 00.000543 000000 absolute write >>CPP data: 00.000547 000000 absolute write >>CPP data: 00.000553 000000 absolute write >>CPP data: 00.000557 000000 absolute write >>CPP data: 00.000563 000000 absolute write >>CPP data: 00.000567 000000 absolute write >>CPP data: 00.000573 000000 absolute write >>CPP data: 00.000577 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command INIT register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register E data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register E (DMA abort) status is S2 A | S1 CPU | channel ID 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000010 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is poll response | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 7 data 000200 with signals ADO | DDO | PRI >>GIC csrw: Register 7 (Bus address) control is bus address 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000060 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is REN | IFC | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000040 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is REN | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 2 data 040301 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) control is parity error | status change | FIFO abort | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000001 absolute read >>CPP cmd: Channel processor executing HIOP >>CPP data: 00.000771 000132 absolute read >>CPP data: 00.000553 000000 absolute read >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000003 absolute read >>CPP cmd: Channel processor executing WIOC >>CPP data: 00.000771 100000 absolute read >>CPP data: 00.000772 000020 absolute read >>CPP data: 00.000103 000000 absolute read >>IMBA imbus: Channel 1 received opcode I/O Write command SMSK register 0 data 000020 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command SMSK register 0 data 000020 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000000 absolute read >>CPP cmd: Channel processor executing SIOP >>CPP data: 00.000771 000132 absolute read >>CPP data: 00.000773 101140 absolute read >>CPP data: 00.000553 000000 absolute read >>CPP data: 00.000550 101140 absolute write >>CPP data: 00.000553 140000 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command SIOP register 0 data 000002 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>CPP opnd: 00.101140 003000 Identify | response FFFF >>CPP opnd: 00.101142 000601 Interrupt/Halt 0001 | CPVA 1 >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor rescheduled >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | CSRQ1 | PRO >>CPP cmd: Channel processor servicing channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBSI register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 001132 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.000553 140000 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command SIOP register 0 data 000012 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000140 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is parity freeze | REN | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 4 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 4 (Poll mask) status is PP 0 | PP 1 >>GIC imbus: Channel 11 returned data 000300 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 4 data 000340 with signals ADO | DDO | PRI >>GIC csrw: Register 4 (Poll mask) control is PP 0 | PP 1 | PP 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register F data 000002 with signals ADO | DDO | PRI >>GIC csrw: Register F (Service info) control is DMA inbound | device 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000553 100000 absolute write >>CPP data: 00.000550 101140 absolute read >>CPP data: 00.101140 003000 absolute read >>CPP data: 00.101141 177777 absolute read >>CPP cmd: Executing Identify | response FFFF >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040076 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 076 sent to bus >>GIC buf: Command byte 076 loaded into outbound FIFO count 1 >>GIC buf: Command byte 076 unloaded from outbound FIFO count 0 >>GIC xfer: 3EH | ATN | | | | | Listen 30 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040137 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 137 sent to bus >>GIC buf: Command byte 137 loaded into outbound FIFO count 1 >>GIC buf: Command byte 137 unloaded from outbound FIFO count 0 >>GIC xfer: 5FH | ATN | | | | | Untalk >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040142 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 142 sent to bus >>GIC buf: Command byte 142 loaded into outbound FIFO count 1 >>GIC buf: Command byte 142 unloaded from outbound FIFO count 0 >>GIC xfer: 62H | ATN | | | | | Secondary 02H >>GIC xfer: 00H | | | | | | Data (device 30 accepts) >>GIC buf: Data byte 000 loaded into inbound FIFO count 1 >>GIC xfer: 02H | | EOI | | | | Data (device 30 accepts) >>GIC buf: Tagged data byte 002 loaded into inbound FIFO count 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 140002 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Reception enabled >>GIC buf: Transfer count 002 loaded into outbound FIFO count 1 >>GIC buf: Transfer count 002 unloaded from outbound FIFO count 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 100004 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is IRQ | data >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register F data 000202 with signals ADO | DDO | PRI >>GIC csrw: Register F (Service info) control is inhibit CSRQ | DMA inbound | device 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.000553 100000 absolute read >>CPP data: 00.000553 100010 absolute write >>CPP data: 00.000550 101140 absolute write >>CPP serv: Channel processor rescheduled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | CSRQ1 | PRO >>CPP cmd: Channel processor servicing channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBSI register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000532 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>CPP data: 00.000553 100010 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register F data 000002 with signals ADO | DDO | PRI >>GIC csrw: Register F (Service info) control is DMA inbound | device 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000553 100000 absolute write >>CPP data: 00.000550 101140 absolute read >>CPP data: 00.101140 003000 absolute read >>CPP data: 00.101141 177777 absolute read >>CPP cmd: Executing Identify | response FFFF >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is data | empty >>GIC imbus: Channel 11 returned data 000006 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 0 data 000000 with signals ADO | DDO | PRI >>GIC buf: Data byte 000 unloaded from inbound FIFO count 1 >>GIC csrw: Register 0 (FIFO) Data 000 received from bus >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 0 data 000000 with signals ADO | DDO | PRI >>GIC buf: Tagged data byte 002 unloaded from inbound FIFO count 0 >>GIC csrw: Register 0 (FIFO) Data Tagged | 002 received from bus >>GIC imbus: Channel 11 returned data 140002 with signals ADN | DDN | PRO >>CPP data: 00.101141 000002 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040077 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 077 sent to bus >>GIC buf: Command byte 077 loaded into outbound FIFO count 1 >>GIC buf: Command byte 077 unloaded from outbound FIFO count 0 >>GIC xfer: 3FH | ATN | | | | | Unlisten >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040136 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 136 sent to bus >>GIC buf: Command byte 136 loaded into outbound FIFO count 1 >>GIC buf: Command byte 136 unloaded from outbound FIFO count 0 >>GIC xfer: 5EH | ATN | | | | | Talk 30 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101142 000601 absolute read >>CPP data: 00.101143 000001 absolute read >>CPP cmd: Executing Interrupt/Halt 0001 | CPVA 1 >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>CPP data: 00.000552 101104 absolute read >>CPP data: 00.101105 100001 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register C data 000012 with signals ADO | DDO | PRI >>GIC csrw: Register C (Interrupt) control is set | device 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | IRQ | PRO >>GIC imbus: Channel 11 asserts IRQ >>CPP serv: Program delay 1 service scheduled >>CPP data: 00.000553 100000 absolute read >>CPP data: 00.000553 000000 absolute write >>CPP data: 00.000550 101144 absolute write >>CPP serv: Channel processor rescheduled >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command IPOLL register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | IRQ | PRO >>CPP cmd: Channel processor interrupted by channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBII register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000132 with signals ADN | DDN | IRQ | PRO >>IMBA imbus: Channel 1 received opcode I/O Write command WIOC register 0 data 000132 with signals ADO | DDO | PRI >>IOP irq: Device number 125 asserted INTREQ at priority 12 >>IMBA imbus: Channel 1 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register C data 000002 with signals ADO | DDO | PRI >>GIC csrw: Register C (Interrupt) control is clear | device 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Channel processor idled >>IMBA iobus: Received data 000000 with signals INTPOLLIN >>IMBA iobus: Returned data 000132 with signals INTACK >>IOP irq: Device number 125 acknowledged interrupt request at priority 12 >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000004 absolute read >>CPP cmd: Channel processor executing SED2 >>CPP data: 00.000771 000001 absolute read >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Reset Interrupt order sent to device number 90 >>IMBA iobus: Received data 000000 with signals DRESETINT >>IMBA iobus: Returned data 000000 with signals (none) >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000003 absolute read >>CPP cmd: Channel processor executing WIOC >>CPP data: 00.000771 100000 absolute read >>CPP data: 00.000772 000020 absolute read >>CPP data: 00.000103 000000 absolute read >>IMBA imbus: Channel 1 received opcode I/O Write command SMSK register 0 data 000020 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command SMSK register 0 data 000020 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000000 absolute read >>CPP cmd: Channel processor executing SIOP >>CPP data: 00.000771 000132 absolute read >>CPP data: 00.000773 101171 absolute read >>CPP data: 00.000553 000000 absolute read >>CPP data: 00.000550 101171 absolute write >>CPP data: 00.000553 140000 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command SIOP register 0 data 000002 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>CPP opnd: 00.101171 004400 Clear 000 >>CPP opnd: 00.101173 002010 Write secondary 10 count 2 burst 1 address 00101115 chain 0 | record mode | left byte >>CPP opnd: 00.101200 001410 Read secondary 10 count 4 burst 1 address 00101113 chain 0 termination 101205 | record mode | left byte >>CPP opnd: 00.101205 000601 Interrupt/Halt 0001 | CPVA 1 >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor rescheduled >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | CSRQ1 | PRO >>CPP cmd: Channel processor servicing channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBSI register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 001132 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.000553 140000 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command SIOP register 0 data 000012 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000140 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is parity freeze | REN | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 4 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 4 (Poll mask) status is PP 0 | PP 1 | PP 2 >>GIC imbus: Channel 11 returned data 000340 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 4 data 000340 with signals ADO | DDO | PRI >>GIC csrw: Register 4 (Poll mask) control is PP 0 | PP 1 | PP 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register F data 000002 with signals ADO | DDO | PRI >>GIC csrw: Register F (Service info) control is DMA inbound | device 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000553 100000 absolute write >>CPP data: 00.000550 101171 absolute read >>CPP data: 00.101171 004400 absolute read >>CPP data: 00.101172 061044 absolute read >>CPP cmd: Executing Clear 000 >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040136 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 136 sent to bus >>GIC buf: Command byte 136 loaded into outbound FIFO count 1 >>GIC buf: Command byte 136 unloaded from outbound FIFO count 0 >>GIC xfer: 5EH | ATN | | | | | Talk 30 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040042 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 042 sent to bus >>GIC buf: Command byte 042 loaded into outbound FIFO count 1 >>GIC buf: Command byte 042 unloaded from outbound FIFO count 0 >>GIC xfer: 22H | ATN | | | | | Listen 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040160 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 160 sent to bus >>GIC buf: Command byte 160 loaded into outbound FIFO count 1 >>GIC buf: Command byte 160 unloaded from outbound FIFO count 0 >>GIC xfer: 70H | ATN | | | | | Secondary 10H >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 100000 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data EOI | 000 sent to bus >>GIC buf: EOI | data byte 000 loaded into outbound FIFO count 1 >>GIC buf: EOI | data byte 000 unloaded from outbound FIFO count 0 >>GIC xfer: 00H | | EOI | | | | Data (device 0 accepts) >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040004 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 004 sent to bus >>GIC buf: Command byte 004 loaded into outbound FIFO count 1 >>GIC buf: Command byte 004 unloaded from outbound FIFO count 0 >>GIC xfer: 04H | ATN | | | | | Selected device clear >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040077 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 077 sent to bus >>GIC buf: Command byte 077 loaded into outbound FIFO count 1 >>GIC buf: Command byte 077 unloaded from outbound FIFO count 0 >>GIC xfer: 3FH | ATN | | | | | Unlisten >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101173 002010 absolute read >>CPP data: 00.101174 000002 absolute read >>CPP cmd: Executing Write secondary 10 count 2 burst 1 address 00101115 chain 0 | record mode | left byte >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>CPP data: 00.101176 000000 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040136 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 136 sent to bus >>GIC buf: Command byte 136 loaded into outbound FIFO count 1 >>GIC buf: Command byte 136 unloaded from outbound FIFO count 0 >>GIC xfer: 5EH | ATN | | | | | Talk 30 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040042 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 042 sent to bus >>GIC buf: Command byte 042 loaded into outbound FIFO count 1 >>GIC buf: Command byte 042 unloaded from outbound FIFO count 0 >>GIC xfer: 22H | ATN | | | | | Listen 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040150 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 150 sent to bus >>GIC buf: Command byte 150 loaded into outbound FIFO count 1 >>GIC buf: Command byte 150 unloaded from outbound FIFO count 0 >>GIC xfer: 68H | ATN | | | | | Secondary 08H >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 6 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) status is parity freeze | REN | DMA inbound >>GIC imbus: Channel 11 returned data 000140 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000142 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is parity freeze | REN | DMA outbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 100002 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is IRQ | empty >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 8 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 8 (DMA bank) control is DMA disabled | bank 000 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.101177 101115 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 9 data 101115 with signals ADO | DDO | PRI >>GIC csrw: Register 9 (DMA address) control is address 101115 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register A data 000002 with signals ADO | DDO | PRI >>GIC csrw: Register A (DMA byte count) control is byte count 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.000553 100000 absolute read >>CPP data: 00.000553 100002 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register B data 000022 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) control is left byte | outbound | device 2 >>IMBA imbus: Memory controller received opcode Memory Read address 00101115 data 000000 with signals ADO | DDO | PRI >>IMBA data: 00.101115 001400 dma read >>IMBA imbus: Memory controller returned data 001400 with signals ADN | DDN | PRO >>GIC buf: Data byte 003 loaded into outbound FIFO count 1 >>GIC buf: EOI | data byte 000 loaded into outbound FIFO count 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.000550 101173 absolute write >>CPP serv: Channel processor rescheduled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | CSRQ1 | PRO >>CPP cmd: Channel processor servicing channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBSI register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000532 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>CPP data: 00.000553 100002 absolute read >>CPP data: 00.000550 101173 absolute read >>CPP data: 00.101173 002010 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101176 000000 absolute read >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register A data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register A (DMA byte count) status is byte count 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101174 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 9 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 9 (DMA address) status is address 101116 >>GIC imbus: Channel 11 returned data 101116 with signals ADN | DDN | PRO >>CPP data: 00.101177 101116 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register B data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) status is left byte | outbound | end state 0 | device 2 >>GIC imbus: Channel 11 returned data 000022 with signals ADN | DDN | PRO >>CPP data: 00.101176 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000140 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is parity freeze | REN | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040077 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 077 sent to bus >>GIC buf: Command byte 077 loaded into outbound FIFO count 3 >>GIC buf: Data byte 003 unloaded from outbound FIFO count 2 >>GIC xfer: 03H | | | | | | Data (device 0 accepts) >>GIC buf: EOI | data byte 000 unloaded from outbound FIFO count 1 >>GIC xfer: 00H | | EOI | | | | Data (device 0 accepts) >>GIC buf: Command byte 077 unloaded from outbound FIFO count 0 >>GIC xfer: 3FH | ATN | | | | | Unlisten >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000550 101200 absolute write >>CPP data: 00.000550 101200 absolute read >>CPP data: 00.101200 001410 absolute read >>CPP data: 00.101201 000004 absolute read >>CPP cmd: Executing Read secondary 10 count 4 burst 1 address 00101113 chain 0 termination 101205 | record mode | left byte >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>CPP data: 00.101203 000000 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040076 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 076 sent to bus >>GIC buf: Command byte 076 loaded into outbound FIFO count 1 >>GIC buf: Command byte 076 unloaded from outbound FIFO count 0 >>GIC xfer: 3EH | ATN | | | | | Listen 30 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040102 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 102 sent to bus >>GIC buf: Command byte 102 loaded into outbound FIFO count 1 >>GIC buf: Command byte 102 unloaded from outbound FIFO count 0 >>GIC xfer: 42H | ATN | | | | | Talk 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040150 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 150 sent to bus >>GIC buf: Command byte 150 loaded into outbound FIFO count 1 >>GIC buf: Command byte 150 unloaded from outbound FIFO count 0 >>GIC xfer: 68H | ATN | | | | | Secondary 08H >>GIC xfer: 00H | | | | | | Data (device 30 accepts) >>GIC buf: Data byte 000 loaded into inbound FIFO count 1 >>GIC xfer: 00H | | | | | | Data (device 30 accepts) >>GIC buf: Data byte 000 loaded into inbound FIFO count 2 >>GIC xfer: 02H | | | | | | Data (device 30 accepts) >>GIC buf: Data byte 002 loaded into inbound FIFO count 3 >>GIC xfer: 00H | | | | | | Data (device 30 accepts) >>GIC buf: Data byte 000 loaded into inbound FIFO count 4 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 140000 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Reception enabled >>GIC buf: Transfer count 000 loaded into outbound FIFO count 1 >>GIC buf: Transfer count 000 unloaded from outbound FIFO count 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 8 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 8 (DMA bank) control is DMA disabled | bank 000 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101204 101113 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 9 data 101113 with signals ADO | DDO | PRI >>GIC csrw: Register 9 (DMA address) control is address 101113 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register A data 000004 with signals ADO | DDO | PRI >>GIC csrw: Register A (DMA byte count) control is byte count 4 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000553 100002 absolute read >>CPP data: 00.000553 100002 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register B data 000002 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) control is left byte | inbound | device 2 >>GIC buf: Data byte 000 unloaded from inbound FIFO count 3 >>GIC buf: Data byte 000 unloaded from inbound FIFO count 2 >>IMBA imbus: Memory controller received opcode Memory Write address 00101113 data 000000 with signals ADO | DDO | PRI >>IMBA data: 00.101113 000000 dma write >>IMBA imbus: Memory controller returned data 000000 with signals ADN | DDN | PRO >>GIC buf: Data byte 002 unloaded from inbound FIFO count 1 >>GIC buf: Data byte 000 unloaded from inbound FIFO count 0 >>IMBA imbus: Memory controller received opcode Memory Write address 00101114 data 001000 with signals ADO | DDO | PRI >>IMBA data: 00.101114 001000 dma write >>IMBA imbus: Memory controller returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>CPP data: 00.000550 101200 absolute write >>CPP serv: Channel processor rescheduled >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | CSRQ1 | PRO >>CPP cmd: Channel processor servicing channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBSI register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000532 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>CPP data: 00.000553 100002 absolute read >>CPP data: 00.000550 101200 absolute read >>CPP data: 00.101200 001410 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101203 000000 absolute read >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register A data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register A (DMA byte count) status is byte count 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101201 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 9 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 9 (DMA address) status is address 101115 >>GIC imbus: Channel 11 returned data 101115 with signals ADN | DDN | PRO >>CPP data: 00.101204 101115 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register B data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) status is left byte | inbound | end state 0 | device 2 >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>CPP data: 00.101203 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register B data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) status is left byte | inbound | end state 0 | device 2 >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register B data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) status is left byte | inbound | end state 0 | device 2 >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040137 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 137 sent to bus >>GIC buf: Command byte 137 loaded into outbound FIFO count 1 >>GIC buf: Command byte 137 unloaded from outbound FIFO count 0 >>GIC xfer: 5FH | ATN | | | | | Untalk >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040077 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 077 sent to bus >>GIC buf: Command byte 077 loaded into outbound FIFO count 1 >>GIC buf: Command byte 077 unloaded from outbound FIFO count 0 >>GIC xfer: 3FH | ATN | | | | | Unlisten >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000550 101205 absolute write >>CPP data: 00.000550 101205 absolute read >>CPP data: 00.101205 000601 absolute read >>CPP data: 00.101206 000001 absolute read >>CPP cmd: Executing Interrupt/Halt 0001 | CPVA 1 >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>CPP data: 00.000552 101104 absolute read >>CPP data: 00.101105 100001 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register C data 000012 with signals ADO | DDO | PRI >>GIC csrw: Register C (Interrupt) control is set | device 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | IRQ | PRO >>GIC imbus: Channel 11 asserts IRQ >>CPP serv: Program delay 1 service scheduled >>CPP data: 00.000553 100002 absolute read >>CPP data: 00.000553 000000 absolute write >>CPP data: 00.000550 101207 absolute write >>CPP serv: Channel processor rescheduled >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command IPOLL register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | IRQ | PRO >>CPP cmd: Channel processor interrupted by channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBII register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000132 with signals ADN | DDN | IRQ | PRO >>IMBA imbus: Channel 1 received opcode I/O Write command WIOC register 0 data 000132 with signals ADO | DDO | PRI >>IOP irq: Device number 125 asserted INTREQ at priority 12 >>IMBA imbus: Channel 1 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register C data 000002 with signals ADO | DDO | PRI >>GIC csrw: Register C (Interrupt) control is clear | device 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Channel processor idled >>IMBA iobus: Received data 000000 with signals INTPOLLIN >>IMBA iobus: Returned data 000132 with signals INTACK >>IOP irq: Device number 125 acknowledged interrupt request at priority 12 >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000004 absolute read >>CPP cmd: Channel processor executing SED2 >>CPP data: 00.000771 000001 absolute read >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Reset Interrupt order sent to device number 90 >>IMBA iobus: Received data 000000 with signals DRESETINT >>IMBA iobus: Returned data 000000 with signals (none) >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000003 absolute read >>CPP cmd: Channel processor executing WIOC >>CPP data: 00.000771 100000 absolute read >>CPP data: 00.000772 000020 absolute read >>CPP data: 00.000103 000000 absolute read >>IMBA imbus: Channel 1 received opcode I/O Write command SMSK register 0 data 000020 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command SMSK register 0 data 000020 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000000 absolute read >>CPP cmd: Channel processor executing SIOP >>CPP data: 00.000771 000132 absolute read >>CPP data: 00.000773 101171 absolute read >>CPP data: 00.000553 000000 absolute read >>CPP data: 00.000550 101171 absolute write >>CPP data: 00.000553 140000 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command SIOP register 0 data 000002 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>CPP opnd: 00.101171 004400 Clear 000 >>CPP opnd: 00.101173 002010 Write secondary 10 count 2 burst 1 address 00101115 chain 0 | record mode | left byte >>CPP opnd: 00.101200 001410 Read secondary 10 count 4 burst 1 address 00101113 chain 0 termination 101205 | record mode | left byte >>CPP opnd: 00.101205 000601 Interrupt/Halt 0001 | CPVA 1 >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor rescheduled >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | CSRQ1 | PRO >>CPP cmd: Channel processor servicing channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBSI register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 001132 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.000553 140000 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command SIOP register 0 data 000012 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000140 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is parity freeze | REN | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 4 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 4 (Poll mask) status is PP 0 | PP 1 | PP 2 >>GIC imbus: Channel 11 returned data 000340 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 4 data 000340 with signals ADO | DDO | PRI >>GIC csrw: Register 4 (Poll mask) control is PP 0 | PP 1 | PP 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register F data 000002 with signals ADO | DDO | PRI >>GIC csrw: Register F (Service info) control is DMA inbound | device 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000553 100000 absolute write >>CPP data: 00.000550 101171 absolute read >>CPP data: 00.101171 004400 absolute read >>CPP data: 00.101172 061044 absolute read >>CPP cmd: Executing Clear 000 >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040136 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 136 sent to bus >>GIC buf: Command byte 136 loaded into outbound FIFO count 1 >>GIC buf: Command byte 136 unloaded from outbound FIFO count 0 >>GIC xfer: 5EH | ATN | | | | | Talk 30 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040042 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 042 sent to bus >>GIC buf: Command byte 042 loaded into outbound FIFO count 1 >>GIC buf: Command byte 042 unloaded from outbound FIFO count 0 >>GIC xfer: 22H | ATN | | | | | Listen 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040160 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 160 sent to bus >>GIC buf: Command byte 160 loaded into outbound FIFO count 1 >>GIC buf: Command byte 160 unloaded from outbound FIFO count 0 >>GIC xfer: 70H | ATN | | | | | Secondary 10H >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 100000 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data EOI | 000 sent to bus >>GIC buf: EOI | data byte 000 loaded into outbound FIFO count 1 >>GIC buf: EOI | data byte 000 unloaded from outbound FIFO count 0 >>GIC xfer: 00H | | EOI | | | | Data (device 0 accepts) >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040004 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 004 sent to bus >>GIC buf: Command byte 004 loaded into outbound FIFO count 1 >>GIC buf: Command byte 004 unloaded from outbound FIFO count 0 >>GIC xfer: 04H | ATN | | | | | Selected device clear >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040077 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 077 sent to bus >>GIC buf: Command byte 077 loaded into outbound FIFO count 1 >>GIC buf: Command byte 077 unloaded from outbound FIFO count 0 >>GIC xfer: 3FH | ATN | | | | | Unlisten >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101173 002010 absolute read >>CPP data: 00.101174 000002 absolute read >>CPP cmd: Executing Write secondary 10 count 2 burst 1 address 00101115 chain 0 | record mode | left byte >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>CPP data: 00.101176 000000 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040136 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 136 sent to bus >>GIC buf: Command byte 136 loaded into outbound FIFO count 1 >>GIC buf: Command byte 136 unloaded from outbound FIFO count 0 >>GIC xfer: 5EH | ATN | | | | | Talk 30 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040042 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 042 sent to bus >>GIC buf: Command byte 042 loaded into outbound FIFO count 1 >>GIC buf: Command byte 042 unloaded from outbound FIFO count 0 >>GIC xfer: 22H | ATN | | | | | Listen 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040150 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 150 sent to bus >>GIC buf: Command byte 150 loaded into outbound FIFO count 1 >>GIC buf: Command byte 150 unloaded from outbound FIFO count 0 >>GIC xfer: 68H | ATN | | | | | Secondary 08H >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 6 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) status is parity freeze | REN | DMA inbound >>GIC imbus: Channel 11 returned data 000140 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000142 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is parity freeze | REN | DMA outbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 100002 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is IRQ | empty >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 8 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 8 (DMA bank) control is DMA disabled | bank 000 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.101177 101115 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 9 data 101115 with signals ADO | DDO | PRI >>GIC csrw: Register 9 (DMA address) control is address 101115 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register A data 000002 with signals ADO | DDO | PRI >>GIC csrw: Register A (DMA byte count) control is byte count 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.000553 100000 absolute read >>CPP data: 00.000553 100002 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register B data 000022 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) control is left byte | outbound | device 2 >>IMBA imbus: Memory controller received opcode Memory Read address 00101115 data 000000 with signals ADO | DDO | PRI >>IMBA data: 00.101115 001401 dma read >>IMBA imbus: Memory controller returned data 001401 with signals ADN | DDN | PRO >>GIC buf: Data byte 003 loaded into outbound FIFO count 1 >>GIC buf: EOI | data byte 001 loaded into outbound FIFO count 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.000550 101173 absolute write >>CPP serv: Channel processor rescheduled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | CSRQ1 | PRO >>CPP cmd: Channel processor servicing channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBSI register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000532 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>CPP data: 00.000553 100002 absolute read >>CPP data: 00.000550 101173 absolute read >>CPP data: 00.101173 002010 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101176 000000 absolute read >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register A data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register A (DMA byte count) status is byte count 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101174 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 9 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 9 (DMA address) status is address 101116 >>GIC imbus: Channel 11 returned data 101116 with signals ADN | DDN | PRO >>CPP data: 00.101177 101116 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register B data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) status is left byte | outbound | end state 0 | device 2 >>GIC imbus: Channel 11 returned data 000022 with signals ADN | DDN | PRO >>CPP data: 00.101176 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000140 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is parity freeze | REN | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040077 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 077 sent to bus >>GIC buf: Command byte 077 loaded into outbound FIFO count 3 >>GIC buf: Data byte 003 unloaded from outbound FIFO count 2 >>GIC xfer: 03H | | | | | | Data (device 0 accepts) >>GIC buf: EOI | data byte 001 unloaded from outbound FIFO count 1 >>GIC xfer: 01H | | EOI | | | | Data (device 0 accepts) >>GIC buf: Command byte 077 unloaded from outbound FIFO count 0 >>GIC xfer: 3FH | ATN | | | | | Unlisten >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000550 101200 absolute write >>CPP data: 00.000550 101200 absolute read >>CPP data: 00.101200 001410 absolute read >>CPP data: 00.101201 000004 absolute read >>CPP cmd: Executing Read secondary 10 count 4 burst 1 address 00101113 chain 0 termination 101205 | record mode | left byte >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>CPP data: 00.101203 000000 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040076 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 076 sent to bus >>GIC buf: Command byte 076 loaded into outbound FIFO count 1 >>GIC buf: Command byte 076 unloaded from outbound FIFO count 0 >>GIC xfer: 3EH | ATN | | | | | Listen 30 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040102 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 102 sent to bus >>GIC buf: Command byte 102 loaded into outbound FIFO count 1 >>GIC buf: Command byte 102 unloaded from outbound FIFO count 0 >>GIC xfer: 42H | ATN | | | | | Talk 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040150 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 150 sent to bus >>GIC buf: Command byte 150 loaded into outbound FIFO count 1 >>GIC buf: Command byte 150 unloaded from outbound FIFO count 0 >>GIC xfer: 68H | ATN | | | | | Secondary 08H >>GIC xfer: 00H | | | | | | Data (device 30 accepts) >>GIC buf: Data byte 000 loaded into inbound FIFO count 1 >>GIC xfer: 00H | | | | | | Data (device 30 accepts) >>GIC buf: Data byte 000 loaded into inbound FIFO count 2 >>GIC xfer: 02H | | | | | | Data (device 30 accepts) >>GIC buf: Data byte 002 loaded into inbound FIFO count 3 >>GIC xfer: 00H | | | | | | Data (device 30 accepts) >>GIC buf: Data byte 000 loaded into inbound FIFO count 4 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 140000 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Reception enabled >>GIC buf: Transfer count 000 loaded into outbound FIFO count 1 >>GIC buf: Transfer count 000 unloaded from outbound FIFO count 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 8 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 8 (DMA bank) control is DMA disabled | bank 000 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101204 101113 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 9 data 101113 with signals ADO | DDO | PRI >>GIC csrw: Register 9 (DMA address) control is address 101113 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register A data 000004 with signals ADO | DDO | PRI >>GIC csrw: Register A (DMA byte count) control is byte count 4 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000553 100002 absolute read >>CPP data: 00.000553 100002 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register B data 000002 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) control is left byte | inbound | device 2 >>GIC buf: Data byte 000 unloaded from inbound FIFO count 3 >>GIC buf: Data byte 000 unloaded from inbound FIFO count 2 >>IMBA imbus: Memory controller received opcode Memory Write address 00101113 data 000000 with signals ADO | DDO | PRI >>IMBA data: 00.101113 000000 dma write >>IMBA imbus: Memory controller returned data 000000 with signals ADN | DDN | PRO >>GIC buf: Data byte 002 unloaded from inbound FIFO count 1 >>GIC buf: Data byte 000 unloaded from inbound FIFO count 0 >>IMBA imbus: Memory controller received opcode Memory Write address 00101114 data 001000 with signals ADO | DDO | PRI >>IMBA data: 00.101114 001000 dma write >>IMBA imbus: Memory controller returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>CPP data: 00.000550 101200 absolute write >>CPP serv: Channel processor rescheduled >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | CSRQ1 | PRO >>CPP cmd: Channel processor servicing channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBSI register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000532 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>CPP data: 00.000553 100002 absolute read >>CPP data: 00.000550 101200 absolute read >>CPP data: 00.101200 001410 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101203 000000 absolute read >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register A data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register A (DMA byte count) status is byte count 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101201 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 9 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 9 (DMA address) status is address 101115 >>GIC imbus: Channel 11 returned data 101115 with signals ADN | DDN | PRO >>CPP data: 00.101204 101115 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register B data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) status is left byte | inbound | end state 0 | device 2 >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>CPP data: 00.101203 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register B data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) status is left byte | inbound | end state 0 | device 2 >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register B data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) status is left byte | inbound | end state 0 | device 2 >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040137 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 137 sent to bus >>GIC buf: Command byte 137 loaded into outbound FIFO count 1 >>GIC buf: Command byte 137 unloaded from outbound FIFO count 0 >>GIC xfer: 5FH | ATN | | | | | Untalk >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040077 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 077 sent to bus >>GIC buf: Command byte 077 loaded into outbound FIFO count 1 >>GIC buf: Command byte 077 unloaded from outbound FIFO count 0 >>GIC xfer: 3FH | ATN | | | | | Unlisten >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000550 101205 absolute write >>CPP data: 00.000550 101205 absolute read >>CPP data: 00.101205 000601 absolute read >>CPP data: 00.101206 000001 absolute read >>CPP cmd: Executing Interrupt/Halt 0001 | CPVA 1 >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>CPP data: 00.000552 101104 absolute read >>CPP data: 00.101105 100001 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register C data 000012 with signals ADO | DDO | PRI >>GIC csrw: Register C (Interrupt) control is set | device 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | IRQ | PRO >>GIC imbus: Channel 11 asserts IRQ >>CPP serv: Program delay 1 service scheduled >>CPP data: 00.000553 100002 absolute read >>CPP data: 00.000553 000000 absolute write >>CPP data: 00.000550 101207 absolute write >>CPP serv: Channel processor rescheduled >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command IPOLL register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | IRQ | PRO >>CPP cmd: Channel processor interrupted by channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBII register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000132 with signals ADN | DDN | IRQ | PRO >>IMBA imbus: Channel 1 received opcode I/O Write command WIOC register 0 data 000132 with signals ADO | DDO | PRI >>IOP irq: Device number 125 asserted INTREQ at priority 12 >>IMBA imbus: Channel 1 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register C data 000002 with signals ADO | DDO | PRI >>GIC csrw: Register C (Interrupt) control is clear | device 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Channel processor idled >>IMBA iobus: Received data 000000 with signals INTPOLLIN >>IMBA iobus: Returned data 000132 with signals INTACK >>IOP irq: Device number 125 acknowledged interrupt request at priority 12 >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000004 absolute read >>CPP cmd: Channel processor executing SED2 >>CPP data: 00.000771 000001 absolute read >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Reset Interrupt order sent to device number 90 >>IMBA iobus: Received data 000000 with signals DRESETINT >>IMBA iobus: Returned data 000000 with signals (none) >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000003 absolute read >>CPP cmd: Channel processor executing WIOC >>CPP data: 00.000771 100000 absolute read >>CPP data: 00.000772 000020 absolute read >>CPP data: 00.000103 000000 absolute read >>IMBA imbus: Channel 1 received opcode I/O Write command SMSK register 0 data 000020 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command SMSK register 0 data 000020 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000000 absolute read >>CPP cmd: Channel processor executing SIOP >>CPP data: 00.000771 000132 absolute read >>CPP data: 00.000773 101171 absolute read >>CPP data: 00.000553 000000 absolute read >>CPP data: 00.000550 101171 absolute write >>CPP data: 00.000553 140000 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command SIOP register 0 data 000002 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>CPP opnd: 00.101171 004400 Clear 000 >>CPP opnd: 00.101173 002010 Write secondary 10 count 2 burst 1 address 00101115 chain 0 | record mode | left byte >>CPP opnd: 00.101200 001410 Read secondary 10 count 4 burst 1 address 00101113 chain 0 termination 101205 | record mode | left byte >>CPP opnd: 00.101205 000601 Interrupt/Halt 0001 | CPVA 1 >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor rescheduled >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | CSRQ1 | PRO >>CPP cmd: Channel processor servicing channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBSI register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 001132 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.000553 140000 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command SIOP register 0 data 000012 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000140 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is parity freeze | REN | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 4 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 4 (Poll mask) status is PP 0 | PP 1 | PP 2 >>GIC imbus: Channel 11 returned data 000340 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 4 data 000340 with signals ADO | DDO | PRI >>GIC csrw: Register 4 (Poll mask) control is PP 0 | PP 1 | PP 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register F data 000002 with signals ADO | DDO | PRI >>GIC csrw: Register F (Service info) control is DMA inbound | device 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000553 100000 absolute write >>CPP data: 00.000550 101171 absolute read >>CPP data: 00.101171 004400 absolute read >>CPP data: 00.101172 061044 absolute read >>CPP cmd: Executing Clear 000 >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040136 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 136 sent to bus >>GIC buf: Command byte 136 loaded into outbound FIFO count 1 >>GIC buf: Command byte 136 unloaded from outbound FIFO count 0 >>GIC xfer: 5EH | ATN | | | | | Talk 30 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040042 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 042 sent to bus >>GIC buf: Command byte 042 loaded into outbound FIFO count 1 >>GIC buf: Command byte 042 unloaded from outbound FIFO count 0 >>GIC xfer: 22H | ATN | | | | | Listen 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040160 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 160 sent to bus >>GIC buf: Command byte 160 loaded into outbound FIFO count 1 >>GIC buf: Command byte 160 unloaded from outbound FIFO count 0 >>GIC xfer: 70H | ATN | | | | | Secondary 10H >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 100000 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data EOI | 000 sent to bus >>GIC buf: EOI | data byte 000 loaded into outbound FIFO count 1 >>GIC buf: EOI | data byte 000 unloaded from outbound FIFO count 0 >>GIC xfer: 00H | | EOI | | | | Data (device 0 accepts) >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040004 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 004 sent to bus >>GIC buf: Command byte 004 loaded into outbound FIFO count 1 >>GIC buf: Command byte 004 unloaded from outbound FIFO count 0 >>GIC xfer: 04H | ATN | | | | | Selected device clear >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040077 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 077 sent to bus >>GIC buf: Command byte 077 loaded into outbound FIFO count 1 >>GIC buf: Command byte 077 unloaded from outbound FIFO count 0 >>GIC xfer: 3FH | ATN | | | | | Unlisten >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101173 002010 absolute read >>CPP data: 00.101174 000002 absolute read >>CPP cmd: Executing Write secondary 10 count 2 burst 1 address 00101115 chain 0 | record mode | left byte >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>CPP data: 00.101176 000000 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040136 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 136 sent to bus >>GIC buf: Command byte 136 loaded into outbound FIFO count 1 >>GIC buf: Command byte 136 unloaded from outbound FIFO count 0 >>GIC xfer: 5EH | ATN | | | | | Talk 30 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040042 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 042 sent to bus >>GIC buf: Command byte 042 loaded into outbound FIFO count 1 >>GIC buf: Command byte 042 unloaded from outbound FIFO count 0 >>GIC xfer: 22H | ATN | | | | | Listen 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040150 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 150 sent to bus >>GIC buf: Command byte 150 loaded into outbound FIFO count 1 >>GIC buf: Command byte 150 unloaded from outbound FIFO count 0 >>GIC xfer: 68H | ATN | | | | | Secondary 08H >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 6 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) status is parity freeze | REN | DMA inbound >>GIC imbus: Channel 11 returned data 000140 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000142 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is parity freeze | REN | DMA outbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 100002 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is IRQ | empty >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 8 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 8 (DMA bank) control is DMA disabled | bank 000 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.101177 101115 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 9 data 101115 with signals ADO | DDO | PRI >>GIC csrw: Register 9 (DMA address) control is address 101115 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register A data 000002 with signals ADO | DDO | PRI >>GIC csrw: Register A (DMA byte count) control is byte count 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.000553 100000 absolute read >>CPP data: 00.000553 100002 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register B data 000022 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) control is left byte | outbound | device 2 >>IMBA imbus: Memory controller received opcode Memory Read address 00101115 data 000000 with signals ADO | DDO | PRI >>IMBA data: 00.101115 001402 dma read >>IMBA imbus: Memory controller returned data 001402 with signals ADN | DDN | PRO >>GIC buf: Data byte 003 loaded into outbound FIFO count 1 >>GIC buf: EOI | data byte 002 loaded into outbound FIFO count 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.000550 101173 absolute write >>CPP serv: Channel processor rescheduled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | CSRQ1 | PRO >>CPP cmd: Channel processor servicing channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBSI register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000532 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>CPP data: 00.000553 100002 absolute read >>CPP data: 00.000550 101173 absolute read >>CPP data: 00.101173 002010 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101176 000000 absolute read >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register A data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register A (DMA byte count) status is byte count 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101174 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 9 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 9 (DMA address) status is address 101116 >>GIC imbus: Channel 11 returned data 101116 with signals ADN | DDN | PRO >>CPP data: 00.101177 101116 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register B data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) status is left byte | outbound | end state 0 | device 2 >>GIC imbus: Channel 11 returned data 000022 with signals ADN | DDN | PRO >>CPP data: 00.101176 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000140 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is parity freeze | REN | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040077 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 077 sent to bus >>GIC buf: Command byte 077 loaded into outbound FIFO count 3 >>GIC buf: Data byte 003 unloaded from outbound FIFO count 2 >>GIC xfer: 03H | | | | | | Data (device 0 accepts) >>GIC buf: EOI | data byte 002 unloaded from outbound FIFO count 1 >>GIC xfer: 02H | | EOI | | | | Data (device 0 accepts) >>GIC buf: Command byte 077 unloaded from outbound FIFO count 0 >>GIC xfer: 3FH | ATN | | | | | Unlisten >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000550 101200 absolute write >>CPP data: 00.000550 101200 absolute read >>CPP data: 00.101200 001410 absolute read >>CPP data: 00.101201 000004 absolute read >>CPP cmd: Executing Read secondary 10 count 4 burst 1 address 00101113 chain 0 termination 101205 | record mode | left byte >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>CPP data: 00.101203 000000 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040076 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 076 sent to bus >>GIC buf: Command byte 076 loaded into outbound FIFO count 1 >>GIC buf: Command byte 076 unloaded from outbound FIFO count 0 >>GIC xfer: 3EH | ATN | | | | | Listen 30 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040102 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 102 sent to bus >>GIC buf: Command byte 102 loaded into outbound FIFO count 1 >>GIC buf: Command byte 102 unloaded from outbound FIFO count 0 >>GIC xfer: 42H | ATN | | | | | Talk 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040150 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 150 sent to bus >>GIC buf: Command byte 150 loaded into outbound FIFO count 1 >>GIC buf: Command byte 150 unloaded from outbound FIFO count 0 >>GIC xfer: 68H | ATN | | | | | Secondary 08H >>GIC xfer: 00H | | | | | | Data (device 30 accepts) >>GIC buf: Data byte 000 loaded into inbound FIFO count 1 >>GIC xfer: 00H | | | | | | Data (device 30 accepts) >>GIC buf: Data byte 000 loaded into inbound FIFO count 2 >>GIC xfer: 02H | | | | | | Data (device 30 accepts) >>GIC buf: Data byte 002 loaded into inbound FIFO count 3 >>GIC xfer: 00H | | | | | | Data (device 30 accepts) >>GIC buf: Data byte 000 loaded into inbound FIFO count 4 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 140000 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Reception enabled >>GIC buf: Transfer count 000 loaded into outbound FIFO count 1 >>GIC buf: Transfer count 000 unloaded from outbound FIFO count 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 8 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 8 (DMA bank) control is DMA disabled | bank 000 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101204 101113 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 9 data 101113 with signals ADO | DDO | PRI >>GIC csrw: Register 9 (DMA address) control is address 101113 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register A data 000004 with signals ADO | DDO | PRI >>GIC csrw: Register A (DMA byte count) control is byte count 4 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000553 100002 absolute read >>CPP data: 00.000553 100002 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register B data 000002 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) control is left byte | inbound | device 2 >>GIC buf: Data byte 000 unloaded from inbound FIFO count 3 >>GIC buf: Data byte 000 unloaded from inbound FIFO count 2 >>IMBA imbus: Memory controller received opcode Memory Write address 00101113 data 000000 with signals ADO | DDO | PRI >>IMBA data: 00.101113 000000 dma write >>IMBA imbus: Memory controller returned data 000000 with signals ADN | DDN | PRO >>GIC buf: Data byte 002 unloaded from inbound FIFO count 1 >>GIC buf: Data byte 000 unloaded from inbound FIFO count 0 >>IMBA imbus: Memory controller received opcode Memory Write address 00101114 data 001000 with signals ADO | DDO | PRI >>IMBA data: 00.101114 001000 dma write >>IMBA imbus: Memory controller returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>CPP data: 00.000550 101200 absolute write >>CPP serv: Channel processor rescheduled >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | CSRQ1 | PRO >>CPP cmd: Channel processor servicing channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBSI register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000532 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>CPP data: 00.000553 100002 absolute read >>CPP data: 00.000550 101200 absolute read >>CPP data: 00.101200 001410 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101203 000000 absolute read >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register A data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register A (DMA byte count) status is byte count 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101201 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 9 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 9 (DMA address) status is address 101115 >>GIC imbus: Channel 11 returned data 101115 with signals ADN | DDN | PRO >>CPP data: 00.101204 101115 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register B data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) status is left byte | inbound | end state 0 | device 2 >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>CPP data: 00.101203 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register B data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) status is left byte | inbound | end state 0 | device 2 >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register B data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) status is left byte | inbound | end state 0 | device 2 >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040137 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 137 sent to bus >>GIC buf: Command byte 137 loaded into outbound FIFO count 1 >>GIC buf: Command byte 137 unloaded from outbound FIFO count 0 >>GIC xfer: 5FH | ATN | | | | | Untalk >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040077 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 077 sent to bus >>GIC buf: Command byte 077 loaded into outbound FIFO count 1 >>GIC buf: Command byte 077 unloaded from outbound FIFO count 0 >>GIC xfer: 3FH | ATN | | | | | Unlisten >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000550 101205 absolute write >>CPP data: 00.000550 101205 absolute read >>CPP data: 00.101205 000601 absolute read >>CPP data: 00.101206 000001 absolute read >>CPP cmd: Executing Interrupt/Halt 0001 | CPVA 1 >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>CPP data: 00.000552 101104 absolute read >>CPP data: 00.101105 100001 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register C data 000012 with signals ADO | DDO | PRI >>GIC csrw: Register C (Interrupt) control is set | device 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | IRQ | PRO >>GIC imbus: Channel 11 asserts IRQ >>CPP serv: Program delay 1 service scheduled >>CPP data: 00.000553 100002 absolute read >>CPP data: 00.000553 000000 absolute write >>CPP data: 00.000550 101207 absolute write >>CPP serv: Channel processor rescheduled >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command IPOLL register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | IRQ | PRO >>CPP cmd: Channel processor interrupted by channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBII register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000132 with signals ADN | DDN | IRQ | PRO >>IMBA imbus: Channel 1 received opcode I/O Write command WIOC register 0 data 000132 with signals ADO | DDO | PRI >>IOP irq: Device number 125 asserted INTREQ at priority 12 >>IMBA imbus: Channel 1 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register C data 000002 with signals ADO | DDO | PRI >>GIC csrw: Register C (Interrupt) control is clear | device 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Channel processor idled >>IMBA iobus: Received data 000000 with signals INTPOLLIN >>IMBA iobus: Returned data 000132 with signals INTACK >>IOP irq: Device number 125 acknowledged interrupt request at priority 12 >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000004 absolute read >>CPP cmd: Channel processor executing SED2 >>CPP data: 00.000771 000001 absolute read >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Reset Interrupt order sent to device number 90 >>IMBA iobus: Received data 000000 with signals DRESETINT >>IMBA iobus: Returned data 000000 with signals (none) >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000003 absolute read >>CPP cmd: Channel processor executing WIOC >>CPP data: 00.000771 100000 absolute read >>CPP data: 00.000772 000020 absolute read >>CPP data: 00.000103 000000 absolute read >>IMBA imbus: Channel 1 received opcode I/O Write command SMSK register 0 data 000020 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command SMSK register 0 data 000020 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000000 absolute read >>CPP cmd: Channel processor executing SIOP >>CPP data: 00.000771 000132 absolute read >>CPP data: 00.000773 101171 absolute read >>CPP data: 00.000553 000000 absolute read >>CPP data: 00.000550 101171 absolute write >>CPP data: 00.000553 140000 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command SIOP register 0 data 000002 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>CPP opnd: 00.101171 004400 Clear 000 >>CPP opnd: 00.101173 002010 Write secondary 10 count 2 burst 1 address 00101115 chain 0 | record mode | left byte >>CPP opnd: 00.101200 001410 Read secondary 10 count 4 burst 1 address 00101113 chain 0 termination 101205 | record mode | left byte >>CPP opnd: 00.101205 000601 Interrupt/Halt 0001 | CPVA 1 >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor rescheduled >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | CSRQ1 | PRO >>CPP cmd: Channel processor servicing channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBSI register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 001132 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.000553 140000 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command SIOP register 0 data 000012 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000140 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is parity freeze | REN | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 4 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 4 (Poll mask) status is PP 0 | PP 1 | PP 2 >>GIC imbus: Channel 11 returned data 000340 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 4 data 000340 with signals ADO | DDO | PRI >>GIC csrw: Register 4 (Poll mask) control is PP 0 | PP 1 | PP 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register F data 000002 with signals ADO | DDO | PRI >>GIC csrw: Register F (Service info) control is DMA inbound | device 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000553 100000 absolute write >>CPP data: 00.000550 101171 absolute read >>CPP data: 00.101171 004400 absolute read >>CPP data: 00.101172 061044 absolute read >>CPP cmd: Executing Clear 000 >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040136 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 136 sent to bus >>GIC buf: Command byte 136 loaded into outbound FIFO count 1 >>GIC buf: Command byte 136 unloaded from outbound FIFO count 0 >>GIC xfer: 5EH | ATN | | | | | Talk 30 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040042 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 042 sent to bus >>GIC buf: Command byte 042 loaded into outbound FIFO count 1 >>GIC buf: Command byte 042 unloaded from outbound FIFO count 0 >>GIC xfer: 22H | ATN | | | | | Listen 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040160 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 160 sent to bus >>GIC buf: Command byte 160 loaded into outbound FIFO count 1 >>GIC buf: Command byte 160 unloaded from outbound FIFO count 0 >>GIC xfer: 70H | ATN | | | | | Secondary 10H >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 100000 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data EOI | 000 sent to bus >>GIC buf: EOI | data byte 000 loaded into outbound FIFO count 1 >>GIC buf: EOI | data byte 000 unloaded from outbound FIFO count 0 >>GIC xfer: 00H | | EOI | | | | Data (device 0 accepts) >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040004 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 004 sent to bus >>GIC buf: Command byte 004 loaded into outbound FIFO count 1 >>GIC buf: Command byte 004 unloaded from outbound FIFO count 0 >>GIC xfer: 04H | ATN | | | | | Selected device clear >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040077 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 077 sent to bus >>GIC buf: Command byte 077 loaded into outbound FIFO count 1 >>GIC buf: Command byte 077 unloaded from outbound FIFO count 0 >>GIC xfer: 3FH | ATN | | | | | Unlisten >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101173 002010 absolute read >>CPP data: 00.101174 000002 absolute read >>CPP cmd: Executing Write secondary 10 count 2 burst 1 address 00101115 chain 0 | record mode | left byte >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>CPP data: 00.101176 000000 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040136 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 136 sent to bus >>GIC buf: Command byte 136 loaded into outbound FIFO count 1 >>GIC buf: Command byte 136 unloaded from outbound FIFO count 0 >>GIC xfer: 5EH | ATN | | | | | Talk 30 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040042 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 042 sent to bus >>GIC buf: Command byte 042 loaded into outbound FIFO count 1 >>GIC buf: Command byte 042 unloaded from outbound FIFO count 0 >>GIC xfer: 22H | ATN | | | | | Listen 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040150 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 150 sent to bus >>GIC buf: Command byte 150 loaded into outbound FIFO count 1 >>GIC buf: Command byte 150 unloaded from outbound FIFO count 0 >>GIC xfer: 68H | ATN | | | | | Secondary 08H >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 6 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) status is parity freeze | REN | DMA inbound >>GIC imbus: Channel 11 returned data 000140 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000142 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is parity freeze | REN | DMA outbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 100002 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is IRQ | empty >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 8 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 8 (DMA bank) control is DMA disabled | bank 000 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.101177 101115 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 9 data 101115 with signals ADO | DDO | PRI >>GIC csrw: Register 9 (DMA address) control is address 101115 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register A data 000002 with signals ADO | DDO | PRI >>GIC csrw: Register A (DMA byte count) control is byte count 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.000553 100000 absolute read >>CPP data: 00.000553 100002 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register B data 000022 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) control is left byte | outbound | device 2 >>IMBA imbus: Memory controller received opcode Memory Read address 00101115 data 000000 with signals ADO | DDO | PRI >>IMBA data: 00.101115 001403 dma read >>IMBA imbus: Memory controller returned data 001403 with signals ADN | DDN | PRO >>GIC buf: Data byte 003 loaded into outbound FIFO count 1 >>GIC buf: EOI | data byte 003 loaded into outbound FIFO count 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.000550 101173 absolute write >>CPP serv: Channel processor rescheduled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | CSRQ1 | PRO >>CPP cmd: Channel processor servicing channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBSI register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000532 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>CPP data: 00.000553 100002 absolute read >>CPP data: 00.000550 101173 absolute read >>CPP data: 00.101173 002010 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101176 000000 absolute read >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register A data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register A (DMA byte count) status is byte count 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101174 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 9 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 9 (DMA address) status is address 101116 >>GIC imbus: Channel 11 returned data 101116 with signals ADN | DDN | PRO >>CPP data: 00.101177 101116 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register B data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) status is left byte | outbound | end state 0 | device 2 >>GIC imbus: Channel 11 returned data 000022 with signals ADN | DDN | PRO >>CPP data: 00.101176 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000140 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is parity freeze | REN | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040077 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 077 sent to bus >>GIC buf: Command byte 077 loaded into outbound FIFO count 3 >>GIC buf: Data byte 003 unloaded from outbound FIFO count 2 >>GIC xfer: 03H | | | | | | Data (device 0 accepts) >>GIC buf: EOI | data byte 003 unloaded from outbound FIFO count 1 >>GIC xfer: 03H | | EOI | | | | Data (device 0 accepts) >>GIC buf: Command byte 077 unloaded from outbound FIFO count 0 >>GIC xfer: 3FH | ATN | | | | | Unlisten >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000550 101200 absolute write >>CPP data: 00.000550 101200 absolute read >>CPP data: 00.101200 001410 absolute read >>CPP data: 00.101201 000004 absolute read >>CPP cmd: Executing Read secondary 10 count 4 burst 1 address 00101113 chain 0 termination 101205 | record mode | left byte >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>CPP data: 00.101203 000000 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040076 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 076 sent to bus >>GIC buf: Command byte 076 loaded into outbound FIFO count 1 >>GIC buf: Command byte 076 unloaded from outbound FIFO count 0 >>GIC xfer: 3EH | ATN | | | | | Listen 30 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040102 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 102 sent to bus >>GIC buf: Command byte 102 loaded into outbound FIFO count 1 >>GIC buf: Command byte 102 unloaded from outbound FIFO count 0 >>GIC xfer: 42H | ATN | | | | | Talk 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040150 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 150 sent to bus >>GIC buf: Command byte 150 loaded into outbound FIFO count 1 >>GIC buf: Command byte 150 unloaded from outbound FIFO count 0 >>GIC xfer: 68H | ATN | | | | | Secondary 08H >>GIC xfer: 00H | | | | | | Data (device 30 accepts) >>GIC buf: Data byte 000 loaded into inbound FIFO count 1 >>GIC xfer: 00H | | | | | | Data (device 30 accepts) >>GIC buf: Data byte 000 loaded into inbound FIFO count 2 >>GIC xfer: 02H | | | | | | Data (device 30 accepts) >>GIC buf: Data byte 002 loaded into inbound FIFO count 3 >>GIC xfer: 00H | | | | | | Data (device 30 accepts) >>GIC buf: Data byte 000 loaded into inbound FIFO count 4 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 140000 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Reception enabled >>GIC buf: Transfer count 000 loaded into outbound FIFO count 1 >>GIC buf: Transfer count 000 unloaded from outbound FIFO count 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 8 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 8 (DMA bank) control is DMA disabled | bank 000 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101204 101113 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 9 data 101113 with signals ADO | DDO | PRI >>GIC csrw: Register 9 (DMA address) control is address 101113 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register A data 000004 with signals ADO | DDO | PRI >>GIC csrw: Register A (DMA byte count) control is byte count 4 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000553 100002 absolute read >>CPP data: 00.000553 100002 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register B data 000002 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) control is left byte | inbound | device 2 >>GIC buf: Data byte 000 unloaded from inbound FIFO count 3 >>GIC buf: Data byte 000 unloaded from inbound FIFO count 2 >>IMBA imbus: Memory controller received opcode Memory Write address 00101113 data 000000 with signals ADO | DDO | PRI >>IMBA data: 00.101113 000000 dma write >>IMBA imbus: Memory controller returned data 000000 with signals ADN | DDN | PRO >>GIC buf: Data byte 002 unloaded from inbound FIFO count 1 >>GIC buf: Data byte 000 unloaded from inbound FIFO count 0 >>IMBA imbus: Memory controller received opcode Memory Write address 00101114 data 001000 with signals ADO | DDO | PRI >>IMBA data: 00.101114 001000 dma write >>IMBA imbus: Memory controller returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>CPP data: 00.000550 101200 absolute write >>CPP serv: Channel processor rescheduled >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | CSRQ1 | PRO >>CPP cmd: Channel processor servicing channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBSI register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000532 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>CPP data: 00.000553 100002 absolute read >>CPP data: 00.000550 101200 absolute read >>CPP data: 00.101200 001410 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101203 000000 absolute read >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register A data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register A (DMA byte count) status is byte count 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101201 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 9 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 9 (DMA address) status is address 101115 >>GIC imbus: Channel 11 returned data 101115 with signals ADN | DDN | PRO >>CPP data: 00.101204 101115 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register B data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) status is left byte | inbound | end state 0 | device 2 >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>CPP data: 00.101203 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register B data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) status is left byte | inbound | end state 0 | device 2 >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register B data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) status is left byte | inbound | end state 0 | device 2 >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040137 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 137 sent to bus >>GIC buf: Command byte 137 loaded into outbound FIFO count 1 >>GIC buf: Command byte 137 unloaded from outbound FIFO count 0 >>GIC xfer: 5FH | ATN | | | | | Untalk >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040077 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 077 sent to bus >>GIC buf: Command byte 077 loaded into outbound FIFO count 1 >>GIC buf: Command byte 077 unloaded from outbound FIFO count 0 >>GIC xfer: 3FH | ATN | | | | | Unlisten >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000550 101205 absolute write >>CPP data: 00.000550 101205 absolute read >>CPP data: 00.101205 000601 absolute read >>CPP data: 00.101206 000001 absolute read >>CPP cmd: Executing Interrupt/Halt 0001 | CPVA 1 >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>CPP data: 00.000552 101104 absolute read >>CPP data: 00.101105 100001 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register C data 000012 with signals ADO | DDO | PRI >>GIC csrw: Register C (Interrupt) control is set | device 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | IRQ | PRO >>GIC imbus: Channel 11 asserts IRQ >>CPP serv: Program delay 1 service scheduled >>CPP data: 00.000553 100002 absolute read >>CPP data: 00.000553 000000 absolute write >>CPP data: 00.000550 101207 absolute write >>CPP serv: Channel processor rescheduled >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command IPOLL register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | IRQ | PRO >>CPP cmd: Channel processor interrupted by channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBII register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000132 with signals ADN | DDN | IRQ | PRO >>IMBA imbus: Channel 1 received opcode I/O Write command WIOC register 0 data 000132 with signals ADO | DDO | PRI >>IOP irq: Device number 125 asserted INTREQ at priority 12 >>IMBA imbus: Channel 1 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register C data 000002 with signals ADO | DDO | PRI >>GIC csrw: Register C (Interrupt) control is clear | device 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Channel processor idled >>IMBA iobus: Received data 000000 with signals INTPOLLIN >>IMBA iobus: Returned data 000132 with signals INTACK >>IOP irq: Device number 125 acknowledged interrupt request at priority 12 >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000004 absolute read >>CPP cmd: Channel processor executing SED2 >>CPP data: 00.000771 000001 absolute read >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Reset Interrupt order sent to device number 90 >>IMBA iobus: Received data 000000 with signals DRESETINT >>IMBA iobus: Returned data 000000 with signals (none) >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000003 absolute read >>CPP cmd: Channel processor executing WIOC >>CPP data: 00.000771 100000 absolute read >>CPP data: 00.000772 000020 absolute read >>CPP data: 00.000103 000000 absolute read >>IMBA imbus: Channel 1 received opcode I/O Write command SMSK register 0 data 000020 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command SMSK register 0 data 000020 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000000 absolute read >>CPP cmd: Channel processor executing SIOP >>CPP data: 00.000771 000132 absolute read >>CPP data: 00.000773 101171 absolute read >>CPP data: 00.000553 000000 absolute read >>CPP data: 00.000550 101171 absolute write >>CPP data: 00.000553 140000 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command SIOP register 0 data 000002 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>CPP opnd: 00.101171 004400 Clear 000 >>CPP opnd: 00.101173 002010 Write secondary 10 count 2 burst 1 address 00101115 chain 0 | record mode | left byte >>CPP opnd: 00.101200 001410 Read secondary 10 count 4 burst 1 address 00101113 chain 0 termination 101205 | record mode | left byte >>CPP opnd: 00.101205 000601 Interrupt/Halt 0001 | CPVA 1 >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor rescheduled >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | CSRQ1 | PRO >>CPP cmd: Channel processor servicing channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBSI register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 001132 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.000553 140000 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command SIOP register 0 data 000012 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000140 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is parity freeze | REN | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 4 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 4 (Poll mask) status is PP 0 | PP 1 | PP 2 >>GIC imbus: Channel 11 returned data 000340 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 4 data 000340 with signals ADO | DDO | PRI >>GIC csrw: Register 4 (Poll mask) control is PP 0 | PP 1 | PP 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register F data 000002 with signals ADO | DDO | PRI >>GIC csrw: Register F (Service info) control is DMA inbound | device 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000553 100000 absolute write >>CPP data: 00.000550 101171 absolute read >>CPP data: 00.101171 004400 absolute read >>CPP data: 00.101172 061044 absolute read >>CPP cmd: Executing Clear 000 >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040136 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 136 sent to bus >>GIC buf: Command byte 136 loaded into outbound FIFO count 1 >>GIC buf: Command byte 136 unloaded from outbound FIFO count 0 >>GIC xfer: 5EH | ATN | | | | | Talk 30 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040042 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 042 sent to bus >>GIC buf: Command byte 042 loaded into outbound FIFO count 1 >>GIC buf: Command byte 042 unloaded from outbound FIFO count 0 >>GIC xfer: 22H | ATN | | | | | Listen 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040160 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 160 sent to bus >>GIC buf: Command byte 160 loaded into outbound FIFO count 1 >>GIC buf: Command byte 160 unloaded from outbound FIFO count 0 >>GIC xfer: 70H | ATN | | | | | Secondary 10H >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 100000 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data EOI | 000 sent to bus >>GIC buf: EOI | data byte 000 loaded into outbound FIFO count 1 >>GIC buf: EOI | data byte 000 unloaded from outbound FIFO count 0 >>GIC xfer: 00H | | EOI | | | | Data (device 0 accepts) >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040004 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 004 sent to bus >>GIC buf: Command byte 004 loaded into outbound FIFO count 1 >>GIC buf: Command byte 004 unloaded from outbound FIFO count 0 >>GIC xfer: 04H | ATN | | | | | Selected device clear >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040077 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 077 sent to bus >>GIC buf: Command byte 077 loaded into outbound FIFO count 1 >>GIC buf: Command byte 077 unloaded from outbound FIFO count 0 >>GIC xfer: 3FH | ATN | | | | | Unlisten >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101173 002010 absolute read >>CPP data: 00.101174 000002 absolute read >>CPP cmd: Executing Write secondary 10 count 2 burst 1 address 00101115 chain 0 | record mode | left byte >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>CPP data: 00.101176 000000 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040136 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 136 sent to bus >>GIC buf: Command byte 136 loaded into outbound FIFO count 1 >>GIC buf: Command byte 136 unloaded from outbound FIFO count 0 >>GIC xfer: 5EH | ATN | | | | | Talk 30 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040042 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 042 sent to bus >>GIC buf: Command byte 042 loaded into outbound FIFO count 1 >>GIC buf: Command byte 042 unloaded from outbound FIFO count 0 >>GIC xfer: 22H | ATN | | | | | Listen 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040150 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 150 sent to bus >>GIC buf: Command byte 150 loaded into outbound FIFO count 1 >>GIC buf: Command byte 150 unloaded from outbound FIFO count 0 >>GIC xfer: 68H | ATN | | | | | Secondary 08H >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 6 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) status is parity freeze | REN | DMA inbound >>GIC imbus: Channel 11 returned data 000140 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000142 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is parity freeze | REN | DMA outbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 100002 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is IRQ | empty >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 8 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 8 (DMA bank) control is DMA disabled | bank 000 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.101177 101115 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 9 data 101115 with signals ADO | DDO | PRI >>GIC csrw: Register 9 (DMA address) control is address 101115 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register A data 000002 with signals ADO | DDO | PRI >>GIC csrw: Register A (DMA byte count) control is byte count 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.000553 100000 absolute read >>CPP data: 00.000553 100002 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register B data 000022 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) control is left byte | outbound | device 2 >>IMBA imbus: Memory controller received opcode Memory Read address 00101115 data 000000 with signals ADO | DDO | PRI >>IMBA data: 00.101115 001404 dma read >>IMBA imbus: Memory controller returned data 001404 with signals ADN | DDN | PRO >>GIC buf: Data byte 003 loaded into outbound FIFO count 1 >>GIC buf: EOI | data byte 004 loaded into outbound FIFO count 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.000550 101173 absolute write >>CPP serv: Channel processor rescheduled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | CSRQ1 | PRO >>CPP cmd: Channel processor servicing channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBSI register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000532 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>CPP data: 00.000553 100002 absolute read >>CPP data: 00.000550 101173 absolute read >>CPP data: 00.101173 002010 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101176 000000 absolute read >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register A data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register A (DMA byte count) status is byte count 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101174 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 9 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 9 (DMA address) status is address 101116 >>GIC imbus: Channel 11 returned data 101116 with signals ADN | DDN | PRO >>CPP data: 00.101177 101116 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register B data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) status is left byte | outbound | end state 0 | device 2 >>GIC imbus: Channel 11 returned data 000022 with signals ADN | DDN | PRO >>CPP data: 00.101176 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000140 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is parity freeze | REN | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040077 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 077 sent to bus >>GIC buf: Command byte 077 loaded into outbound FIFO count 3 >>GIC buf: Data byte 003 unloaded from outbound FIFO count 2 >>GIC xfer: 03H | | | | | | Data (device 0 accepts) >>GIC buf: EOI | data byte 004 unloaded from outbound FIFO count 1 >>GIC xfer: 04H | | EOI | | | | Data (device 0 accepts) >>GIC buf: Command byte 077 unloaded from outbound FIFO count 0 >>GIC xfer: 3FH | ATN | | | | | Unlisten >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000550 101200 absolute write >>CPP data: 00.000550 101200 absolute read >>CPP data: 00.101200 001410 absolute read >>CPP data: 00.101201 000004 absolute read >>CPP cmd: Executing Read secondary 10 count 4 burst 1 address 00101113 chain 0 termination 101205 | record mode | left byte >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>CPP data: 00.101203 000000 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040076 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 076 sent to bus >>GIC buf: Command byte 076 loaded into outbound FIFO count 1 >>GIC buf: Command byte 076 unloaded from outbound FIFO count 0 >>GIC xfer: 3EH | ATN | | | | | Listen 30 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040102 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 102 sent to bus >>GIC buf: Command byte 102 loaded into outbound FIFO count 1 >>GIC buf: Command byte 102 unloaded from outbound FIFO count 0 >>GIC xfer: 42H | ATN | | | | | Talk 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040150 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 150 sent to bus >>GIC buf: Command byte 150 loaded into outbound FIFO count 1 >>GIC buf: Command byte 150 unloaded from outbound FIFO count 0 >>GIC xfer: 68H | ATN | | | | | Secondary 08H >>GIC xfer: 00H | | | | | | Data (device 30 accepts) >>GIC buf: Data byte 000 loaded into inbound FIFO count 1 >>GIC xfer: 00H | | | | | | Data (device 30 accepts) >>GIC buf: Data byte 000 loaded into inbound FIFO count 2 >>GIC xfer: 02H | | | | | | Data (device 30 accepts) >>GIC buf: Data byte 002 loaded into inbound FIFO count 3 >>GIC xfer: 00H | | | | | | Data (device 30 accepts) >>GIC buf: Data byte 000 loaded into inbound FIFO count 4 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 140000 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Reception enabled >>GIC buf: Transfer count 000 loaded into outbound FIFO count 1 >>GIC buf: Transfer count 000 unloaded from outbound FIFO count 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 8 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 8 (DMA bank) control is DMA disabled | bank 000 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101204 101113 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 9 data 101113 with signals ADO | DDO | PRI >>GIC csrw: Register 9 (DMA address) control is address 101113 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register A data 000004 with signals ADO | DDO | PRI >>GIC csrw: Register A (DMA byte count) control is byte count 4 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000553 100002 absolute read >>CPP data: 00.000553 100002 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register B data 000002 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) control is left byte | inbound | device 2 >>GIC buf: Data byte 000 unloaded from inbound FIFO count 3 >>GIC buf: Data byte 000 unloaded from inbound FIFO count 2 >>IMBA imbus: Memory controller received opcode Memory Write address 00101113 data 000000 with signals ADO | DDO | PRI >>IMBA data: 00.101113 000000 dma write >>IMBA imbus: Memory controller returned data 000000 with signals ADN | DDN | PRO >>GIC buf: Data byte 002 unloaded from inbound FIFO count 1 >>GIC buf: Data byte 000 unloaded from inbound FIFO count 0 >>IMBA imbus: Memory controller received opcode Memory Write address 00101114 data 001000 with signals ADO | DDO | PRI >>IMBA data: 00.101114 001000 dma write >>IMBA imbus: Memory controller returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>CPP data: 00.000550 101200 absolute write >>CPP serv: Channel processor rescheduled >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | CSRQ1 | PRO >>CPP cmd: Channel processor servicing channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBSI register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000532 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>CPP data: 00.000553 100002 absolute read >>CPP data: 00.000550 101200 absolute read >>CPP data: 00.101200 001410 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101203 000000 absolute read >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register A data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register A (DMA byte count) status is byte count 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101201 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 9 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 9 (DMA address) status is address 101115 >>GIC imbus: Channel 11 returned data 101115 with signals ADN | DDN | PRO >>CPP data: 00.101204 101115 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register B data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) status is left byte | inbound | end state 0 | device 2 >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>CPP data: 00.101203 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register B data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) status is left byte | inbound | end state 0 | device 2 >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register B data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) status is left byte | inbound | end state 0 | device 2 >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040137 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 137 sent to bus >>GIC buf: Command byte 137 loaded into outbound FIFO count 1 >>GIC buf: Command byte 137 unloaded from outbound FIFO count 0 >>GIC xfer: 5FH | ATN | | | | | Untalk >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040077 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 077 sent to bus >>GIC buf: Command byte 077 loaded into outbound FIFO count 1 >>GIC buf: Command byte 077 unloaded from outbound FIFO count 0 >>GIC xfer: 3FH | ATN | | | | | Unlisten >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000550 101205 absolute write >>CPP data: 00.000550 101205 absolute read >>CPP data: 00.101205 000601 absolute read >>CPP data: 00.101206 000001 absolute read >>CPP cmd: Executing Interrupt/Halt 0001 | CPVA 1 >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>CPP data: 00.000552 101104 absolute read >>CPP data: 00.101105 100001 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register C data 000012 with signals ADO | DDO | PRI >>GIC csrw: Register C (Interrupt) control is set | device 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | IRQ | PRO >>GIC imbus: Channel 11 asserts IRQ >>CPP serv: Program delay 1 service scheduled >>CPP data: 00.000553 100002 absolute read >>CPP data: 00.000553 000000 absolute write >>CPP data: 00.000550 101207 absolute write >>CPP serv: Channel processor rescheduled >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command IPOLL register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | IRQ | PRO >>CPP cmd: Channel processor interrupted by channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBII register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000132 with signals ADN | DDN | IRQ | PRO >>IMBA imbus: Channel 1 received opcode I/O Write command WIOC register 0 data 000132 with signals ADO | DDO | PRI >>IOP irq: Device number 125 asserted INTREQ at priority 12 >>IMBA imbus: Channel 1 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register C data 000002 with signals ADO | DDO | PRI >>GIC csrw: Register C (Interrupt) control is clear | device 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Channel processor idled >>IMBA iobus: Received data 000000 with signals INTPOLLIN >>IMBA iobus: Returned data 000132 with signals INTACK >>IOP irq: Device number 125 acknowledged interrupt request at priority 12 >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000004 absolute read >>CPP cmd: Channel processor executing SED2 >>CPP data: 00.000771 000001 absolute read >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Reset Interrupt order sent to device number 90 >>IMBA iobus: Received data 000000 with signals DRESETINT >>IMBA iobus: Returned data 000000 with signals (none) >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000003 absolute read >>CPP cmd: Channel processor executing WIOC >>CPP data: 00.000771 100000 absolute read >>CPP data: 00.000772 000020 absolute read >>CPP data: 00.000103 000000 absolute read >>IMBA imbus: Channel 1 received opcode I/O Write command SMSK register 0 data 000020 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command SMSK register 0 data 000020 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000000 absolute read >>CPP cmd: Channel processor executing SIOP >>CPP data: 00.000771 000132 absolute read >>CPP data: 00.000773 101171 absolute read >>CPP data: 00.000553 000000 absolute read >>CPP data: 00.000550 101171 absolute write >>CPP data: 00.000553 140000 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command SIOP register 0 data 000002 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>CPP opnd: 00.101171 004400 Clear 000 >>CPP opnd: 00.101173 002010 Write secondary 10 count 2 burst 1 address 00101115 chain 0 | record mode | left byte >>CPP opnd: 00.101200 001410 Read secondary 10 count 4 burst 1 address 00101113 chain 0 termination 101205 | record mode | left byte >>CPP opnd: 00.101205 000601 Interrupt/Halt 0001 | CPVA 1 >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor rescheduled >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | CSRQ1 | PRO >>CPP cmd: Channel processor servicing channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBSI register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 001132 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.000553 140000 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command SIOP register 0 data 000012 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000140 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is parity freeze | REN | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 4 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 4 (Poll mask) status is PP 0 | PP 1 | PP 2 >>GIC imbus: Channel 11 returned data 000340 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 4 data 000340 with signals ADO | DDO | PRI >>GIC csrw: Register 4 (Poll mask) control is PP 0 | PP 1 | PP 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register F data 000002 with signals ADO | DDO | PRI >>GIC csrw: Register F (Service info) control is DMA inbound | device 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000553 100000 absolute write >>CPP data: 00.000550 101171 absolute read >>CPP data: 00.101171 004400 absolute read >>CPP data: 00.101172 061044 absolute read >>CPP cmd: Executing Clear 000 >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040136 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 136 sent to bus >>GIC buf: Command byte 136 loaded into outbound FIFO count 1 >>GIC buf: Command byte 136 unloaded from outbound FIFO count 0 >>GIC xfer: 5EH | ATN | | | | | Talk 30 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040042 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 042 sent to bus >>GIC buf: Command byte 042 loaded into outbound FIFO count 1 >>GIC buf: Command byte 042 unloaded from outbound FIFO count 0 >>GIC xfer: 22H | ATN | | | | | Listen 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040160 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 160 sent to bus >>GIC buf: Command byte 160 loaded into outbound FIFO count 1 >>GIC buf: Command byte 160 unloaded from outbound FIFO count 0 >>GIC xfer: 70H | ATN | | | | | Secondary 10H >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 100000 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data EOI | 000 sent to bus >>GIC buf: EOI | data byte 000 loaded into outbound FIFO count 1 >>GIC buf: EOI | data byte 000 unloaded from outbound FIFO count 0 >>GIC xfer: 00H | | EOI | | | | Data (device 0 accepts) >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040004 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 004 sent to bus >>GIC buf: Command byte 004 loaded into outbound FIFO count 1 >>GIC buf: Command byte 004 unloaded from outbound FIFO count 0 >>GIC xfer: 04H | ATN | | | | | Selected device clear >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040077 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 077 sent to bus >>GIC buf: Command byte 077 loaded into outbound FIFO count 1 >>GIC buf: Command byte 077 unloaded from outbound FIFO count 0 >>GIC xfer: 3FH | ATN | | | | | Unlisten >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101173 002010 absolute read >>CPP data: 00.101174 000002 absolute read >>CPP cmd: Executing Write secondary 10 count 2 burst 1 address 00101115 chain 0 | record mode | left byte >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>CPP data: 00.101176 000000 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040136 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 136 sent to bus >>GIC buf: Command byte 136 loaded into outbound FIFO count 1 >>GIC buf: Command byte 136 unloaded from outbound FIFO count 0 >>GIC xfer: 5EH | ATN | | | | | Talk 30 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040042 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 042 sent to bus >>GIC buf: Command byte 042 loaded into outbound FIFO count 1 >>GIC buf: Command byte 042 unloaded from outbound FIFO count 0 >>GIC xfer: 22H | ATN | | | | | Listen 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040150 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 150 sent to bus >>GIC buf: Command byte 150 loaded into outbound FIFO count 1 >>GIC buf: Command byte 150 unloaded from outbound FIFO count 0 >>GIC xfer: 68H | ATN | | | | | Secondary 08H >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 6 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) status is parity freeze | REN | DMA inbound >>GIC imbus: Channel 11 returned data 000140 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000142 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is parity freeze | REN | DMA outbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 100002 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is IRQ | empty >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 8 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 8 (DMA bank) control is DMA disabled | bank 000 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.101177 101115 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 9 data 101115 with signals ADO | DDO | PRI >>GIC csrw: Register 9 (DMA address) control is address 101115 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register A data 000002 with signals ADO | DDO | PRI >>GIC csrw: Register A (DMA byte count) control is byte count 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.000553 100000 absolute read >>CPP data: 00.000553 100002 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register B data 000022 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) control is left byte | outbound | device 2 >>IMBA imbus: Memory controller received opcode Memory Read address 00101115 data 000000 with signals ADO | DDO | PRI >>IMBA data: 00.101115 001405 dma read >>IMBA imbus: Memory controller returned data 001405 with signals ADN | DDN | PRO >>GIC buf: Data byte 003 loaded into outbound FIFO count 1 >>GIC buf: EOI | data byte 005 loaded into outbound FIFO count 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.000550 101173 absolute write >>CPP serv: Channel processor rescheduled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | CSRQ1 | PRO >>CPP cmd: Channel processor servicing channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBSI register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000532 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>CPP data: 00.000553 100002 absolute read >>CPP data: 00.000550 101173 absolute read >>CPP data: 00.101173 002010 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101176 000000 absolute read >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register A data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register A (DMA byte count) status is byte count 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101174 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 9 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 9 (DMA address) status is address 101116 >>GIC imbus: Channel 11 returned data 101116 with signals ADN | DDN | PRO >>CPP data: 00.101177 101116 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register B data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) status is left byte | outbound | end state 0 | device 2 >>GIC imbus: Channel 11 returned data 000022 with signals ADN | DDN | PRO >>CPP data: 00.101176 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000140 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is parity freeze | REN | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040077 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 077 sent to bus >>GIC buf: Command byte 077 loaded into outbound FIFO count 3 >>GIC buf: Data byte 003 unloaded from outbound FIFO count 2 >>GIC xfer: 03H | | | | | | Data (device 0 accepts) >>GIC buf: EOI | data byte 005 unloaded from outbound FIFO count 1 >>GIC xfer: 05H | | EOI | | | | Data (device 0 accepts) >>GIC buf: Command byte 077 unloaded from outbound FIFO count 0 >>GIC xfer: 3FH | ATN | | | | | Unlisten >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000550 101200 absolute write >>CPP data: 00.000550 101200 absolute read >>CPP data: 00.101200 001410 absolute read >>CPP data: 00.101201 000004 absolute read >>CPP cmd: Executing Read secondary 10 count 4 burst 1 address 00101113 chain 0 termination 101205 | record mode | left byte >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>CPP data: 00.101203 000000 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040076 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 076 sent to bus >>GIC buf: Command byte 076 loaded into outbound FIFO count 1 >>GIC buf: Command byte 076 unloaded from outbound FIFO count 0 >>GIC xfer: 3EH | ATN | | | | | Listen 30 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040102 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 102 sent to bus >>GIC buf: Command byte 102 loaded into outbound FIFO count 1 >>GIC buf: Command byte 102 unloaded from outbound FIFO count 0 >>GIC xfer: 42H | ATN | | | | | Talk 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040150 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 150 sent to bus >>GIC buf: Command byte 150 loaded into outbound FIFO count 1 >>GIC buf: Command byte 150 unloaded from outbound FIFO count 0 >>GIC xfer: 68H | ATN | | | | | Secondary 08H >>GIC xfer: 00H | | | | | | Data (device 30 accepts) >>GIC buf: Data byte 000 loaded into inbound FIFO count 1 >>GIC xfer: 00H | | | | | | Data (device 30 accepts) >>GIC buf: Data byte 000 loaded into inbound FIFO count 2 >>GIC xfer: 02H | | | | | | Data (device 30 accepts) >>GIC buf: Data byte 002 loaded into inbound FIFO count 3 >>GIC xfer: 00H | | | | | | Data (device 30 accepts) >>GIC buf: Data byte 000 loaded into inbound FIFO count 4 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 140000 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Reception enabled >>GIC buf: Transfer count 000 loaded into outbound FIFO count 1 >>GIC buf: Transfer count 000 unloaded from outbound FIFO count 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 8 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 8 (DMA bank) control is DMA disabled | bank 000 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101204 101113 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 9 data 101113 with signals ADO | DDO | PRI >>GIC csrw: Register 9 (DMA address) control is address 101113 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register A data 000004 with signals ADO | DDO | PRI >>GIC csrw: Register A (DMA byte count) control is byte count 4 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000553 100002 absolute read >>CPP data: 00.000553 100002 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register B data 000002 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) control is left byte | inbound | device 2 >>GIC buf: Data byte 000 unloaded from inbound FIFO count 3 >>GIC buf: Data byte 000 unloaded from inbound FIFO count 2 >>IMBA imbus: Memory controller received opcode Memory Write address 00101113 data 000000 with signals ADO | DDO | PRI >>IMBA data: 00.101113 000000 dma write >>IMBA imbus: Memory controller returned data 000000 with signals ADN | DDN | PRO >>GIC buf: Data byte 002 unloaded from inbound FIFO count 1 >>GIC buf: Data byte 000 unloaded from inbound FIFO count 0 >>IMBA imbus: Memory controller received opcode Memory Write address 00101114 data 001000 with signals ADO | DDO | PRI >>IMBA data: 00.101114 001000 dma write >>IMBA imbus: Memory controller returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>CPP data: 00.000550 101200 absolute write >>CPP serv: Channel processor rescheduled >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | CSRQ1 | PRO >>CPP cmd: Channel processor servicing channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBSI register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000532 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>CPP data: 00.000553 100002 absolute read >>CPP data: 00.000550 101200 absolute read >>CPP data: 00.101200 001410 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101203 000000 absolute read >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register A data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register A (DMA byte count) status is byte count 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101201 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 9 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 9 (DMA address) status is address 101115 >>GIC imbus: Channel 11 returned data 101115 with signals ADN | DDN | PRO >>CPP data: 00.101204 101115 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register B data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) status is left byte | inbound | end state 0 | device 2 >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>CPP data: 00.101203 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register B data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) status is left byte | inbound | end state 0 | device 2 >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register B data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) status is left byte | inbound | end state 0 | device 2 >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040137 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 137 sent to bus >>GIC buf: Command byte 137 loaded into outbound FIFO count 1 >>GIC buf: Command byte 137 unloaded from outbound FIFO count 0 >>GIC xfer: 5FH | ATN | | | | | Untalk >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040077 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 077 sent to bus >>GIC buf: Command byte 077 loaded into outbound FIFO count 1 >>GIC buf: Command byte 077 unloaded from outbound FIFO count 0 >>GIC xfer: 3FH | ATN | | | | | Unlisten >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000550 101205 absolute write >>CPP data: 00.000550 101205 absolute read >>CPP data: 00.101205 000601 absolute read >>CPP data: 00.101206 000001 absolute read >>CPP cmd: Executing Interrupt/Halt 0001 | CPVA 1 >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>CPP data: 00.000552 101104 absolute read >>CPP data: 00.101105 100001 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register C data 000012 with signals ADO | DDO | PRI >>GIC csrw: Register C (Interrupt) control is set | device 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | IRQ | PRO >>GIC imbus: Channel 11 asserts IRQ >>CPP serv: Program delay 1 service scheduled >>CPP data: 00.000553 100002 absolute read >>CPP data: 00.000553 000000 absolute write >>CPP data: 00.000550 101207 absolute write >>CPP serv: Channel processor rescheduled >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command IPOLL register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | IRQ | PRO >>CPP cmd: Channel processor interrupted by channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBII register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000132 with signals ADN | DDN | IRQ | PRO >>IMBA imbus: Channel 1 received opcode I/O Write command WIOC register 0 data 000132 with signals ADO | DDO | PRI >>IOP irq: Device number 125 asserted INTREQ at priority 12 >>IMBA imbus: Channel 1 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register C data 000002 with signals ADO | DDO | PRI >>GIC csrw: Register C (Interrupt) control is clear | device 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Channel processor idled >>IMBA iobus: Received data 000000 with signals INTPOLLIN >>IMBA iobus: Returned data 000132 with signals INTACK >>IOP irq: Device number 125 acknowledged interrupt request at priority 12 >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000004 absolute read >>CPP cmd: Channel processor executing SED2 >>CPP data: 00.000771 000001 absolute read >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Reset Interrupt order sent to device number 90 >>IMBA iobus: Received data 000000 with signals DRESETINT >>IMBA iobus: Returned data 000000 with signals (none) >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000003 absolute read >>CPP cmd: Channel processor executing WIOC >>CPP data: 00.000771 100000 absolute read >>CPP data: 00.000772 000020 absolute read >>CPP data: 00.000103 000000 absolute read >>IMBA imbus: Channel 1 received opcode I/O Write command SMSK register 0 data 000020 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command SMSK register 0 data 000020 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000000 absolute read >>CPP cmd: Channel processor executing SIOP >>CPP data: 00.000771 000132 absolute read >>CPP data: 00.000773 101171 absolute read >>CPP data: 00.000553 000000 absolute read >>CPP data: 00.000550 101171 absolute write >>CPP data: 00.000553 140000 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command SIOP register 0 data 000002 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>CPP opnd: 00.101171 004400 Clear 000 >>CPP opnd: 00.101173 002010 Write secondary 10 count 2 burst 1 address 00101115 chain 0 | record mode | left byte >>CPP opnd: 00.101200 001410 Read secondary 10 count 4 burst 1 address 00101113 chain 0 termination 101205 | record mode | left byte >>CPP opnd: 00.101205 000601 Interrupt/Halt 0001 | CPVA 1 >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor rescheduled >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | CSRQ1 | PRO >>CPP cmd: Channel processor servicing channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBSI register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 001132 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.000553 140000 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command SIOP register 0 data 000012 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000140 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is parity freeze | REN | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 4 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 4 (Poll mask) status is PP 0 | PP 1 | PP 2 >>GIC imbus: Channel 11 returned data 000340 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 4 data 000340 with signals ADO | DDO | PRI >>GIC csrw: Register 4 (Poll mask) control is PP 0 | PP 1 | PP 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register F data 000002 with signals ADO | DDO | PRI >>GIC csrw: Register F (Service info) control is DMA inbound | device 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000553 100000 absolute write >>CPP data: 00.000550 101171 absolute read >>CPP data: 00.101171 004400 absolute read >>CPP data: 00.101172 061044 absolute read >>CPP cmd: Executing Clear 000 >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040136 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 136 sent to bus >>GIC buf: Command byte 136 loaded into outbound FIFO count 1 >>GIC buf: Command byte 136 unloaded from outbound FIFO count 0 >>GIC xfer: 5EH | ATN | | | | | Talk 30 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040042 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 042 sent to bus >>GIC buf: Command byte 042 loaded into outbound FIFO count 1 >>GIC buf: Command byte 042 unloaded from outbound FIFO count 0 >>GIC xfer: 22H | ATN | | | | | Listen 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040160 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 160 sent to bus >>GIC buf: Command byte 160 loaded into outbound FIFO count 1 >>GIC buf: Command byte 160 unloaded from outbound FIFO count 0 >>GIC xfer: 70H | ATN | | | | | Secondary 10H >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 100000 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data EOI | 000 sent to bus >>GIC buf: EOI | data byte 000 loaded into outbound FIFO count 1 >>GIC buf: EOI | data byte 000 unloaded from outbound FIFO count 0 >>GIC xfer: 00H | | EOI | | | | Data (device 0 accepts) >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040004 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 004 sent to bus >>GIC buf: Command byte 004 loaded into outbound FIFO count 1 >>GIC buf: Command byte 004 unloaded from outbound FIFO count 0 >>GIC xfer: 04H | ATN | | | | | Selected device clear >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040077 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 077 sent to bus >>GIC buf: Command byte 077 loaded into outbound FIFO count 1 >>GIC buf: Command byte 077 unloaded from outbound FIFO count 0 >>GIC xfer: 3FH | ATN | | | | | Unlisten >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101173 002010 absolute read >>CPP data: 00.101174 000002 absolute read >>CPP cmd: Executing Write secondary 10 count 2 burst 1 address 00101115 chain 0 | record mode | left byte >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>CPP data: 00.101176 000000 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040136 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 136 sent to bus >>GIC buf: Command byte 136 loaded into outbound FIFO count 1 >>GIC buf: Command byte 136 unloaded from outbound FIFO count 0 >>GIC xfer: 5EH | ATN | | | | | Talk 30 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040042 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 042 sent to bus >>GIC buf: Command byte 042 loaded into outbound FIFO count 1 >>GIC buf: Command byte 042 unloaded from outbound FIFO count 0 >>GIC xfer: 22H | ATN | | | | | Listen 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040150 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 150 sent to bus >>GIC buf: Command byte 150 loaded into outbound FIFO count 1 >>GIC buf: Command byte 150 unloaded from outbound FIFO count 0 >>GIC xfer: 68H | ATN | | | | | Secondary 08H >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 6 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) status is parity freeze | REN | DMA inbound >>GIC imbus: Channel 11 returned data 000140 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000142 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is parity freeze | REN | DMA outbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 100002 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is IRQ | empty >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 8 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 8 (DMA bank) control is DMA disabled | bank 000 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.101177 101115 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 9 data 101115 with signals ADO | DDO | PRI >>GIC csrw: Register 9 (DMA address) control is address 101115 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register A data 000002 with signals ADO | DDO | PRI >>GIC csrw: Register A (DMA byte count) control is byte count 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.000553 100000 absolute read >>CPP data: 00.000553 100002 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register B data 000022 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) control is left byte | outbound | device 2 >>IMBA imbus: Memory controller received opcode Memory Read address 00101115 data 000000 with signals ADO | DDO | PRI >>IMBA data: 00.101115 001406 dma read >>IMBA imbus: Memory controller returned data 001406 with signals ADN | DDN | PRO >>GIC buf: Data byte 003 loaded into outbound FIFO count 1 >>GIC buf: EOI | data byte 006 loaded into outbound FIFO count 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.000550 101173 absolute write >>CPP serv: Channel processor rescheduled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | CSRQ1 | PRO >>CPP cmd: Channel processor servicing channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBSI register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000532 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>CPP data: 00.000553 100002 absolute read >>CPP data: 00.000550 101173 absolute read >>CPP data: 00.101173 002010 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101176 000000 absolute read >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register A data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register A (DMA byte count) status is byte count 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101174 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 9 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 9 (DMA address) status is address 101116 >>GIC imbus: Channel 11 returned data 101116 with signals ADN | DDN | PRO >>CPP data: 00.101177 101116 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register B data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) status is left byte | outbound | end state 0 | device 2 >>GIC imbus: Channel 11 returned data 000022 with signals ADN | DDN | PRO >>CPP data: 00.101176 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000140 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is parity freeze | REN | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040077 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 077 sent to bus >>GIC buf: Command byte 077 loaded into outbound FIFO count 3 >>GIC buf: Data byte 003 unloaded from outbound FIFO count 2 >>GIC xfer: 03H | | | | | | Data (device 0 accepts) >>GIC buf: EOI | data byte 006 unloaded from outbound FIFO count 1 >>GIC xfer: 06H | | EOI | | | | Data (device 0 accepts) >>GIC buf: Command byte 077 unloaded from outbound FIFO count 0 >>GIC xfer: 3FH | ATN | | | | | Unlisten >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000550 101200 absolute write >>CPP data: 00.000550 101200 absolute read >>CPP data: 00.101200 001410 absolute read >>CPP data: 00.101201 000004 absolute read >>CPP cmd: Executing Read secondary 10 count 4 burst 1 address 00101113 chain 0 termination 101205 | record mode | left byte >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>CPP data: 00.101203 000000 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040076 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 076 sent to bus >>GIC buf: Command byte 076 loaded into outbound FIFO count 1 >>GIC buf: Command byte 076 unloaded from outbound FIFO count 0 >>GIC xfer: 3EH | ATN | | | | | Listen 30 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040102 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 102 sent to bus >>GIC buf: Command byte 102 loaded into outbound FIFO count 1 >>GIC buf: Command byte 102 unloaded from outbound FIFO count 0 >>GIC xfer: 42H | ATN | | | | | Talk 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040150 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 150 sent to bus >>GIC buf: Command byte 150 loaded into outbound FIFO count 1 >>GIC buf: Command byte 150 unloaded from outbound FIFO count 0 >>GIC xfer: 68H | ATN | | | | | Secondary 08H >>GIC xfer: 00H | | | | | | Data (device 30 accepts) >>GIC buf: Data byte 000 loaded into inbound FIFO count 1 >>GIC xfer: 00H | | | | | | Data (device 30 accepts) >>GIC buf: Data byte 000 loaded into inbound FIFO count 2 >>GIC xfer: 02H | | | | | | Data (device 30 accepts) >>GIC buf: Data byte 002 loaded into inbound FIFO count 3 >>GIC xfer: 00H | | | | | | Data (device 30 accepts) >>GIC buf: Data byte 000 loaded into inbound FIFO count 4 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 140000 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Reception enabled >>GIC buf: Transfer count 000 loaded into outbound FIFO count 1 >>GIC buf: Transfer count 000 unloaded from outbound FIFO count 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 8 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 8 (DMA bank) control is DMA disabled | bank 000 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101204 101113 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 9 data 101113 with signals ADO | DDO | PRI >>GIC csrw: Register 9 (DMA address) control is address 101113 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register A data 000004 with signals ADO | DDO | PRI >>GIC csrw: Register A (DMA byte count) control is byte count 4 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000553 100002 absolute read >>CPP data: 00.000553 100002 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register B data 000002 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) control is left byte | inbound | device 2 >>GIC buf: Data byte 000 unloaded from inbound FIFO count 3 >>GIC buf: Data byte 000 unloaded from inbound FIFO count 2 >>IMBA imbus: Memory controller received opcode Memory Write address 00101113 data 000000 with signals ADO | DDO | PRI >>IMBA data: 00.101113 000000 dma write >>IMBA imbus: Memory controller returned data 000000 with signals ADN | DDN | PRO >>GIC buf: Data byte 002 unloaded from inbound FIFO count 1 >>GIC buf: Data byte 000 unloaded from inbound FIFO count 0 >>IMBA imbus: Memory controller received opcode Memory Write address 00101114 data 001000 with signals ADO | DDO | PRI >>IMBA data: 00.101114 001000 dma write >>IMBA imbus: Memory controller returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>CPP data: 00.000550 101200 absolute write >>CPP serv: Channel processor rescheduled >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | CSRQ1 | PRO >>CPP cmd: Channel processor servicing channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBSI register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000532 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>CPP data: 00.000553 100002 absolute read >>CPP data: 00.000550 101200 absolute read >>CPP data: 00.101200 001410 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101203 000000 absolute read >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register A data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register A (DMA byte count) status is byte count 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101201 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 9 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 9 (DMA address) status is address 101115 >>GIC imbus: Channel 11 returned data 101115 with signals ADN | DDN | PRO >>CPP data: 00.101204 101115 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register B data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) status is left byte | inbound | end state 0 | device 2 >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>CPP data: 00.101203 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register B data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) status is left byte | inbound | end state 0 | device 2 >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register B data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) status is left byte | inbound | end state 0 | device 2 >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040137 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 137 sent to bus >>GIC buf: Command byte 137 loaded into outbound FIFO count 1 >>GIC buf: Command byte 137 unloaded from outbound FIFO count 0 >>GIC xfer: 5FH | ATN | | | | | Untalk >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040077 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 077 sent to bus >>GIC buf: Command byte 077 loaded into outbound FIFO count 1 >>GIC buf: Command byte 077 unloaded from outbound FIFO count 0 >>GIC xfer: 3FH | ATN | | | | | Unlisten >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000550 101205 absolute write >>CPP data: 00.000550 101205 absolute read >>CPP data: 00.101205 000601 absolute read >>CPP data: 00.101206 000001 absolute read >>CPP cmd: Executing Interrupt/Halt 0001 | CPVA 1 >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>CPP data: 00.000552 101104 absolute read >>CPP data: 00.101105 100001 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register C data 000012 with signals ADO | DDO | PRI >>GIC csrw: Register C (Interrupt) control is set | device 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | IRQ | PRO >>GIC imbus: Channel 11 asserts IRQ >>CPP serv: Program delay 1 service scheduled >>CPP data: 00.000553 100002 absolute read >>CPP data: 00.000553 000000 absolute write >>CPP data: 00.000550 101207 absolute write >>CPP serv: Channel processor rescheduled >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command IPOLL register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | IRQ | PRO >>CPP cmd: Channel processor interrupted by channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBII register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000132 with signals ADN | DDN | IRQ | PRO >>IMBA imbus: Channel 1 received opcode I/O Write command WIOC register 0 data 000132 with signals ADO | DDO | PRI >>IOP irq: Device number 125 asserted INTREQ at priority 12 >>IMBA imbus: Channel 1 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register C data 000002 with signals ADO | DDO | PRI >>GIC csrw: Register C (Interrupt) control is clear | device 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Channel processor idled >>IMBA iobus: Received data 000000 with signals INTPOLLIN >>IMBA iobus: Returned data 000132 with signals INTACK >>IOP irq: Device number 125 acknowledged interrupt request at priority 12 >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000004 absolute read >>CPP cmd: Channel processor executing SED2 >>CPP data: 00.000771 000001 absolute read >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Reset Interrupt order sent to device number 90 >>IMBA iobus: Received data 000000 with signals DRESETINT >>IMBA iobus: Returned data 000000 with signals (none) >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000003 absolute read >>CPP cmd: Channel processor executing WIOC >>CPP data: 00.000771 100000 absolute read >>CPP data: 00.000772 000020 absolute read >>CPP data: 00.000103 000000 absolute read >>IMBA imbus: Channel 1 received opcode I/O Write command SMSK register 0 data 000020 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command SMSK register 0 data 000020 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000000 absolute read >>CPP cmd: Channel processor executing SIOP >>CPP data: 00.000771 000132 absolute read >>CPP data: 00.000773 101171 absolute read >>CPP data: 00.000553 000000 absolute read >>CPP data: 00.000550 101171 absolute write >>CPP data: 00.000553 140000 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command SIOP register 0 data 000002 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>CPP opnd: 00.101171 004400 Clear 000 >>CPP opnd: 00.101173 002010 Write secondary 10 count 2 burst 1 address 00101115 chain 0 | record mode | left byte >>CPP opnd: 00.101200 001410 Read secondary 10 count 4 burst 1 address 00101113 chain 0 termination 101205 | record mode | left byte >>CPP opnd: 00.101205 000601 Interrupt/Halt 0001 | CPVA 1 >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor rescheduled >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | CSRQ1 | PRO >>CPP cmd: Channel processor servicing channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBSI register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 001132 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.000553 140000 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command SIOP register 0 data 000012 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000140 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is parity freeze | REN | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 4 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 4 (Poll mask) status is PP 0 | PP 1 | PP 2 >>GIC imbus: Channel 11 returned data 000340 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 4 data 000340 with signals ADO | DDO | PRI >>GIC csrw: Register 4 (Poll mask) control is PP 0 | PP 1 | PP 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register F data 000002 with signals ADO | DDO | PRI >>GIC csrw: Register F (Service info) control is DMA inbound | device 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000553 100000 absolute write >>CPP data: 00.000550 101171 absolute read >>CPP data: 00.101171 004400 absolute read >>CPP data: 00.101172 061044 absolute read >>CPP cmd: Executing Clear 000 >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040136 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 136 sent to bus >>GIC buf: Command byte 136 loaded into outbound FIFO count 1 >>GIC buf: Command byte 136 unloaded from outbound FIFO count 0 >>GIC xfer: 5EH | ATN | | | | | Talk 30 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040042 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 042 sent to bus >>GIC buf: Command byte 042 loaded into outbound FIFO count 1 >>GIC buf: Command byte 042 unloaded from outbound FIFO count 0 >>GIC xfer: 22H | ATN | | | | | Listen 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040160 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 160 sent to bus >>GIC buf: Command byte 160 loaded into outbound FIFO count 1 >>GIC buf: Command byte 160 unloaded from outbound FIFO count 0 >>GIC xfer: 70H | ATN | | | | | Secondary 10H >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 100000 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data EOI | 000 sent to bus >>GIC buf: EOI | data byte 000 loaded into outbound FIFO count 1 >>GIC buf: EOI | data byte 000 unloaded from outbound FIFO count 0 >>GIC xfer: 00H | | EOI | | | | Data (device 0 accepts) >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040004 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 004 sent to bus >>GIC buf: Command byte 004 loaded into outbound FIFO count 1 >>GIC buf: Command byte 004 unloaded from outbound FIFO count 0 >>GIC xfer: 04H | ATN | | | | | Selected device clear >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040077 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 077 sent to bus >>GIC buf: Command byte 077 loaded into outbound FIFO count 1 >>GIC buf: Command byte 077 unloaded from outbound FIFO count 0 >>GIC xfer: 3FH | ATN | | | | | Unlisten >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101173 002010 absolute read >>CPP data: 00.101174 000002 absolute read >>CPP cmd: Executing Write secondary 10 count 2 burst 1 address 00101115 chain 0 | record mode | left byte >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>CPP data: 00.101176 000000 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040136 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 136 sent to bus >>GIC buf: Command byte 136 loaded into outbound FIFO count 1 >>GIC buf: Command byte 136 unloaded from outbound FIFO count 0 >>GIC xfer: 5EH | ATN | | | | | Talk 30 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040042 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 042 sent to bus >>GIC buf: Command byte 042 loaded into outbound FIFO count 1 >>GIC buf: Command byte 042 unloaded from outbound FIFO count 0 >>GIC xfer: 22H | ATN | | | | | Listen 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040150 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 150 sent to bus >>GIC buf: Command byte 150 loaded into outbound FIFO count 1 >>GIC buf: Command byte 150 unloaded from outbound FIFO count 0 >>GIC xfer: 68H | ATN | | | | | Secondary 08H >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 6 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) status is parity freeze | REN | DMA inbound >>GIC imbus: Channel 11 returned data 000140 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000142 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is parity freeze | REN | DMA outbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 100002 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is IRQ | empty >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 8 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 8 (DMA bank) control is DMA disabled | bank 000 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.101177 101115 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 9 data 101115 with signals ADO | DDO | PRI >>GIC csrw: Register 9 (DMA address) control is address 101115 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register A data 000002 with signals ADO | DDO | PRI >>GIC csrw: Register A (DMA byte count) control is byte count 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.000553 100000 absolute read >>CPP data: 00.000553 100002 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register B data 000022 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) control is left byte | outbound | device 2 >>IMBA imbus: Memory controller received opcode Memory Read address 00101115 data 000000 with signals ADO | DDO | PRI >>IMBA data: 00.101115 001407 dma read >>IMBA imbus: Memory controller returned data 001407 with signals ADN | DDN | PRO >>GIC buf: Data byte 003 loaded into outbound FIFO count 1 >>GIC buf: EOI | data byte 007 loaded into outbound FIFO count 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.000550 101173 absolute write >>CPP serv: Channel processor rescheduled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | CSRQ1 | PRO >>CPP cmd: Channel processor servicing channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBSI register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000532 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>CPP data: 00.000553 100002 absolute read >>CPP data: 00.000550 101173 absolute read >>CPP data: 00.101173 002010 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101176 000000 absolute read >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register A data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register A (DMA byte count) status is byte count 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101174 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 9 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 9 (DMA address) status is address 101116 >>GIC imbus: Channel 11 returned data 101116 with signals ADN | DDN | PRO >>CPP data: 00.101177 101116 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register B data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) status is left byte | outbound | end state 0 | device 2 >>GIC imbus: Channel 11 returned data 000022 with signals ADN | DDN | PRO >>CPP data: 00.101176 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000140 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is parity freeze | REN | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040077 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 077 sent to bus >>GIC buf: Command byte 077 loaded into outbound FIFO count 3 >>GIC buf: Data byte 003 unloaded from outbound FIFO count 2 >>GIC xfer: 03H | | | | | | Data (device 0 accepts) >>GIC buf: EOI | data byte 007 unloaded from outbound FIFO count 1 >>GIC xfer: 07H | | EOI | | | | Data (device 0 accepts) >>GIC buf: Command byte 077 unloaded from outbound FIFO count 0 >>GIC xfer: 3FH | ATN | | | | | Unlisten >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000550 101200 absolute write >>CPP data: 00.000550 101200 absolute read >>CPP data: 00.101200 001410 absolute read >>CPP data: 00.101201 000004 absolute read >>CPP cmd: Executing Read secondary 10 count 4 burst 1 address 00101113 chain 0 termination 101205 | record mode | left byte >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>CPP data: 00.101203 000000 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040076 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 076 sent to bus >>GIC buf: Command byte 076 loaded into outbound FIFO count 1 >>GIC buf: Command byte 076 unloaded from outbound FIFO count 0 >>GIC xfer: 3EH | ATN | | | | | Listen 30 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040102 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 102 sent to bus >>GIC buf: Command byte 102 loaded into outbound FIFO count 1 >>GIC buf: Command byte 102 unloaded from outbound FIFO count 0 >>GIC xfer: 42H | ATN | | | | | Talk 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040150 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 150 sent to bus >>GIC buf: Command byte 150 loaded into outbound FIFO count 1 >>GIC buf: Command byte 150 unloaded from outbound FIFO count 0 >>GIC xfer: 68H | ATN | | | | | Secondary 08H >>GIC xfer: 00H | | | | | | Data (device 30 accepts) >>GIC buf: Data byte 000 loaded into inbound FIFO count 1 >>GIC xfer: 00H | | | | | | Data (device 30 accepts) >>GIC buf: Data byte 000 loaded into inbound FIFO count 2 >>GIC xfer: 02H | | | | | | Data (device 30 accepts) >>GIC buf: Data byte 002 loaded into inbound FIFO count 3 >>GIC xfer: 00H | | | | | | Data (device 30 accepts) >>GIC buf: Data byte 000 loaded into inbound FIFO count 4 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 140000 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Reception enabled >>GIC buf: Transfer count 000 loaded into outbound FIFO count 1 >>GIC buf: Transfer count 000 unloaded from outbound FIFO count 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 8 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 8 (DMA bank) control is DMA disabled | bank 000 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101204 101113 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 9 data 101113 with signals ADO | DDO | PRI >>GIC csrw: Register 9 (DMA address) control is address 101113 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register A data 000004 with signals ADO | DDO | PRI >>GIC csrw: Register A (DMA byte count) control is byte count 4 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000553 100002 absolute read >>CPP data: 00.000553 100002 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register B data 000002 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) control is left byte | inbound | device 2 >>GIC buf: Data byte 000 unloaded from inbound FIFO count 3 >>GIC buf: Data byte 000 unloaded from inbound FIFO count 2 >>IMBA imbus: Memory controller received opcode Memory Write address 00101113 data 000000 with signals ADO | DDO | PRI >>IMBA data: 00.101113 000000 dma write >>IMBA imbus: Memory controller returned data 000000 with signals ADN | DDN | PRO >>GIC buf: Data byte 002 unloaded from inbound FIFO count 1 >>GIC buf: Data byte 000 unloaded from inbound FIFO count 0 >>IMBA imbus: Memory controller received opcode Memory Write address 00101114 data 001000 with signals ADO | DDO | PRI >>IMBA data: 00.101114 001000 dma write >>IMBA imbus: Memory controller returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>CPP data: 00.000550 101200 absolute write >>CPP serv: Channel processor rescheduled >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | CSRQ1 | PRO >>CPP cmd: Channel processor servicing channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBSI register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000532 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>CPP data: 00.000553 100002 absolute read >>CPP data: 00.000550 101200 absolute read >>CPP data: 00.101200 001410 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101203 000000 absolute read >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register A data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register A (DMA byte count) status is byte count 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101201 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 9 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 9 (DMA address) status is address 101115 >>GIC imbus: Channel 11 returned data 101115 with signals ADN | DDN | PRO >>CPP data: 00.101204 101115 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register B data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) status is left byte | inbound | end state 0 | device 2 >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>CPP data: 00.101203 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register B data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) status is left byte | inbound | end state 0 | device 2 >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register B data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) status is left byte | inbound | end state 0 | device 2 >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040137 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 137 sent to bus >>GIC buf: Command byte 137 loaded into outbound FIFO count 1 >>GIC buf: Command byte 137 unloaded from outbound FIFO count 0 >>GIC xfer: 5FH | ATN | | | | | Untalk >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040077 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 077 sent to bus >>GIC buf: Command byte 077 loaded into outbound FIFO count 1 >>GIC buf: Command byte 077 unloaded from outbound FIFO count 0 >>GIC xfer: 3FH | ATN | | | | | Unlisten >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000550 101205 absolute write >>CPP data: 00.000550 101205 absolute read >>CPP data: 00.101205 000601 absolute read >>CPP data: 00.101206 000001 absolute read >>CPP cmd: Executing Interrupt/Halt 0001 | CPVA 1 >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>CPP data: 00.000552 101104 absolute read >>CPP data: 00.101105 100001 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register C data 000012 with signals ADO | DDO | PRI >>GIC csrw: Register C (Interrupt) control is set | device 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | IRQ | PRO >>GIC imbus: Channel 11 asserts IRQ >>CPP serv: Program delay 1 service scheduled >>CPP data: 00.000553 100002 absolute read >>CPP data: 00.000553 000000 absolute write >>CPP data: 00.000550 101207 absolute write >>CPP serv: Channel processor rescheduled >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command IPOLL register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | IRQ | PRO >>CPP cmd: Channel processor interrupted by channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBII register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000132 with signals ADN | DDN | IRQ | PRO >>IMBA imbus: Channel 1 received opcode I/O Write command WIOC register 0 data 000132 with signals ADO | DDO | PRI >>IOP irq: Device number 125 asserted INTREQ at priority 12 >>IMBA imbus: Channel 1 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register C data 000002 with signals ADO | DDO | PRI >>GIC csrw: Register C (Interrupt) control is clear | device 2 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Channel processor idled >>IMBA iobus: Received data 000000 with signals INTPOLLIN >>IMBA iobus: Returned data 000132 with signals INTACK >>IOP irq: Device number 125 acknowledged interrupt request at priority 12 >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000004 absolute read >>CPP cmd: Channel processor executing SED2 >>CPP data: 00.000771 000001 absolute read >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Reset Interrupt order sent to device number 90 >>IMBA iobus: Received data 000000 with signals DRESETINT >>IMBA iobus: Returned data 000000 with signals (none) >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000002 absolute read >>CPP cmd: Channel processor executing RIOC >>CPP data: 00.000771 007133 absolute read >>CPP data: 00.000557 000000 absolute read >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register E data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register E (DMA abort) status is S2 A | S1 CPU | channel ID 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000772 000000 absolute write >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000006 absolute read >>CPP cmd: Channel processor executing INIT >>CPP data: 00.000771 000130 absolute read >>CPP data: 00.000013 000020 absolute read >>CPP data: 00.000013 000000 absolute write >>CPP data: 00.000543 000000 absolute write >>CPP data: 00.000547 000000 absolute write >>CPP data: 00.000553 000000 absolute write >>CPP data: 00.000557 000000 absolute write >>CPP data: 00.000563 000000 absolute write >>CPP data: 00.000567 000000 absolute write >>CPP data: 00.000573 000000 absolute write >>CPP data: 00.000577 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command INIT register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register E data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register E (DMA abort) status is S2 A | S1 CPU | channel ID 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000010 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is poll response | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 7 data 000200 with signals ADO | DDO | PRI >>GIC csrw: Register 7 (Bus address) control is bus address 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000060 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is REN | IFC | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000040 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is REN | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 2 data 040301 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) control is parity error | status change | FIFO abort | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000001 absolute read >>CPP cmd: Channel processor executing HIOP >>CPP data: 00.000771 000133 absolute read >>CPP data: 00.000557 000000 absolute read >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000003 absolute read >>CPP cmd: Channel processor executing WIOC >>CPP data: 00.000771 100000 absolute read >>CPP data: 00.000772 000020 absolute read >>CPP data: 00.000103 000000 absolute read >>IMBA imbus: Channel 1 received opcode I/O Write command SMSK register 0 data 000020 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command SMSK register 0 data 000020 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000000 absolute read >>CPP cmd: Channel processor executing SIOP >>CPP data: 00.000771 000133 absolute read >>CPP data: 00.000773 101203 absolute read >>CPP data: 00.000557 000000 absolute read >>CPP data: 00.000554 101203 absolute write >>CPP data: 00.000557 140000 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command SIOP register 0 data 000003 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>CPP opnd: 00.101203 003000 Identify | response FFFF >>CPP opnd: 00.101205 000601 Interrupt/Halt 0001 | CPVA 1 >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor rescheduled >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | CSRQ1 | PRO >>CPP cmd: Channel processor servicing channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBSI register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 001133 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.000557 140000 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command SIOP register 0 data 000013 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000140 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is parity freeze | REN | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 4 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 4 (Poll mask) status is PP 0 | PP 1 | PP 2 >>GIC imbus: Channel 11 returned data 000340 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 4 data 000360 with signals ADO | DDO | PRI >>GIC csrw: Register 4 (Poll mask) control is PP 0 | PP 1 | PP 2 | PP 3 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register F data 000003 with signals ADO | DDO | PRI >>GIC csrw: Register F (Service info) control is DMA inbound | device 3 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000557 100000 absolute write >>CPP data: 00.000554 101203 absolute read >>CPP data: 00.101203 003000 absolute read >>CPP data: 00.101204 177777 absolute read >>CPP cmd: Executing Identify | response FFFF >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040076 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 076 sent to bus >>GIC buf: Command byte 076 loaded into outbound FIFO count 1 >>GIC buf: Command byte 076 unloaded from outbound FIFO count 0 >>GIC xfer: 3EH | ATN | | | | | Listen 30 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040137 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 137 sent to bus >>GIC buf: Command byte 137 loaded into outbound FIFO count 1 >>GIC buf: Command byte 137 unloaded from outbound FIFO count 0 >>GIC xfer: 5FH | ATN | | | | | Untalk >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040143 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 143 sent to bus >>GIC buf: Command byte 143 loaded into outbound FIFO count 1 >>GIC buf: Command byte 143 unloaded from outbound FIFO count 0 >>GIC xfer: 63H | ATN | | | | | Secondary 03H >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 140002 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Reception enabled >>GIC buf: Transfer count 002 loaded into outbound FIFO count 1 >>GIC buf: Transfer count 002 unloaded from outbound FIFO count 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 100004 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is IRQ | data >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register F data 000203 with signals ADO | DDO | PRI >>GIC csrw: Register F (Service info) control is inhibit CSRQ | DMA inbound | device 3 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000557 100000 absolute read >>CPP data: 00.000557 100010 absolute write >>CPP data: 00.000554 101203 absolute write >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000001 absolute read >>CPP cmd: Channel processor executing HIOP >>CPP data: 00.000771 000133 absolute read >>CPP data: 00.000557 100010 absolute read >>CPP data: 00.000557 040000 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command HIOP register 0 data 000003 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor rescheduled >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | CSRQ1 | PRO >>CPP cmd: Channel processor servicing channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBSI register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 001133 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.000557 040000 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command HIOP register 0 data 000013 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000557 040000 absolute read >>CPP data: 00.000557 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 4 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 4 (Poll mask) status is PP 0 | PP 1 | PP 2 | PP 3 >>GIC imbus: Channel 11 returned data 000360 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 4 data 000360 with signals ADO | DDO | PRI >>GIC csrw: Register 4 (Poll mask) control is PP 0 | PP 1 | PP 2 | PP 3 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 100240 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is IRQ | status change | poll response >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100401 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000006 absolute read >>CPP cmd: Channel processor executing INIT >>CPP data: 00.000771 000130 absolute read >>CPP data: 00.000013 000020 absolute read >>CPP data: 00.000013 000000 absolute write >>CPP data: 00.000543 000000 absolute write >>CPP data: 00.000547 000000 absolute write >>CPP data: 00.000553 000000 absolute write >>CPP data: 00.000557 000000 absolute write >>CPP data: 00.000563 000000 absolute write >>CPP data: 00.000567 000000 absolute write >>CPP data: 00.000573 000000 absolute write >>CPP data: 00.000577 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command INIT register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register E data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register E (DMA abort) status is S2 A | S1 CPU | channel ID 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000010 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is poll response | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 7 data 000200 with signals ADO | DDO | PRI >>GIC csrw: Register 7 (Bus address) control is bus address 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000060 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is REN | IFC | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000040 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is REN | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 2 data 040301 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) control is parity error | status change | FIFO abort | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000002 absolute read >>CPP cmd: Channel processor executing RIOC >>CPP data: 00.000771 007134 absolute read >>CPP data: 00.000563 000000 absolute read >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register E data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register E (DMA abort) status is S2 A | S1 CPU | channel ID 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000772 000000 absolute write >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000006 absolute read >>CPP cmd: Channel processor executing INIT >>CPP data: 00.000771 000130 absolute read >>CPP data: 00.000013 000000 absolute read >>CPP data: 00.000013 000000 absolute write >>CPP data: 00.000543 000000 absolute write >>CPP data: 00.000547 000000 absolute write >>CPP data: 00.000553 000000 absolute write >>CPP data: 00.000557 000000 absolute write >>CPP data: 00.000563 000000 absolute write >>CPP data: 00.000567 000000 absolute write >>CPP data: 00.000573 000000 absolute write >>CPP data: 00.000577 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command INIT register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register E data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register E (DMA abort) status is S2 A | S1 CPU | channel ID 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000010 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is poll response | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 7 data 000200 with signals ADO | DDO | PRI >>GIC csrw: Register 7 (Bus address) control is bus address 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000060 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is REN | IFC | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000040 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is REN | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 2 data 040301 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) control is parity error | status change | FIFO abort | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000001 absolute read >>CPP cmd: Channel processor executing HIOP >>CPP data: 00.000771 000134 absolute read >>CPP data: 00.000563 000000 absolute read >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000003 absolute read >>CPP cmd: Channel processor executing WIOC >>CPP data: 00.000771 100000 absolute read >>CPP data: 00.000772 000020 absolute read >>CPP data: 00.000103 000000 absolute read >>IMBA imbus: Channel 1 received opcode I/O Write command SMSK register 0 data 000020 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command SMSK register 0 data 000020 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000000 absolute read >>CPP cmd: Channel processor executing SIOP >>CPP data: 00.000771 000134 absolute read >>CPP data: 00.000773 101203 absolute read >>CPP data: 00.000563 000000 absolute read >>CPP data: 00.000560 101203 absolute write >>CPP data: 00.000563 140000 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command SIOP register 0 data 000004 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>CPP opnd: 00.101203 003000 Identify | response FFFF >>CPP opnd: 00.101205 000601 Interrupt/Halt 0001 | CPVA 1 >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor rescheduled >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | CSRQ1 | PRO >>CPP cmd: Channel processor servicing channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBSI register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 001134 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.000563 140000 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command SIOP register 0 data 000014 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000140 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is parity freeze | REN | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 4 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 4 (Poll mask) status is PP 0 | PP 1 | PP 2 | PP 3 >>GIC imbus: Channel 11 returned data 000360 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 4 data 000370 with signals ADO | DDO | PRI >>GIC csrw: Register 4 (Poll mask) control is PP 0 | PP 1 | PP 2 | PP 3 | PP 4 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register F data 000004 with signals ADO | DDO | PRI >>GIC csrw: Register F (Service info) control is DMA inbound | device 4 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000563 100000 absolute write >>CPP data: 00.000560 101203 absolute read >>CPP data: 00.101203 003000 absolute read >>CPP data: 00.101204 177777 absolute read >>CPP cmd: Executing Identify | response FFFF >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040076 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 076 sent to bus >>GIC buf: Command byte 076 loaded into outbound FIFO count 1 >>GIC buf: Command byte 076 unloaded from outbound FIFO count 0 >>GIC xfer: 3EH | ATN | | | | | Listen 30 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040137 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 137 sent to bus >>GIC buf: Command byte 137 loaded into outbound FIFO count 1 >>GIC buf: Command byte 137 unloaded from outbound FIFO count 0 >>GIC xfer: 5FH | ATN | | | | | Untalk >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040144 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 144 sent to bus >>GIC buf: Command byte 144 loaded into outbound FIFO count 1 >>GIC buf: Command byte 144 unloaded from outbound FIFO count 0 >>GIC xfer: 64H | ATN | | | | | Secondary 04H >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 140002 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Reception enabled >>GIC buf: Transfer count 002 loaded into outbound FIFO count 1 >>GIC buf: Transfer count 002 unloaded from outbound FIFO count 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 100004 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is IRQ | data >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register F data 000204 with signals ADO | DDO | PRI >>GIC csrw: Register F (Service info) control is inhibit CSRQ | DMA inbound | device 4 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000563 100000 absolute read >>CPP data: 00.000563 100010 absolute write >>CPP data: 00.000560 101203 absolute write >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000001 absolute read >>CPP cmd: Channel processor executing HIOP >>CPP data: 00.000771 000134 absolute read >>CPP data: 00.000563 100010 absolute read >>CPP data: 00.000563 040000 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command HIOP register 0 data 000004 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor rescheduled >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | CSRQ1 | PRO >>CPP cmd: Channel processor servicing channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBSI register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 001134 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.000563 040000 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command HIOP register 0 data 000014 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000563 040000 absolute read >>CPP data: 00.000563 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 4 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 4 (Poll mask) status is PP 0 | PP 1 | PP 2 | PP 3 | PP 4 >>GIC imbus: Channel 11 returned data 000370 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 4 data 000370 with signals ADO | DDO | PRI >>GIC csrw: Register 4 (Poll mask) control is PP 0 | PP 1 | PP 2 | PP 3 | PP 4 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 100240 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is IRQ | status change | poll response >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100401 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000006 absolute read >>CPP cmd: Channel processor executing INIT >>CPP data: 00.000771 000130 absolute read >>CPP data: 00.000013 000020 absolute read >>CPP data: 00.000013 000000 absolute write >>CPP data: 00.000543 000000 absolute write >>CPP data: 00.000547 000000 absolute write >>CPP data: 00.000553 000000 absolute write >>CPP data: 00.000557 000000 absolute write >>CPP data: 00.000563 000000 absolute write >>CPP data: 00.000567 000000 absolute write >>CPP data: 00.000573 000000 absolute write >>CPP data: 00.000577 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command INIT register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register E data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register E (DMA abort) status is S2 A | S1 CPU | channel ID 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000010 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is poll response | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 7 data 000200 with signals ADO | DDO | PRI >>GIC csrw: Register 7 (Bus address) control is bus address 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000060 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is REN | IFC | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000040 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is REN | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 2 data 040301 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) control is parity error | status change | FIFO abort | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000002 absolute read >>CPP cmd: Channel processor executing RIOC >>CPP data: 00.000771 007135 absolute read >>CPP data: 00.000567 000000 absolute read >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register E data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register E (DMA abort) status is S2 A | S1 CPU | channel ID 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000772 000000 absolute write >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000006 absolute read >>CPP cmd: Channel processor executing INIT >>CPP data: 00.000771 000130 absolute read >>CPP data: 00.000013 000000 absolute read >>CPP data: 00.000013 000000 absolute write >>CPP data: 00.000543 000000 absolute write >>CPP data: 00.000547 000000 absolute write >>CPP data: 00.000553 000000 absolute write >>CPP data: 00.000557 000000 absolute write >>CPP data: 00.000563 000000 absolute write >>CPP data: 00.000567 000000 absolute write >>CPP data: 00.000573 000000 absolute write >>CPP data: 00.000577 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command INIT register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register E data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register E (DMA abort) status is S2 A | S1 CPU | channel ID 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000010 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is poll response | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 7 data 000200 with signals ADO | DDO | PRI >>GIC csrw: Register 7 (Bus address) control is bus address 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000060 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is REN | IFC | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000040 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is REN | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 2 data 040301 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) control is parity error | status change | FIFO abort | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000001 absolute read >>CPP cmd: Channel processor executing HIOP >>CPP data: 00.000771 000135 absolute read >>CPP data: 00.000567 000000 absolute read >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000003 absolute read >>CPP cmd: Channel processor executing WIOC >>CPP data: 00.000771 100000 absolute read >>CPP data: 00.000772 000020 absolute read >>CPP data: 00.000103 000000 absolute read >>IMBA imbus: Channel 1 received opcode I/O Write command SMSK register 0 data 000020 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command SMSK register 0 data 000020 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000000 absolute read >>CPP cmd: Channel processor executing SIOP >>CPP data: 00.000771 000135 absolute read >>CPP data: 00.000773 101203 absolute read >>CPP data: 00.000567 000000 absolute read >>CPP data: 00.000564 101203 absolute write >>CPP data: 00.000567 140000 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command SIOP register 0 data 000005 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>CPP opnd: 00.101203 003000 Identify | response FFFF >>CPP opnd: 00.101205 000601 Interrupt/Halt 0001 | CPVA 1 >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor rescheduled >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | CSRQ1 | PRO >>CPP cmd: Channel processor servicing channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBSI register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 001135 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.000567 140000 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command SIOP register 0 data 000015 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000140 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is parity freeze | REN | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 4 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 4 (Poll mask) status is PP 0 | PP 1 | PP 2 | PP 3 | PP 4 >>GIC imbus: Channel 11 returned data 000370 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 4 data 000374 with signals ADO | DDO | PRI >>GIC csrw: Register 4 (Poll mask) control is PP 0 | PP 1 | PP 2 | PP 3 | PP 4 | PP 5 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register F data 000005 with signals ADO | DDO | PRI >>GIC csrw: Register F (Service info) control is DMA inbound | device 5 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000567 100000 absolute write >>CPP data: 00.000564 101203 absolute read >>CPP data: 00.101203 003000 absolute read >>CPP data: 00.101204 177777 absolute read >>CPP cmd: Executing Identify | response FFFF >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040076 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 076 sent to bus >>GIC buf: Command byte 076 loaded into outbound FIFO count 1 >>GIC buf: Command byte 076 unloaded from outbound FIFO count 0 >>GIC xfer: 3EH | ATN | | | | | Listen 30 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040137 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 137 sent to bus >>GIC buf: Command byte 137 loaded into outbound FIFO count 1 >>GIC buf: Command byte 137 unloaded from outbound FIFO count 0 >>GIC xfer: 5FH | ATN | | | | | Untalk >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040145 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 145 sent to bus >>GIC buf: Command byte 145 loaded into outbound FIFO count 1 >>GIC buf: Command byte 145 unloaded from outbound FIFO count 0 >>GIC xfer: 65H | ATN | | | | | Secondary 05H >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 140002 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Reception enabled >>GIC buf: Transfer count 002 loaded into outbound FIFO count 1 >>GIC buf: Transfer count 002 unloaded from outbound FIFO count 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 100004 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is IRQ | data >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register F data 000205 with signals ADO | DDO | PRI >>GIC csrw: Register F (Service info) control is inhibit CSRQ | DMA inbound | device 5 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000567 100000 absolute read >>CPP data: 00.000567 100010 absolute write >>CPP data: 00.000564 101203 absolute write >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000001 absolute read >>CPP cmd: Channel processor executing HIOP >>CPP data: 00.000771 000135 absolute read >>CPP data: 00.000567 100010 absolute read >>CPP data: 00.000567 040000 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command HIOP register 0 data 000005 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor rescheduled >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | CSRQ1 | PRO >>CPP cmd: Channel processor servicing channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBSI register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 001135 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.000567 040000 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command HIOP register 0 data 000015 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000567 040000 absolute read >>CPP data: 00.000567 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 4 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 4 (Poll mask) status is PP 0 | PP 1 | PP 2 | PP 3 | PP 4 | PP 5 >>GIC imbus: Channel 11 returned data 000374 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 4 data 000374 with signals ADO | DDO | PRI >>GIC csrw: Register 4 (Poll mask) control is PP 0 | PP 1 | PP 2 | PP 3 | PP 4 | PP 5 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 100240 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is IRQ | status change | poll response >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100401 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000006 absolute read >>CPP cmd: Channel processor executing INIT >>CPP data: 00.000771 000130 absolute read >>CPP data: 00.000013 000020 absolute read >>CPP data: 00.000013 000000 absolute write >>CPP data: 00.000543 000000 absolute write >>CPP data: 00.000547 000000 absolute write >>CPP data: 00.000553 000000 absolute write >>CPP data: 00.000557 000000 absolute write >>CPP data: 00.000563 000000 absolute write >>CPP data: 00.000567 000000 absolute write >>CPP data: 00.000573 000000 absolute write >>CPP data: 00.000577 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command INIT register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register E data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register E (DMA abort) status is S2 A | S1 CPU | channel ID 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000010 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is poll response | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 7 data 000200 with signals ADO | DDO | PRI >>GIC csrw: Register 7 (Bus address) control is bus address 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000060 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is REN | IFC | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000040 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is REN | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 2 data 040301 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) control is parity error | status change | FIFO abort | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000002 absolute read >>CPP cmd: Channel processor executing RIOC >>CPP data: 00.000771 007136 absolute read >>CPP data: 00.000573 000000 absolute read >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register E data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register E (DMA abort) status is S2 A | S1 CPU | channel ID 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000772 000000 absolute write >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000006 absolute read >>CPP cmd: Channel processor executing INIT >>CPP data: 00.000771 000130 absolute read >>CPP data: 00.000013 000000 absolute read >>CPP data: 00.000013 000000 absolute write >>CPP data: 00.000543 000000 absolute write >>CPP data: 00.000547 000000 absolute write >>CPP data: 00.000553 000000 absolute write >>CPP data: 00.000557 000000 absolute write >>CPP data: 00.000563 000000 absolute write >>CPP data: 00.000567 000000 absolute write >>CPP data: 00.000573 000000 absolute write >>CPP data: 00.000577 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command INIT register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register E data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register E (DMA abort) status is S2 A | S1 CPU | channel ID 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000010 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is poll response | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 7 data 000200 with signals ADO | DDO | PRI >>GIC csrw: Register 7 (Bus address) control is bus address 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000060 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is REN | IFC | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000040 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is REN | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 2 data 040301 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) control is parity error | status change | FIFO abort | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000001 absolute read >>CPP cmd: Channel processor executing HIOP >>CPP data: 00.000771 000136 absolute read >>CPP data: 00.000573 000000 absolute read >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000003 absolute read >>CPP cmd: Channel processor executing WIOC >>CPP data: 00.000771 100000 absolute read >>CPP data: 00.000772 000020 absolute read >>CPP data: 00.000103 000000 absolute read >>IMBA imbus: Channel 1 received opcode I/O Write command SMSK register 0 data 000020 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command SMSK register 0 data 000020 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000000 absolute read >>CPP cmd: Channel processor executing SIOP >>CPP data: 00.000771 000136 absolute read >>CPP data: 00.000773 101203 absolute read >>CPP data: 00.000573 000000 absolute read >>CPP data: 00.000570 101203 absolute write >>CPP data: 00.000573 140000 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command SIOP register 0 data 000006 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>CPP opnd: 00.101203 003000 Identify | response FFFF >>CPP opnd: 00.101205 000601 Interrupt/Halt 0001 | CPVA 1 >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor rescheduled >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | CSRQ1 | PRO >>CPP cmd: Channel processor servicing channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBSI register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 001136 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.000573 140000 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command SIOP register 0 data 000016 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000140 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is parity freeze | REN | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 4 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 4 (Poll mask) status is PP 0 | PP 1 | PP 2 | PP 3 | PP 4 | PP 5 >>GIC imbus: Channel 11 returned data 000374 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 4 data 000376 with signals ADO | DDO | PRI >>GIC csrw: Register 4 (Poll mask) control is PP 0 | PP 1 | PP 2 | PP 3 | PP 4 | PP 5 | PP 6 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register F data 000006 with signals ADO | DDO | PRI >>GIC csrw: Register F (Service info) control is DMA inbound | device 6 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000573 100000 absolute write >>CPP data: 00.000570 101203 absolute read >>CPP data: 00.101203 003000 absolute read >>CPP data: 00.101204 177777 absolute read >>CPP cmd: Executing Identify | response FFFF >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040076 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 076 sent to bus >>GIC buf: Command byte 076 loaded into outbound FIFO count 1 >>GIC buf: Command byte 076 unloaded from outbound FIFO count 0 >>GIC xfer: 3EH | ATN | | | | | Listen 30 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040137 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 137 sent to bus >>GIC buf: Command byte 137 loaded into outbound FIFO count 1 >>GIC buf: Command byte 137 unloaded from outbound FIFO count 0 >>GIC xfer: 5FH | ATN | | | | | Untalk >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040146 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 146 sent to bus >>GIC buf: Command byte 146 loaded into outbound FIFO count 1 >>GIC buf: Command byte 146 unloaded from outbound FIFO count 0 >>GIC xfer: 66H | ATN | | | | | Secondary 06H >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 140002 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Reception enabled >>GIC buf: Transfer count 002 loaded into outbound FIFO count 1 >>GIC buf: Transfer count 002 unloaded from outbound FIFO count 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 100004 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is IRQ | data >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register F data 000206 with signals ADO | DDO | PRI >>GIC csrw: Register F (Service info) control is inhibit CSRQ | DMA inbound | device 6 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000573 100000 absolute read >>CPP data: 00.000573 100010 absolute write >>CPP data: 00.000570 101203 absolute write >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000001 absolute read >>CPP cmd: Channel processor executing HIOP >>CPP data: 00.000771 000136 absolute read >>CPP data: 00.000573 100010 absolute read >>CPP data: 00.000573 040000 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command HIOP register 0 data 000006 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor rescheduled >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | CSRQ1 | PRO >>CPP cmd: Channel processor servicing channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBSI register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 001136 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.000573 040000 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command HIOP register 0 data 000016 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000573 040000 absolute read >>CPP data: 00.000573 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 4 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 4 (Poll mask) status is PP 0 | PP 1 | PP 2 | PP 3 | PP 4 | PP 5 | PP 6 >>GIC imbus: Channel 11 returned data 000376 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 4 data 000376 with signals ADO | DDO | PRI >>GIC csrw: Register 4 (Poll mask) control is PP 0 | PP 1 | PP 2 | PP 3 | PP 4 | PP 5 | PP 6 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 100240 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is IRQ | status change | poll response >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100401 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000006 absolute read >>CPP cmd: Channel processor executing INIT >>CPP data: 00.000771 000130 absolute read >>CPP data: 00.000013 000020 absolute read >>CPP data: 00.000013 000000 absolute write >>CPP data: 00.000543 000000 absolute write >>CPP data: 00.000547 000000 absolute write >>CPP data: 00.000553 000000 absolute write >>CPP data: 00.000557 000000 absolute write >>CPP data: 00.000563 000000 absolute write >>CPP data: 00.000567 000000 absolute write >>CPP data: 00.000573 000000 absolute write >>CPP data: 00.000577 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command INIT register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register E data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register E (DMA abort) status is S2 A | S1 CPU | channel ID 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000010 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is poll response | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 7 data 000200 with signals ADO | DDO | PRI >>GIC csrw: Register 7 (Bus address) control is bus address 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000060 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is REN | IFC | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000040 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is REN | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 2 data 040301 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) control is parity error | status change | FIFO abort | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000002 absolute read >>CPP cmd: Channel processor executing RIOC >>CPP data: 00.000771 007137 absolute read >>CPP data: 00.000577 000000 absolute read >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register E data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register E (DMA abort) status is S2 A | S1 CPU | channel ID 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000772 000000 absolute write >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000006 absolute read >>CPP cmd: Channel processor executing INIT >>CPP data: 00.000771 000130 absolute read >>CPP data: 00.000013 000000 absolute read >>CPP data: 00.000013 000000 absolute write >>CPP data: 00.000543 000000 absolute write >>CPP data: 00.000547 000000 absolute write >>CPP data: 00.000553 000000 absolute write >>CPP data: 00.000557 000000 absolute write >>CPP data: 00.000563 000000 absolute write >>CPP data: 00.000567 000000 absolute write >>CPP data: 00.000573 000000 absolute write >>CPP data: 00.000577 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command INIT register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register E data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register E (DMA abort) status is S2 A | S1 CPU | channel ID 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000010 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is poll response | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 7 data 000200 with signals ADO | DDO | PRI >>GIC csrw: Register 7 (Bus address) control is bus address 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000060 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is REN | IFC | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000040 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is REN | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 2 data 040301 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) control is parity error | status change | FIFO abort | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000001 absolute read >>CPP cmd: Channel processor executing HIOP >>CPP data: 00.000771 000137 absolute read >>CPP data: 00.000577 000000 absolute read >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000003 absolute read >>CPP cmd: Channel processor executing WIOC >>CPP data: 00.000771 100000 absolute read >>CPP data: 00.000772 000020 absolute read >>CPP data: 00.000103 000000 absolute read >>IMBA imbus: Channel 1 received opcode I/O Write command SMSK register 0 data 000020 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command SMSK register 0 data 000020 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000000 absolute read >>CPP cmd: Channel processor executing SIOP >>CPP data: 00.000771 000137 absolute read >>CPP data: 00.000773 101203 absolute read >>CPP data: 00.000577 000000 absolute read >>CPP data: 00.000574 101203 absolute write >>CPP data: 00.000577 140000 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command SIOP register 0 data 000007 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>CPP opnd: 00.101203 003000 Identify | response FFFF >>CPP opnd: 00.101205 000601 Interrupt/Halt 0001 | CPVA 1 >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor rescheduled >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | CSRQ1 | PRO >>CPP cmd: Channel processor servicing channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBSI register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 001137 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.000577 140000 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command SIOP register 0 data 000017 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000140 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is parity freeze | REN | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 4 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 4 (Poll mask) status is PP 0 | PP 1 | PP 2 | PP 3 | PP 4 | PP 5 | PP 6 >>GIC imbus: Channel 11 returned data 000376 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 4 data 000377 with signals ADO | DDO | PRI >>GIC csrw: Register 4 (Poll mask) control is PP 0 | PP 1 | PP 2 | PP 3 | PP 4 | PP 5 | PP 6 | PP 7 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register F data 000007 with signals ADO | DDO | PRI >>GIC csrw: Register F (Service info) control is DMA inbound | device 7 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000577 100000 absolute write >>CPP data: 00.000574 101203 absolute read >>CPP data: 00.101203 003000 absolute read >>CPP data: 00.101204 177777 absolute read >>CPP cmd: Executing Identify | response FFFF >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040076 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 076 sent to bus >>GIC buf: Command byte 076 loaded into outbound FIFO count 1 >>GIC buf: Command byte 076 unloaded from outbound FIFO count 0 >>GIC xfer: 3EH | ATN | | | | | Listen 30 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040137 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 137 sent to bus >>GIC buf: Command byte 137 loaded into outbound FIFO count 1 >>GIC buf: Command byte 137 unloaded from outbound FIFO count 0 >>GIC xfer: 5FH | ATN | | | | | Untalk >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040147 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 147 sent to bus >>GIC buf: Command byte 147 loaded into outbound FIFO count 1 >>GIC buf: Command byte 147 unloaded from outbound FIFO count 0 >>GIC xfer: 67H | ATN | | | | | Secondary 07H >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 140002 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Reception enabled >>GIC buf: Transfer count 002 loaded into outbound FIFO count 1 >>GIC buf: Transfer count 002 unloaded from outbound FIFO count 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 100004 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is IRQ | data >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register F data 000207 with signals ADO | DDO | PRI >>GIC csrw: Register F (Service info) control is inhibit CSRQ | DMA inbound | device 7 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000577 100000 absolute read >>CPP data: 00.000577 100010 absolute write >>CPP data: 00.000574 101203 absolute write >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000001 absolute read >>CPP cmd: Channel processor executing HIOP >>CPP data: 00.000771 000137 absolute read >>CPP data: 00.000577 100010 absolute read >>CPP data: 00.000577 040000 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command HIOP register 0 data 000007 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor rescheduled >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | CSRQ1 | PRO >>CPP cmd: Channel processor servicing channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBSI register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 001137 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.000577 040000 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command HIOP register 0 data 000017 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000577 040000 absolute read >>CPP data: 00.000577 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 4 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 4 (Poll mask) status is PP 0 | PP 1 | PP 2 | PP 3 | PP 4 | PP 5 | PP 6 | PP 7 >>GIC imbus: Channel 11 returned data 000377 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 4 data 000377 with signals ADO | DDO | PRI >>GIC csrw: Register 4 (Poll mask) control is PP 0 | PP 1 | PP 2 | PP 3 | PP 4 | PP 5 | PP 6 | PP 7 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 100240 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is IRQ | status change | poll response >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100401 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000006 absolute read >>CPP cmd: Channel processor executing INIT >>CPP data: 00.000771 000130 absolute read >>CPP data: 00.000013 000020 absolute read >>CPP data: 00.000013 000000 absolute write >>CPP data: 00.000543 000000 absolute write >>CPP data: 00.000547 000000 absolute write >>CPP data: 00.000553 000000 absolute write >>CPP data: 00.000557 000000 absolute write >>CPP data: 00.000563 000000 absolute write >>CPP data: 00.000567 000000 absolute write >>CPP data: 00.000573 000000 absolute write >>CPP data: 00.000577 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command INIT register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register E data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register E (DMA abort) status is S2 A | S1 CPU | channel ID 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000010 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is poll response | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 7 data 000200 with signals ADO | DDO | PRI >>GIC csrw: Register 7 (Bus address) control is bus address 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000060 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is REN | IFC | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000040 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is REN | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 2 data 040301 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) control is parity error | status change | FIFO abort | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000002 absolute read >>CPP cmd: Channel processor executing RIOC >>CPP data: 00.000771 120010 absolute read >>CPP data: 00.000043 000000 absolute read >>IMBA imbus: Channel 1 received opcode I/O Read command ROCL register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command ROCL register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | PRO >>CPP data: 00.000772 000020 absolute write >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000002 absolute read >>CPP cmd: Channel processor executing RIOC >>CPP data: 00.000771 120010 absolute read >>CPP data: 00.000043 000000 absolute read >>IMBA imbus: Channel 1 received opcode I/O Read command ROCL register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command ROCL register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | PRO >>CPP data: 00.000772 000020 absolute write >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000002 absolute read >>CPP cmd: Channel processor executing RIOC >>CPP data: 00.000771 120010 absolute read >>CPP data: 00.000043 000000 absolute read >>IMBA imbus: Channel 1 received opcode I/O Read command ROCL register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command ROCL register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | PRO >>CPP data: 00.000772 000020 absolute write >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 1 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000002 absolute read >>CPP cmd: Channel processor executing RIOC >>CPP data: 00.000771 120010 absolute read >>CPP data: 00.000043 000000 absolute read >>IMBA imbus: Channel 1 received opcode I/O Read command ROCL register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command ROCL register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | PRO >>CPP data: 00.000772 000020 absolute write >>CPP serv: Completion delay 1 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write