Work Remaining on the HP 3000 Simulator ======================================= ------------ Current Work ------------ General ------- - Try MPE V/R for Series 33 and MPE IV, if we have it. CPU --- - Move UNIT_CALTIME from cpu.h to cpu.c (recast as DEV_CALTIME ?). - SYSHALT 3 is "trace or absence trap for segment 1," but we split these conditions into halts 33 and 3, respectively, so that the diagnostic command file can assert that the correct system halt occurred. Use some other condition to detect? Note that the halt occurs in cpu_call_procedure, so the A and T bits are coming from the CST. MEM --- IOP --- MPX --- SEL --- ADCC ---- ATC --- CLK --- CPP --- DC -- DS -- GIC --- LP -- LPA --- MA -- - Does having MA and DC on the same GIC work if bus addresses do not conflict? MS -- - Confirm that detaching the unit fails gracefully even if an event is scheduled. User's Manual ------------- Software Kits ------------- ================================================================================ ----------- Future Work ----------- General ------- + Implement generic _trace routine that handles setting and showing local trigger and window commands, and listing trace events? Otherwise, need separate list and window (and trigger?) routines. + Implement multi-device triggering: TRACE TRIGGER =, e.g., TRACE TRIGGER CPU INSTRUCTION=LDI 1. Might want to trigger on, e.g., a disc seek or an ADCC modem state change. + Trace list calls device.trace routine, so all IDs can be local. + [sys] Add symbolic entry for DEPOSIT, etc. perhaps using the HP2100 instruction mnemonic decoding method. - BUG: trace formatting uses sys_device_size and sys_flag_size, but these are calculated only in response to a SET command (to catch SET DEBUG). But with in-memory tracing, they don't get set because of TRACE STORE =.... - [CPP] Can we have a CPP unit that is scheduled instead of a delay counter? Is the delay even necessary? It is for Identify, but what if DC and MA sent both bytes in the same transaction? The receiving GIC has a FIFO. For the CPU, the instruction loop could just do "if (SIR & sir_IMBCSRQ)" and then call cpp_service(). - [extension] Enhance expanded modifiers to handle OFF/0/1/2/3 and INTMASK=0-15/E/D (i.e., where the value is a bit in a bitmap). - [MA] Add POWER FAIL/RESTORE MA handling for diagnostic. - [MA] Provide a SET UNIT command in hp_tapelib, so the diags that push the unit buttons don't need detach/attach. Detaching loses the tape position, while changing the unit assignment doesn't. Fortunately, this isn't tested by any diagnostic.... - fprint_edit calls mem_examine to get words, but this won't work if EXAMINE -E specifies a device (e.g., DS0). Must call get_aval potentially multiple times to get sim_emax words each time. - fprint_edit calls fmt_byte_operand to print edit strings, but this only works with main memory. Same issue as above. - SET GIC COUNT=1,CHANNEL=2 fails on 2nd option. Fix will be automatic when COUNT is an SCP option. It would be possible for ex_set_dev_count to call set_cmd with constructed SET GIC CHANNEL=2... string, but SET GIC CHANNEL=2,COUNT=1 will not work. - TO_PA currently masks the bank parameter with "mem_bank_mask" but does not mask the offset parameter. Assignments to PBANK, etc. are masked when stored, so they do not need to be masked each time they are used. If all uses of TO_PA ensured that the bank number was masked before used (e.g., when the bank number is in a TOS register), then redundant masking for bank registers would not be needed. x The interpretive switches for EXAMINE and DEPOSIT (B, D, H, O, A, C, and M) should be mutually exclusive and should return an error (SCPE_INVSW, "Invalid switch") if more than one are entered. In particular, the radix switches do not modify the mnemonic instruction operand interpretation (so, e.g., "DEPOSIT -O -M 1000 RRL 10" does not interpret the rotate count as octal; instead, it is illegal). In the absence of switches, the lead character (numeric, alpha, ", or ') determines the interpretation, so, e.g., "DEPOSIT 1000 CCE" deposits 002300 (the CCE opcode), whereas "DEPOSIT -H 1000 CCE" deposits 006316 (the value 0xCCE). Alpha values are always interpreted as mnemonics first, even if SET CPU HEX is in effect; otherwise DEP 1000 CCE would be interpreted differently, depending on the setting. - Version-agnostic SAVE/RESTORE is blocked only by one SRDATA for the "overrides" array of structures in DS. Use 4.0 STRDATA instead? Would have to implement for 3.9 too.... - Should DEVNO be limited to 3-127 instead of 0-127? Hardware doesn't.... - hp_disclib.h and hp_tapelib.h should include hp2100_defs.h or hp3000_defs.h, depending on a symbol defined on the compilation command line, rather than hard-coding the filename. - Terminology: "Programmed Master Clear" instead of "master reset"? - Add some helpful system-wide definitions: - define TRUE_IF as (BOOLEAN) (v != 0) - define SET_IF as (FLIP_FLOP) (v != 0) (currently, there is a D_FF macro that does this, but is missing the cast) CPU --- - Implement instruction breakpoints? Can this be leveraged from instruction trace triggering? - Add another parameter to EXEC that ANDs and DOESN'T match target? So maybe "SET CPU EXEC=030060;177774;177777", i.e., CIR & B == A && CIR & C != A? What is the use case? - Add APL instructions. - Add APL instruction mnemonics to disassembly. - Test COBOL II instruction interruptibility and restore intra-instruction checks for pending interrupts. - Implement the Fault Logging Interface. The FLI diagnostic tests memory ECC (there's an FLI option that suppresses writing the ECC bits when a memory location is written, and the ability to correct all single-bit errors is tested), so ECC would have to be implemented as well. - cpu_push (n), cpu_pop (n) to combine multiple calls (esp. stack decrements). cpu_queue_down (n) too, but not cpu_queue_up; only called if SR = 0! cpu_adjust_sr appears to be cpu_queue_up in a loop with the test moved to the end of the loop. - Use common code for the MVB, MVBW and CMPB instructions. MVB and CMPB are almost identical! Or conert to byte accessors (and trace byte operands). - Modify the cold load procedure to work as specified in the Series III ERS. - Decouple STEP counts from event ticks. Currently, STEPping into an interruptable instruction executes only one word move (e.g.), rather than one MOVE instruction. Implement by getting the step count, cancelling the step counter, and decrementing the step count once for each instruction executed. - Event ticks may eventually correspond to microseconds to allow instructions to take varying lengths of simulated time. Change the machine_instruction return from a t_stat to a uint32, with the status in one half and the event tick count to decrement in the other. - Add the Series II as an option; initial release is Series III only. Modify the cold load procedure to work as specified in the Series II microcode manual. - Implement the LOCK/UNLK instructions (required for the Series II only). - Create a cpu_handle_ics_irq() and cpu_handle_non_ics_irq() functions to call from trap and interrupt routines, and from IXIT, DISP, and PSEB instructions. - Implement the front panel diagnostics (they're different for II vs. III). - Implement direct I/O cold load. - Add a BACKTRACE command to trace stack frames? Helpful for MPE debugging? - Add CPU DEBUG=DWARN to print access to undefined device but keep going? DSTOP both prints and stops (e.g., DEB_DWARN = 001, DEB_DSTOP = 011) same for IWARN/ISTOP. - Change interrupt_pending to cpu_interrupt_pending and use for sim_instr execution loop check too? Only external use of cpu_run_mode_interrupt. - Add some means of seeing what precedes a system halt, e.g., a PC queue, a state memory (last 256 instructions?), etc. The VAX uses SET CPU HISTORY=n and then SHOW HIST=n. IOP --- MPX --- SEL --- ATC --- - Create an hp_muxlib to share the multiplexer code between the ATC and the HP 1000? Use ML_ for muxlib, with DL_ and TL_ for disc and tape libraries. CLK --- DS -- - Allow a variable number (1-8) of MAC units by (a) validating the command unit number via "dptr->numunits" and reporting "unit offline" if larger, and (b) accessing the controller unit as "dptr->units + dptr->numunits - 1" instead of using "DL_MAXDRIVE + 1" as the controller unit number. - Use a fixed, fast end_phase time in set_completion instead of half of the overhead time? An end delay seems to be needed by the interface, but most of the actual overhead is in the first part of command processing. - To support the HP 1000 ICD interface (DA), all uses in the the library must obtain the unit number from "cvptr->poll_unit", which must be set during initialization and never altered thereafter, and ignore the unit number in the command word (ICD unit numbers are always 0). Note that DA declares a four-unit array as well as a four-CNTLR_STAT array. - Recalibrate is much slower than a seek. Recalibrate moves the heads at a constant 3.5" per second. The heads retract to cylinder 0, then reverse over the guard band (24 tracks), and finally move forward over the guard band back to cylinder 0. On a 7925, the track spacing is 2.6 mil, so a full-stroke traversal time is about 650 msec. Should this be simulated? Note also that Recalibrate won't give a seek check if the controller contains a bad head/sector value. - Move "device" to the first item in CNTLR_STATE for faster access? - Separate SPD and unit for improved speed? LP -- MS -- - Is it possible to add a DIAG mode, similar to DS, to help with the diagnostic? - WRZ: check how many zero bytes are recognized as a dropout vs. end of record; write should stop with EOR and ignore CRCC and LRCC passed as data. - Setting the wait timing duplicates a lot of conditions; maybe a lookup table? GIC --- - ADCC and MA use a bitmap for talker, while GIC and DC use an address value. Change so that bitmaps are used uniformly? - Command parity check asserts NDAC. This should freeze the bus by modifying transfer_data to check for NDAC and NRFD and skip transfer if asserted. Also, hpib_source must remove NDAC only if ATN is not asserted (i.e., it's a leftover from a data transfer). - NRFD denial is not handled very well. An example from LPA: the local bus service routine calls hpib_source to deny NRFD, which calls gic_hpib_accept, which calls transfer_data to resume data transfer, which calls hpib_source to source the next data byte, which calls lpa_hpib_accept to receive it, which calls process_data to load the byte into the bus buffer, which sets a global final-byte status. But then unwinding returns to the local bus service, which has been processing the NEXT-to-last byte, but now sees that the final byte has been processed. The problem is that the global state can change during the NRFD denial call. A better idea might be to have NRFD denial in hpib_source clear the signal from the bus but to SCHEDULE the resumption-of-data call to transfer_data with a zero (or one) event-tick delay. That would allow the hpib_source caller to unwind before the next byte was sourced, so that the global state wouldn't change during the denial call. User's Manual ------------- - FLI - Symbolic instruction (CPU/IOP) entry - II / III