HP 3000 Operational Notes ========================= ---------------- Hardware History ---------------- SIO Machines (Date Introduced): - 3000 : 11/72 30000A - 3000 CX : 11/74 32400C - Series II : 6/76 32416A - Series I : 4/77 32420A (a repackaged 3000 CX) - Series III : 6/78 32435B HP-IB Machines (Date Introduced): - Series 33 : 10/78 32412B - Series 30 : 10/79 32430B - Series 44 : 12/80 32440B - Series 40 : 10/81 32445A - Series 64 : 10/81 32460B - Series 39 : 2/83 32514B - Series 42 : 5/83 32542B - Series 48 : 5/83 32548B - Series 68 : 5/83 32468C - Series 37 : 9/84 32449A - Series 37XE : 11/84 32450B - Series 52 : 32552C 3/87 - Series 58 : 8/85 32558A - Series 42XP : 9/85 30550A (is a field upgrade from 39/40/42) - Series 70 : 2/86 32471A - Micro 3000 RX : 11/86 32535A - Micro 3000 LX : 11/86 32520A - Micro 3000 GX : 11/86 32536A - Micro 3000 XE : 32545A 6/88 The 1992 CE Parts List manual lists the following CPU/ALU PCAs and their applicable system models, and the 1987 CE Handbook lists the following CPU instruction counts: Part Number ALU Instr. PCN Series ----------- ------ ------ --- --------------------- 30001-60003 74181 192 - I 30003-60003 74S181 209 1 II 30003-60003 74S181 209 2 III 30070-60003 custom 214 8 33, 30 30457-60001 custom - 5 37 30474-60001 custom - 6 3000 XE 30534-600xx custom - 7 Micro 3000 RX, LX, GX 30090-60002 74S381 195 3 39, 40, 42 30090-60002 74S381 214 3 44, 48 30476-60001 -- 197 3 42XP, 52 30476-60001 -- 214 3 58 30140-60002 100181 - 4 64, 68, 70 Supported Memory Sizes (words): - 3000 : 48K, 64K - 3000 CX : 48K, 64K - Series I : 64K - Series II : 64K, 96K, 128K, 160K, 192K, 224K, 256K - Series III : 128K, 256K, 384K, 512K, 640K, 768K, 896K, 1024K - Series 30 : 128K, 256K, 384K, 512K - Series 33 : 128K, 256K, 384K, 512K - Series 37 : 256K, 512K, 1024K - Series 37XE : 512K, 1024K - Series 39 : 256K, 384K, 512K, 768K, 1024K, 1536K - Series 40 : 256K, 384K, 512K, 768K, 1024K - Series 42 : 512K, 768K, 1024K, 1536K - Series 42XP : 2048K, 2560K, 3072K, 3584K, 4096K - Series 44 : 512K, 768K, 1024K, 1280K, 1536K, 1792K, 2048K - Series 48 : 1024K, 1280K, 1536K, 1792K, 2048K - Series 52 : 1024K [?], 2048K, 2560K, 3072K, 3584K, 4096K - Series 58 : 2048K, 2560K, 3072K, 3584K, 4096K - Series 64 : 2M, 2.5M, 3M, 3.5M, 4M, 4.5M, 5M, 5.5M, 6M, 6.5M, 7M, 7.5M, 8M - Series 68 : 2M, 2.5M, 3M, 3.5M, 4M, 4.5M, 5M, 5.5M, 6M, 6.5M, 7M, 7.5M, 8M - Series 70 : 4M, 4.5M, 5M, 5.5M, 6M, 6.5M, 7M, 7.5M, 8M - Micro 3000 : 1024K, 2048K - Micro 3000 GX : 1024K, 2048K - Micro 3000 LX : 1024K, 2048K - Micro 3000 RX : 1024K, 2048K - Micro 3000 XE : 1024K, 2048K, 3072K, 4096K System Max Modules -------------- ----- ------------------------ 3000 CX 64K 8K Series I 64K 32K Series II 256K 32K Series III 1024K 128K Series 30 512K 64K Series 33 512K 64K Series 37 1024K 256K, 512K, 1024K Series 37XE 1024K 512K, 1024K Series 39 1536K 128K, 512K Series 40 1024K 128K, 256K, 512K Series 42 1536K 256K, 512K Series 42XP 4096K 512K, 1024K, 2048K Series 44 2048K 256K, 512K Series 48 2048K 128K, 512K, 1024K, 2048K Series 52 4096K 512K, 1024K, 2048K Series 58 4096K 512K, 1024K, 2048K Series 64 8192K 512K, 2048K Series 68 8192K 512K, 2048K Series 70 8192K 512K, 2048K Micro 3000 2048K 1024K, 2048K Micro 3000 GX 2048K 1024K, 2048K Micro 3000 LX 2048K 1024K, 2048K Micro 3000 RX 2048K 1024K, 2048K Micro 3000 XE 4096K 1024K, 2048K (Series III supported memory sizes are from the "HP 3000 Computer Systems Price/Configuration Guide", 5953-0558, Oct-1978, page 26.) Terminal Multiplexers: - 30032B ATC - 16 channel, 2400 baud, discrete I/O hardware - Essentially the HP 12920A - Compatible Systems: 3000, 3000 CX, Series II, Series III - 31264A ADCC - 4 channel, 9600 baud, LSI UART per port - Extender PCAs add 4 channels each - Compatible Systems: 33, 30, 39, 40, 42, 42XP, 52, 44, 48, 58 - 30196C ATP - 12 channel (per AIB), 19200 baud, 6801 uP per port - up to 8 AIBs per SIB - Compatible Systems: 64, 68, 70 - 30460A ATP/37 (TIC) - 7 channel, 19200 baud - Compatible Systems: 37 30341A HP-IB Interface Module (a GIC for the Series III to connect HP-IB peripherals) (manuals are dated May 1981) DUS Cold Load Tape Format file VERTS/HP32231/S10S231A.SPL lines 4532-4599 31262A GIC and 31264A ADCC are used on the HP 300 (HPJ 1979-07) ---------------- Software History ---------------- - MPE : for the 3000 - MPE-C : 32000 C.xx.xx for the 3000 CX (Jan-1975) [comm 6-75] - MPE-II : 32002 A.xx.xx for the Series II (64K minimum) (Aug-1976) [comm 9-76] - MPE-III : 32002 B.xx.xx for the Series II and III (128K minimum) (Apr-1978) - MPE-III : 32033 A.xx.xx for the Series 33 (Apr-1979) - MPE-III : 32033 B.xx.xx for the Series 33 and 30 - MPE-IV : 32002 C.xx.xx for the Series II and III (Feb-1981) - MPE-IV : 32033 C/D.xx.xx for the Series 3x, 4x, and 6x - MPE-V/P : 32033 E/F.xx.xx for the Series 3x, 4x, and 6x without microcode upgrades [comm Sep 1984] - MPE-V/E : 32033 G.xx.xx for the Series 3x, 4x, and 6x with microcode upgrades [comm Jul 1984] - MPE-V/R : 32002 E.xx.xx for the Series II and III [comm Oct 1986] - 30300A Programmable Controller : manual is 30300-90002 Feb-1975, 30000-90066 Jun-1976 2100 Computer running BCS described in 5952-4500 Apr-1975 "HP 3000CX Mini DataCenters and Subsystem Data" p.41 - 30301A RTE-C Programmable Controller : manual is 30301-90002 Feb-1975 Upd. Jul-1976 A.00.01 = 1610 (4/76 Communicator p.306) A.00.02 = 1701 (6/77 Communicator p.11) described in 5952-4500 Apr-1975 "HP 3000CX Mini DataCenters and Subsystem Data" p.45 described in 30000-90008 Jun-1977 "HP 3000 Series II Computer System General Information Manual" p.82 XRTCGEN Cross RTE-C System Generator DNLDUSER Download-Program Library routine (downloads user programs to 2100) DNLDSYS Download-System Library routine (downloads RTE operating system to 2100) LINETEST Diagnostic program BBLL Basic binary link loader RTE-C Operating system 3000 version LTEST Diagnostic program - 30301B RTE Programmable Controller : manual is 30301-90002 Feb-1975 Upd. Jul-1976. 30000-90067 Jun-1976 B.00.01 = 1636 (1/77 Communicator p.632) B.00.02 = 1701 (6/77 Communicator p.45) - 32223A 2100 Cross Assembler XA2100 : manual is 03000-90047 Mar-1975 Rev. May-1976 A.00.03 = 1543 (11/75 Communicator p.167) A.01.02 = 1709 (6/77 Communicator p.85) A.01.03 = 1814 (6/78 Communicator p.131) - 32226A 2100 Cross Loader XL2100 : manual is 03000-90107 Oct-1974 Upd. Jun-1976 A.02.00 = 1636 (1/77 Communicator p.631) "provides system generation for BCS, RTE-C, DOS-III" (5952-4500 Apr-1975 p.42) - 5952-4673 May-1975 3000CX Series Price/Configuration Guide lists: - 30300A Programmable Controller (HP2100) with BCS software included - 30361A Programmable Controller Interface Kit includes interfaces for HP 2100 and HP 3000 - 30404A BCS/3000 Field Upgrade Kit provides software to operate RT controller as standard controller - 30301A Real-Time Programmable Controller (HP2100S) with RTE-C software included - 30403A RTE-C/3000 Field Upgrade Kit provides software to operate standard controller as RT controller ------------- I/O Bandwidth ------------- From the HP 3000 Pre-Series II CE Handbook (30000-90070 Sep 1977, p CPU-1). Multiplexer Channel: - Pre-Series II: 880 KB/second - Series II: 990 KB/second Selector Channel: - Pre-Series II: 1.90 MB/second - Series II: 2.86 MB/second --------------------------------------- Changes from Pre-Series II to Series II --------------------------------------- Hardware: - 64 KW maximum core memory -> 256 KW maximum semiconductor memory - 48-bit optional floating point -> 64-bit optional floating point Machine Instructions Added to Series II: - [shift] QASL Quadruple arithmetic shift left - [shift] QASR Quadruple arithmetic shift right - [prgcntl] DISP Dispatch - [prgcntl] IXIT Interrupt exit - [prgcntl] LOCK Lock resource - [prgcntl] PCN Push CPU number - [prgcntl] PSDB Pseudo interrupt disable - [prgcntl] PSEB Pseudo interrupt enable - [prgcntl] UNLK Unlock resource - [registr] RCLK Read clock - [registr] SCLK Store clock - [move] MABS Move using absolute addresses - [move] MDS Move using data segments - [move] MFDS Move from data segment - [move] MTDS Move to data segment - [privmem] LDEA Load double word from extended address - [privmem] LSEA Load single word from extended address - [privmem] LST Load from system table - [privmem] SDEA Store double word into extended address - [privmem] SSEA Store single word into extended address - [privmem] SST Store into system table - [stackop] DDIV Double integer divide (subop 02, op 01) - [stackop] DMUL Double integer multiply (subop 02, op 01) Extended Machine Instructions Now Standard on the Series II: - [extinst] EADD Extended-precision floating-point add - [extinst] ESUB Extended-precision floating-point subtract - [extinst] EMPY Extended-precision floating-point multiply - [extinst] EDIV Extended-precision floating-point divide - [extinst] ECMP Extended-precision floating-point compare - [extinst] ENEG Extended-precision floating-point negate - [extinst] ADDD Decimal add - [extinst] SUBD Decimal subtract - [extinst] MPYD Decimal multiply - [extinst] CMPD Decimal compare - [extinst] CVAD ASCII to decimal conversion - [extinst] CVBD Binary to decimal conversion - [extinst] CVDA Decimal to ASCII conversion - [extinst] CVDB Decimal to binary conversion - [extinst] DMPY Double logical multiply - [extinst] NSLD Decimal normalizing left shift - [extinst] SLD Decimal left shift - [extinst] SRD Decimal right shift Machine Instructions Deleted from Pre-Series II: - [bit tst] TSBM Test and set bits in memory, set CC (code unused) - [I/O] SIRF Set external interrupt reference flag (code reused for SST) The EIS was an option on the CX/Series I. It became standard on the Series II/III. Also, the format changed from a three-word to a four-word representation. The 30135A System Clock/Fault Logging Interface replaced the 30031A System Clock/Console Interface, and the system console moved from a dedicated card to ATC port 0. - 3000, 3000 CX, and Series I used 30031A System Clock/Console Interface. - Series II and III used the 30135A System Clock/Fault Logging Interface with the system console on ATC port 0. I have reverse-assembled the "get" procedure in the HP32230 RL, and it works only with the ATC. So support for the 30031A is not required for the diagnostics. (Maybe "SDUP" used the 30031A, whereas "SDUPII" uses the ATC?) The August 1976 HP Journal article describing the Series II says on page 14 that the "average instruction time during an SPL compilation went from 4.08 microseconds to 2.57 microseconds. This meant that the Series II had an increase in throughput of 50% [vs. the 3000 CX]." Series III performance will be about the same, as the same CPU and virtually the same microcode are used. ------------------------------------ Changes from Series II to Series III ------------------------------------ - See "Preliminary ERS for the HP 3000-35 CPU and I-O System" for details. - Memory increased by expanding bank registers from 2 to 4 bits and memory addresses from 16 to 18 bits (maximum S-I = 64K, S-II = 256K, S-III = 1024K). - Logical configuration is 16 banks of 64K words (1024K). - LOAD and DUMP microcode now uses %1400-%1440 for register save and SIO program. Added recovery from tape write errors (backspace, gap, rewrite). - Microcode diagnostics were expanded. N^2 memory diagnostic replaced by a pattern test diagnositc. - Only changed instruction was PCN (returns 2 for S/III, 1 for S/II). - LOCK and UNLK dropped; MCU "read/write ones" memory operation dropped. - CMD "slightly modified if executed on CPU configured for interleaving." However, "This instruction is used only for diagnostics." - Four WCS instructions added (opcode = %020562, TOS selects). (Was this actually implemented? Not listed in instr set or SRM.) Instruction Set Changes ----------------------- The only standard Series II instruction that was modified was the PCN (push CPU number - opcode %020362). This instruction is now used for the purpose of determining CPU type (Series II or III) rather than CPU number, since multiple CPU configurations are not possible on the III. The firmware for the instruction was modified so that the number returned to the TOS is a 2 for the III (was 1 on Series II). IMPORTANT: In order for this instruction to operate correctly on either a Series II or III system, the MCU PCA must be configured for CPU #1. The instructions LOCK (opcode %020361) and UNLK (opcode %020363) will not be supported on the III since the new memory does not have "read/write-ones" capability. The function of the CMD instruction will be slightly modified if executed on a III configured for interleaving. This is due to the address mapping that takes place. The effect will be that the least significant bit of the parameter being passed to the destination module may be inverted. This should not be a problem on the III, since this instruction is used only by diagnostics. From a functional standpoint, any instruction that referenced a bank register in any way on Series II will now reference a four bit register on the III. ------------------------------------ Device Controller Parameter Defaults ------------------------------------ Per Series III CE Handbook, pp 5-2 and 5-3: Device DEVNO INTPRI INTMASK SRNO Notes ------ ----- ------ ------- ---- ----------------------- FLI 2 - - - DEVNO is fixed CLK 3 1 - - DS 4 4 E - MS 6 11 E 3 ATCD 7 0 E - ATCC 8 8 E - LPT 14 12 E 11 SCMB 65 10 E 0 DEVNO/INTPRI any unused MUX 127 - - - ----------------------------- Controller Interrupt Priority ----------------------------- Typical interrupt priorities, from highest to lowest. Per 7905A Installation and Service Manual (30129-90003, May 1976): - 30031A System clock/console - 30032B Terminal data interface - 30061B Terminal controller interface - 30129A 7905A cartridge disc - 30110A 7900A cartridge disc - 30102A 2888A disc - 30055A Synchronous single-line controller - 30115A 7970 magnetic tape - 30105A Paper tape punch - 30104A Paper tape reader - 30108A/13A/18A Line printers 200/300 lpm - 30109A/28A Line printers 600/1250 lpm - 30050A Universal interface (TTL) - 30051A Universal interface (differential) - 30106A Card reader 600 cpm - 30107A Card reader 1200 cpm - 30226A Calcomp plotter Per Series II System Installation Manual (30000-90019 June 1976, p 3-2): - Terminal data interface - System clock/console - Paper tape reader - Synchronous single-line controller - 7905A cartridge disc - 2660A fixed-head disc - 7900A cartridge disc - 2888A disc file - Terminal controller interface - Hardwired serial interface - HP-IB interface module - Calcomp plotter - 7970 magnetic tape - Line printers - Card reader - Card punch - Paper tape punch Per Series III CE Handbook (30000-90172 July 1981, p 5-4): - 30032B Terminal data interface - 30135A System clock/FLI - 30104A Paper tape reader - 30055A Synchronous single-line controller - 30229B 7905A cartridge disc - 30061B Terminal controller interface - 30360A Hardwired serial interface - 30341A HP-IB interface module - 30226A Calcomp plotter - 30300A Programmable controller - 30215A 7970 magnetic tape - 30010A Intelligent Network Processor - ------ Line printers (all) - 30106A Card reader - 30119A Card reader/punch - 30105A Paper tape punch ----------------------------------- Controller Service Request Priority ----------------------------------- Per Series III System Installation Manual, appendix E: 0 - reserved for the SCMB 3 - 7970B/E magnetic tape 4 - Hardwired serial interface 5 - Hardwired serial interface 6 - Card reader 7 - Synchronous single-line controller 8 - Intelligent network processor 9 - Plotter 10 - Paper tape punch 11 - Line printer 12 - Line printer 13 - Line printer 14 - Paper tape reader 15 - Card reader/punch --------------------- Device Support Matrix --------------------- CX I II III Model --- --- --- --- -------------------------------------------------- Y Y - - 30006A 8K Word Core RAM - - Y - 30008A 32K Word ECC RAM - - - Y 30008B 128K Word ECC RAM Y Y - - 30030A Selector Channel Y Y Y - 30030B Selector Channel - - - Y 30030C Selector Channel Y Y - - 30031A System Clock/Console Interface Y Y Y Y 30032B Asynchronous Terminal Controller Y Y ? ? 30033A Selector Channel Maintenance Board Y Y - - 30035A Multiplexer Channel - - Y - 30036A Multiplexer Channel - - - Y 30036B Multiplexer Channel Y Y Y Y 30055A Synchronous Single-Line Controller Y - Y - 30102A Moving Head Disc (2888A) Y - Y - 30103A Fixed Head Disc (2660A-002) Y Y Y Y 30104A 2748B Paper Tape Reader Subsystem (2748B) Y Y Y Y 30105A 2895A Paper Tape Punch Subsystem (2895A) Y Y Y Y 30106A Card Reader (2893A) Y - Y - 30110A Cartridge Disc (7900A) Y Y Y Y 30119A Card Reader/Punch (2894A) Y Y Y Y 30126A Calcomp Plotter - - Y Y 30135A System Clock/Fault Logging Interface Y Y Y - 30209A Line Printer Subsystem (2607A) - - - Y 30209A Line Printer Subsystem (2608A) Y Y Y Y 30209A Line Printer Subsystem (2613A) Y Y Y Y 30209A Line Printer Subsystem (2617A) Y Y Y Y 30209A Line Printer Subsystem (2618A) Y Y Y Y 30215A Magnetic Tape Interface (7970B/E) Y Y Y Y 30229A Disc Controller Interface (7920/25) - - - Y 30341A HP-IB Interface Module - - Y Y 30360A Hardwired Serial Interface ------------------------------ Supported Disc and Tape Drives ------------------------------ 40 42 44 48 42XP 52 58 Model --- --- --- --- ----- --- --- -------------------------------- Y Y Y Y Y Y Y 7911P Opt. 140 (deletes CTD) Y Y Y Y Y Y Y 7912P Opt. 140 (deletes CTD) Y Y Y Y Y Y Y 7914P Opt. 140 (deletes CTD) Y Y Y Y Y Y Y 7920M/S (requires 12745A HP-IB interface) Y Y Y Y Y Y Y 7925M/S (requires 12745A HP-IB interface) Y Y Y Y Y Y Y 7933H Y Y Y Y Y Y Y 7935H Y Y Y Y Y Y Y 7936H (requires MPE V/E T-delta-6 or later) Y Y Y Y Y Y Y 7937H (requires MPE V/E T-delta-6 or later) Y Y Y Y Y Y Y 7945A (requires MPE V/E T-MIT or later) Y Y Y Y Y Y Y 7957A (requires MPE V/E UB-delta-1 or later) - - Y Y - - Y 7957B (requires MPE V/E V-delta-1 or later) Y Y Y Y Y Y Y 7958A (requires MPE V/E UB-delta-1 or later) - - Y Y - - Y 7958B (requires MPE V/E V-delta-1 or later) - - Y Y - - Y 7959B (requires MPE V/E V-delta-1 or later) - - Y Y - - Y 7961B (requires MPE V/E V-delta-1 or later) - - Y Y - - Y 7962B (requires MPE V/E V-delta-1 or later) - - Y Y - - Y 7963B (requires MPE V/E V-delta-1 or later) Y Y Y Y Y Y Y 7970E Y Y Y Y Y Y Y 7974A Y Y Y Y Y Y Y 7976A Y Y Y Y Y Y Y 7978A Y Y Y Y - - Y 7979A (requires MPE V/E UB-delta-3 or later) Y Y Y Y - - Y 7980A (requires MPE V/E UB-delta-3 or later) Y Y Y Y Y Y Y 9144A (requires MPE V/E T-MIT or later) Y Y Y Y Y Y Y 35401A (requires MPE V/E U-MIT or later plus patch M009) ------------------------------ Controller Channel Assignments ------------------------------ Sel Mux Model --- --- ------------------------------------------------ - - 30032B Asynchronous Terminal Controller - M 30055A Synchronous Single-Line Controller S M 30102A 2888A Disc S M 30103A 2660A Drum - M 30106A Card reader - M 30110A 7900A Disc Interface - M Intelligent network processor - M 30119A Card reader/punch - M 30126A Plotter - M 30204A 2748B Paper Tape Reader Interface - M 30205A 2895A Paper Tape Punch Interface - M 30209A 2607A/13A/17A/18A Line Printer Interface - M 30215A Magnetic Tape Controller Interface S - 30229A Disc Controller Interface - - 30341A HP-IB Interface Module - M 30360A Hardwired Serial Interface ----------- Front Panel ----------- LEDs - Current Instruction Register (16) - System Switch Register (16) - System Halt Flip-Flop - Run Flip-Flop - Battery Status Pushbutton Switches - System Switch Register (16) - Load -- Dump - Run/Halt -- Enable Toggle Switches (behind panel): - CPU Reset (spring return) - Powerfail/Auto-Restart Enable/Disable - Front Panel Enable/Disable Jumpers (behind panel): - control byte (MSB) and DRT number (LSB) for DUMP (gated onto switch register lines) ------------------- PCA Jumper Settings ------------------- System Control Panel - XW1 (Dump DRT number) set to 6 - XW2 (Dump control byte) set to 4 (write) 30003A IOP - S3 (memory size) set to 128K, 256K, 384K, 512K, 768K, 1024K 30030A Selector Channel - S3 (memory size) set to 128K, 256K, 384K, 512K, 768K, 1024K - XW1/3/4 (channel number) set to channel 1, 3, 4 (channel 2 not available) 30033A Selector Channel Maintenance Board - W1 (test channel) set to SC (selector channel) or MX (multiplexer channel) - W2 (multiplexer service request) set to 0-15 (any unused value; no default) - W3 (device number) set to 0-127 (any unused value; no default) - IRQ is not maskable (does not have an Interrupt Mask FF) Note: if W1 = MX, the Selector Channel Diagnostic verifies the SCMB Note: the SCMB is needed to run CPU diag section 4 steps 40-41 and MPX diag section SIOTEST 30036A Multiplexer channel - S1 (device number) set to 177B 30135A System Clock/Fault Logging Interface - WX (clock device number) set to 3 - clock IRQ is not maskable (does not have an Interrupt Mask FF) - FLI device number permanently set to 2 - FLI does not interrupt 30229A 7920 disc controller - W1 (preset disable) installed - W2 (interrupt mask) set to ENABLE - S1 (device number) set to 4 - S2 (interface address) set to 0 30115A 7970B/E magnetic tape controller - W1 (service request) set to 3 - W2 (interrupt mask) set to ENABLE - S1 (device number) set to 6 30032B ATC data - W4 (interrupt mask) set to ENABLE - S1 (device number) set to 7 30032B ATC control - W1 (interrupt mask) set to ENABLE - S1 (device number) set to 10B 30118A 2607A line printer - W4 (interrupt mask) set to ENABLE - W5 (service request) set to 11 - S1 (device number) set to 16B 30204A 2748B Paper Tape Reader Interface - W4 (service request) set to 14 - W5 (interrupt mask) set to ENABLE - S1 (device number) set to 24B 30205A 2895A Paper Tape Punch Interface - W4 (service request) set to ?? - W5 (interrupt mask) set to ENABLE - S1 (device number) set to 25B 30341A HP-IB Interface Module ("Starfish") [reference: CE handbook pages 111, 237-244 of 30000-90172 July 1981] - (device number) set to 125 (%175) ------------------------------- Module Control Priority Numbers ------------------------------- 0 - Memory, lower bank 1 - " 2 - Memory, higher bank 3 - " 4 - Selector Channel Port Controller 5 - CPU/IOP 6 - 7- The two memory modules respond to module numbers 0 and 1 or 2 and 3. ---------------------- Module Operation Codes ---------------------- Memory: NOP (00), Write (01), Read (10). Read/Write Ones (11) for S-II only; treated as NOP by S-III. ----------------- I/O Documentation ----------------- 30033A Selector Channel Maintenance Board - 30000-90018 pages 4-4 through 4-14 - 30000-90172 page 4-10 - 30030-90011 pages 24-25 - 30036-90001 page 16 30036B Multiplexer channel - 30035-90001 Multiplexer Channel Maintenance Manual - 30036-90001 page 15 30135A System Clock/Fault Logging Interface - CLK: 32230-90005 page 8 - FLI: 30000-90143 para 6-23, page 6-21 30031A System Clock/Console Interface - 30000-90070 page CLOCKC-1 (PDF 297) 30032B Asynchronous Terminal Controller - 30032-90004 Section 2 and 30000-90172 page 8-54 30215A Tape controller - 30115-90014 page 17 and 30000-90172 page 8-45 30229A Disc controller - 30129-90007 page 17 and 30000-90172 page 8-37 30209A Line Printer - 30051-90001 Section 2 - 30000-90172 page 8-6 ---------------------------- SIO Cold Load/Dump Microcode ---------------------------- III CE handbook has this; it's different from II! 000030 := 001430 001430 := 014000 (set bank = 0) 001431 := 000000 001432 := 040000 (control, word 1 = 0, word 2 = 6 [read record]) 001433 := 000006 001434 := 077760 (read, count = 16, address = %1400) 001435 := 001400 001436 := 000000 (jump, address = %1400) 001437 := 001400 SLEUTH tape (D411) record 1 - 040000 (control, word 1 = 0, word 2 = 6 [read record]) 000006 - 077400 (read, count = 256, address = %7200) 007200 - 000000 (jump, address = %7200) 007200 record 2 - 040000 (control, word 1 = 0, word 2 = 7 [forward space record]) 000007 - 050000 (sense, status returned P+1) 177777 - 040000 (control, word 1 = 0, word 2 = 6 [read record]) 000006 - 076000 (read, count = 1024, address = %0) 000000 - 040000 (control, word 1 = 0, word 2 = 7 [forward space record]) 000007 - 040000 (control, word 1 = 0, word 2 = 6 [read record]) 000006 - 076000 (read, count = 1024, address = %2000) 002000 - 020000 (interrupt) 000000 - 030000 (end, status returned P+1) 000000 MPE V/R: (cold load) 1430: SETBNK 00 1432: CONTRL 000000,000006 1434: READ #16,001400 1436: JUMP 001400 (record 1) 1400: CONTRL 000000,000006 1402: READ #18,002000 1404: JUMP 002000 (record 2) 2000: CONTRL 000000,000007 2002: CONTRL 000000,000007 2004: CONTRL 000000,000007 2006: CONTRL 000000,000007 2010: CONTRL 000000,000007 2012: CONTRL 000000,000007 2014: CONTRL 000000,000006 2016: READ #32,001400 2020: JUMP 001400 (record 8) 1400: SETBNK 00 1402: CONTRL 000000,000006 1404: READ #152,002000 1406: JUMP 002000 (record 9) 2000: CONTRL 000000,000006 2002: READ #40,174000 2004: CONTRL 000000,000006 2006: READ #12,000000 2010: CONTRL 000000,000006 2012: READ #128,173600 2014: CONTRL 000000,000006 2016: READ #287,113511 2020: CONTRL 000000,000006 2022: READ #834,114150 2024: CONTRL 000000,000006 2026: READ #278,115652 2030: CONTRL 000000,000006 2032: READ #695,116300 2034: CONTRL 000000,000006 2036: READ #202,117567 2040: CONTRL 000000,000006 2042: READ #695,120101 2044: CONTRL 000000,000006 2046: READ #42,121370 2050: CONTRL 000000,000006 2052: READ #14,121442 2054: CONTRL 000000,000006 2056: READ #256,121460 2060: CONTRL 000000,000006 2062: READ #1024,122060 2064: CONTRL 000000,000006 2066: READ #128,124060 2070: CONTRL 000000,000006 2072: READ #128,124260 2074: CONTRL 000000,000006 2076: READ #256,124460 2100: CONTRL 000000,000006 2102: READ #4096,125060 2104: CONTRL 000000,000006 2106: READ #4096,135060 2110: CONTRL 000000,000006 2112: READ #4096,145060 2114: CONTRL 000000,000006 2116: READ #577,155060 2120: CONTRL 000000,000006 2122: READ #12,156161 2124: SETBNK 01 2126: CONTRL 000000,000006 2130: READ #188,177454 2132: CONTRL 000000,000006 2134: READ #1848,173764 2136: CONTRL 000000,000006 2140: READ #4096,141754 2142: CONTRL 000000,000006 2144: READ #4096,151754 2146: CONTRL 000000,000006 2150: READ #4096,161754 2152: CONTRL 000000,000006 2154: READ #1032,171754 2156: CONTRL 000000,000006 2160: READ #4096,117320 2162: CONTRL 000000,000006 2164: READ #4096,127320 2166: CONTRL 000000,000006 2170: READ #1308,137320 2172: CONTRL 000000,000006 2174: READ #2476,112444 2176: CONTRL 000000,000006 2200: READ #2436,105640 2202: CONTRL 000000,000006 2204: READ #3276,077324 2206: CONTRL 000000,000006 2210: READ #2840,071674 2212: CONTRL 000000,000006 2214: READ #3196,063500 2216: CONTRL 000000,000006 2220: READ #2784,056140 2222: CONTRL 000000,000006 2224: READ #2888,050430 2226: ENDINT 000000 ----- DPAN4 ----- The MPE dump analyzer reads the tape produced by the cold dump microcode and formats it for interpretation. Three points are of interest: - After a RELOAD, running DPAN4.PUB.SYS produces a "CODE SEGMENT TOO LARGE (LOAD ERR 33)" error. This is because MPE defaults to an 8K code segment size limit, and DPAN4 has three segments between 8K and 12K in size. The limit must be raised via a SYSDUMP and COLDSTART reconfiguration before DPAN4 will run. - If the upper byte of the machine ID word (memory word %1400) is non-zero, it is interpreted as a DRT number, and the values from memory words %1422-1425 are restored to the four-word DRT entry prior to DPAN4 interpretation. This is intended for use when a Starfish tape drive is used as the dump device; the original DRT values are saved before dumping changes them. - A normal shutdown and HALT %17 may be accompanied by a spurious SYSTEM FAILURE message in the first page REGISTERS summary. This is caused by procedure ANALYZE'HALT in module SC8S002C. It attempts to determine the reason for the halt by looking at the parameter (at Q - 4) passed to the procedure that performed the HALT %17. For the SUDDENDEATH procedure in module INCLHARD, which also does a HALT %17, this is indeed the system failure number. But for the CONSSHUTDOWN prcedure in module PROGEN, this is a byte array pointer to the =SHUTDOWN command. If the halt code is >= %15 and the pointer value is less than 2000, then it is assumed to be a call from SUDDENDEATH, and the code is printed. ------------ MPE Load Map ------------ The load map printed at the end of a reload has this format: () Where: csn = Code Segment Table number in octal sl-name = Segment name lsn = SL.PUB.SYS logical segment number in octal A copy of the map is kept in the LOADMAP.PUB.SYS file. ------------------ Code Segment Table ------------------ References: - Communicator/3000 Volume 2 Issue 1, 5955-1770, July 1984. - S00S002C lines 68430-68606. The code segment table contains four-word entries describing the code segments of programs, user/group segmented libraries, and the system segmented library. The CPU Status Register has an eight-bit field to indicate the currently executing code segment number. The table is partitioned into two areas: the CST comprising entries 0-191, and the CST extension, comprising entries 192-255. The actual CST and CSTX areas are contiguous and reside in a data segment. The CST holds entries for MPE segments, system SL segments, and user/group SL segments, and is shared among all processes. MPE segments and system SL segments identified as permanently allocated are assigned static CST entries by INITIAL. System and user/group SL segments that are referenced by running programs are allocated CST entries dynamically. Without MPE V/E mapping firmware, this table is always 192 entries in size. With mapping firmware, this table can be as large as 2048 entries, with the first 254 entries reserved for MPE segments (254 is the maximum number of segments that can reside in an SL file, in this case SL.PUB.SYS). For the latter, the first 254 entries are in the "physical domain" CST, and the remainder are in the "logical domain" CST. Most of the MPE system segments reside in the system SL. The few that do not reside in program files and include ININ and the disc, tape, and printer drivers. After cold loading, INITIAL scans SL.PUB.SYS and allocates static CST entries for each SL segment that is marked SYSTEM or PERMANENTLY ALLOCATED. The CSTX holds sets of entries for all loaded programs, with one set for the code segments of each program. This table can be as large as 8191 entries. Without mapping firmware, each set can be as large as 63 entries. With mapping firmware, each set can be as large as 255 entries. The entries are all assigned dynamically when programs are loaded or :ALLOCATEd. Code segment numbers in external program labels and stack markers are designated as physically or logically mapped by the value of a mapping bit within the object. Physically mapped segment numbers are used directly as indices into the first 254 CST entries. Logically mapped segment numbers are split into those representing program segments and those representing user SL segments; the count of program segments is given by the value in SYSGLOB location %223. Program segment numbers are used as indices into the CSTX to get the code segment entry. SL segment numbers are used as indices into the Logical Segment Transform Table (LSTT) set up by the loader for the currently executing program, from which the indices into the CST are obtained. The LSTT is created only if a program references user SL segments; if there are none, then the LSTT is omitted. The bank and offset of the current process' LSTT is located in SYSGLOB locations %221 and %222. These locations will be zero if the table is omitted. Memory location 0 points to the origin of the CST entries; these are for control information (entry 0), internal interrupt service (entry 1), and external interrupt service, system intrinsics, and library procedures (entries 2-N). Entry 0 of the CST contains control information rather than segment information, as follows: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Number of entries | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Entry length in words | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Number of available entries | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Table-relative index to first free entry | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Each CST entry from 1-N contains four words, formatted as follows: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | A | M | R | T | Segment length / 4 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - | O | I | - | - | - | S | C | | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Bank address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Base address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ ...where: A = Absent (1 = segment is absent from memory) M = Mode (1 = segment executes in privileged mode only) R = Reference (1 = segment has been referenced; set by microcode) T = Trace (1 = segment is to be traced) O = Overlay (1 = segment is a recoverable overlay candidate) I = In (1 = segment is in motion in) S = System (1 = segment is a system segment) C = Core (1 = segment is core-resident) Bank address = memory bank in which segment resides Base address = absolute address of PB within bank If the A bit is 1, words 3 and 4 contain the absolute disc address of the segment, as follows: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Logical device number | High order disc address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Low order disc address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ If the CST entry is free, words 1 and 2 are as follows: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | %100000 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Table-relative offset to next free entry | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ ---------------------------- Code Segment Table Extension ---------------------------- The Code Segment Table Extension follows the CST in memory and consists of four-word entries grouped into blocks, with one block for each loaded program. Each block consists of control information (entry 0) and segment information for each segment of the program (1-N). Memory location 1 points to the origin of the CST Extension block for the currently executing program. Entry 0 of a CST Extension block contains control information rather than segment information, as follows: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Number of entries in this block | CSTX + 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | %125252 | CSTX + 1 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Number of users sharing this block | CSTX + 2 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | %000000 | CSTX + 3 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Each CST Extension entry from 1-N contains four words, with the same format as the CST entries above. ------------------ Data Segment Table ------------------ Memory location 2 points to the origin of the DST for entries 0-n; these are for control information (entry 0) and all other system and user data segments (entries 1-n). Entry 0 of the DST contains control information rather than segment information, as follows: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Number of entries | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Entry length in words | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Number of available entries | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Table-relative index to first free entry | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Each DST entry contains four words, formatted as follows: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | A | C | R | Segment length / 4 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | V | O | I | K | M | F | S | C | D | VM allocation | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Bank address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Base address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ ...where: A = Absent (1 = segment is absent from memory) C = Clean bit (1 = data has not been modified) R = Reference (1 = segment has been referenced; set by microcode) V = Valid (1 = disc copy is valid) O = Overlay (1 = segment is a recoverable overlay candidate) I = In (1 = segment is in motion in) K = Stack (1 = segment is a stack) M = Mod (1 = a segment change in size or location is requested) F = Force (1 = a forced write of this segment is in progress) S = System (1 = segment is a system segment) C = Core (1 = segment is core-resident) D = Disabled (1 = write is disabled) VM allocation = number of VM pages allocated to this segment Bank address = memory bank in which segment resides Base address = absolute segment address within bank If the A bit is 1, words 3 and 4 contain the absolute disc address of the segment, as follows: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Logical device number | High order disc address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Low order disc address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ If the DST entry is free, words 1 and 2 are as follows: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | %100000 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Table-relative offset to next free entry | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ ---------------------- Segment Transfer Table ---------------------- Register PL points to the origin of the STT. The STT is arranged in order of decreasing memory addresses, so entry 0 is at PL, entry 1 is at PL-1, etc. Entry 0 is reserved for control information (the number of the last STT entry). Each STT entry contains one word. The format depends on the MPE version, as follows: Pre-MPE V/E ----------- STT Length (entry 0) 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | U | 0 0 0 0 0 0 | Number of labels | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Local Program Label 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | U | Address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ External Program Label 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | STT Number | Segment Number | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ MPE V/E ------- STT Length (entry 0) 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Number of local labels | Total number of labels | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Local Program Label 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | U | Address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ External Program Label 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | M | STT Number | Segment Number | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ ...where: U = Uncallable (1 = procedure is callable from privileged mode only) M = Mapped (1 = segment number is physically mapped) Address = PB-relative address of procedure entry STT Number = STT entry within target segment Segment Number = number of target segment For MPE V/E with new firmware, the STT is arranged with all local labels placed immediately prior to the STT header, i.e., at PL-1 through PL-N, where N is the number of local labels, and all external labels at PL-N-1 through PL-T, where T is the total number of labels. ------------ Stack Marker ------------ Executing a PCAL pushes a four-word marker onto the stack. The format depends on the MPE version, as follows: Pre-MPE V/E ----------- 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | X register value | [Q - 3] X +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | T | PB-relative return address | [Q - 2] P + 1 - PB +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Status register value | [Q - 1] STA +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | D | Delta Q value | [Q - 0] S - Q +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ MPE V/E ------- 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | X register value | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | T | M | PB-relative return address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Status register value | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | D | Delta Q value | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ ...where: T = Trace (1 = trace or control-Y interrupt pending) M = Mapped (1 = code segment is physically mapped) D = Dispatcher was interrupted For MPE V/E, the firmware keeps a hidden internal flag that records whether the current segment is physically or logically mapped. The flag determines the value of the M bit in the stack marker and is used with the segment number in the Status register value to locate the CST entry of the segment to which the return is being made. ------------------------------- Logical Segment Transform Table ------------------------------- If the current program references any user SL segments, then it uses the LSTT indicated by the bank and offset specified in SYSGLOB + %221 and %222 (absolute addresses %1221 and %1222). If the current program does not reference user SL segments, then it does not use an LSTT, and these locations will be zero. 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Mapping firmware flag | SYSGLOB + %220 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | LSTT bank of current process | SYSGLOB + %221 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | LSTT offset of current process | SYSGLOB + %222 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Number of code segments of current process | SYSGLOB + %223 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ The LSTT is divided into three major sections: the header, the segment map, and the STT map. The first two words are the header and contain the number of logical segments in the segment map and the total length of the table in words. The segment map consists of two-word entries, one for each logical program segment and user SL segment referenced by the program. Each entry contains the physical segment number, which is an index into the CSTX (for program segments) or CST (for user SL segments) and the offset to the STT map for the segment. STT maps are only used for user SL segments; the offset will be zero if the STT in the code segment is to be used. The STT map consists of one STT for each user SL segment. The STT contains only external labels from the code segment's STT; the number of local labels field will always be zero. The STT map is needed for shared (SL) segments because each process calling the segment may reference it with a different logical segment number, depending on the number of program code segments in the calling process. An STT map lookup is indicated by the external mapped label in the code segment's CST having a segment number of zero. 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Number of logical segments in table | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Length of table in words | +===+===+===+===+===+===+===+===+===+===+===+===+===+===+===+===+ | Physical segment #1 | \ +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ + Logical Segment #1 | Offset to STT #1 length word | / +~~~+~~~+~~~+~~~+~~~+~~~+~~~+~~~+~~~+~~~+~~~+~~~+~~~+~~~+~~~+~~~+ | Physical segment #2 | \ +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ + Logical Segment #2 | Offset to STT #2 length word | / +~~~+~~~+~~~+~~~+~~~+~~~+~~~+~~~+~~~+~~~+~~~+~~~+~~~+~~~+~~~+~~~+ | | + Up to 255 logical segment entries + | | +~~~+~~~+~~~+~~~+~~~+~~~+~~~+~~~+~~~+~~~+~~~+~~~+~~~+~~~+~~~+~~~+ | Physical segment #N | \ +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ + Logical Segment #N | Offset to STT #N length word | / +===+===+===+===+===+===+===+===+===+===+===+===+===+===+===+===+ | M | STT Number | Segment Number | \ +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | | . . . . | | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ + Logical Segment #1 | M | STT Number | Segment Number | | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | | Number of local labels | Total number of labels | / +===+===+===+===+===+===+===+===+===+===+===+===+===+===+===+===+ | M | STT Number | Segment Number | \ +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | | . . . . | | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ + Logical Segment #2 | M | STT Number | Segment Number | | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | | Number of local labels | Total number of labels | / +===+===+===+===+===+===+===+===+===+===+===+===+===+===+===+===+ | | + Up to 255 logical segment entries + | | +===+===+===+===+===+===+===+===+===+===+===+===+===+===+===+===+ | M | STT Number | Segment Number | \ +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | | . . . . | | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ + Logical Segment #N | M | STT Number | Segment Number | | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | | Number of local labels | Total number of labels | / +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ One odd point is that the MPE V/E loader apparently requires LSTT lookups for physically mapped segments (e.g. PRINT or TERMINATE') when called from user SL segments. These calls will have code segment STT external labels with their segment number fields set to zero; the resulting LSTT lookup yields the physically mapped label for the called procedure. It is not clear why simply placing the physically mapped label in the code segment's STT wouldn't work. ------------------------------------- 30031A System Clock/Console Interface ------------------------------------- Control Word Format (CIO): 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | M / rate | R | I | irq reset | X | L | Y | E | C | - | Z | J | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Key: M = master reset (if bit 3 = 0) R = load count rate I = enable console interrupts X = reset count register after LR=CR interrupt L = RIO/WIO to limit/count (0/1) register Y = reset all interrupts E = echo received data C = RIO/WIO to console/timer (0/1) Z = reset console logic J = enable clock interrupts Status Word Format (TIO): 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | S | D | rate | V | I | O | T | E | L | F | B | Q | X | R | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Key: S = SIO OK (always 0) D = direct read/write I/O OK (always 1) V = input data overrun I = input data ready O = ready for output data T = DTR E = count register read error (was incrementing) L = limit register = count register F = limit register = count register overflow (lost tick) B = break received Q = interrupt request X = limit/count (0/1) register selected R = reset count register after interrupt ------------------------------------------- 30135A System Clock/Fault Logging Interface ------------------------------------------- - CLK: 32230-90005 page 8 - FLI: 30000-90143 para 6-23, page 6-21 System Clock Control Word Format (CIO): 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | M / rate | R | - | irq reset | X | L | A | - - - - | E | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Key: M = master reset (if bit 3 = 0) R = master clear enable/load count rate X = reset count register after LR=CR interrupt L = WIO addresses limit/count (0/1) register A = reset all interrupts E = enable clock interrupts Count Rate Selection: 000 = unused 001 = 10 microseconds 010 = 100 microseconds 011 = 1 millisecond 100 = 10 milliseconds 101 = 100 milliseconds 110 = 1 second 111 = 10 seconds IRQ Reset: 000 = none 001 = clear LR = CR interrupt 010 = clear LR = CR overflow interrupt 011 = clear I/O system interrupt (SIN) 100 = unused 101 = unused 110 = unused 111 = unused System Clock Status Word Format (TIO): 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | S | D | rate | - - - - - | L | F | - | Q | X | R | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Key: S = SIO OK (always 0) D = direct read/write I/O OK (always 1) L = limit register = count register F = limit register = count register overflow (lost tick) Q = I/O system interrupt request (SIN) X = limit/count (0/1) register selected R = reset count register after interrupt System Clock Output Data Word Format (WIO): 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | limit register value/count register reset | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ If control bit 9 is 0, the value is written to the limit register. If control bit 9 is 1, the count register is cleared to zero; the output value is ignored. System Clock Input Data Word Format (RIO): 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | count register value | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Master Reset clears: - the Count Register - the Limit Register - the Count Rate Register - the clock division counters - the Interrupt Active flip-flop - the System Interrupt flip-flop - the LR=CR Interrupt flip-flop - the LR=CR Overflow Interrupt flip-flop - the Enable Clock Interrupts flip-flop - the Reset Count Register after LR=CR Interrupt flip-flop - the Address Limit/Count Register flip-flop --------------------------------------- 30032B Asynchronous Terminal Controller --------------------------------------- TDI Control Word Format (CIO): 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | M | R | channel number | - - - - - - - | E | A | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: M = master reset R = reset interrupts E = enable store of preceding data or parameter word to memory A = acknowledge interrupt TDI Status Word Format (TIO): 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | S | D | I | - | C | R | L | B | - - - - - - - - | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: S = SIO OK (always 0) D = direct read/write I/O OK I = interrupt request C = read/write completion flag R = receive/send (0/1) character interrupt L = character lost B = break status TDI Parameter Word Format (WIO): 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | R | I | E | D | char size | baud rate | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: R = receive/send (0/1) configuration I = enable channel completion interrupt E = enable echo (receive) or generate parity (send) D = diagnose using the auxiliary channels Character size: The three least-significant bits of the sum of the data, parity, and stop bits. For example, 7E1 is 1001, so 001 is coded. Baud rate: The value (14400 / device bit rate) - 1. For example, 2400 baud is 005. TDI Output Data Word Format (WIO): 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | - - | S | send data | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: S = sync bit data = right-justified with leading ones TDI Input Data Word Format (RIO): 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | channel | P | receive data | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: P = computed parity data = right-justified with leading ones TCI Control Word Format (CIO): 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | M | R | S | U | channel | W | X | Q | T | Y | Z | C | D | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: M = master reset R = reset interrupts S = scan status U = enable CD/DSR state update W = enable RTS change X = enable DTR change Q = new RTS state T = new DTR state Y = CD interrupt enabled Z = DSR interrupt enabled C = expected CD state D = expected DSR state TCI Status Word Format (TIO or RIO): 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 1 | I | 1 | channel | 0 | 0 | J | K | Y | Z | C | D | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: I = interrupt request J = CD interrupt present K = DSR interrupt present Y = CD interrupt enabled Z = DSR interrupt enabled C = current CD state D = current DSR state TDI: circulating ram contents 256 words x 8 bits in two 256 x 4 shift registers 7 words allocated per channel 16 send channels + 16 receive channels + 5 diagnose channels = 37 channels 7 * 37 = 259 words 36 channels kept in MOS shift registers (7 * 36 = 252 words + 4 unused) + 1 channel ("current" channel) kept in external TTL shift registers total words = 263 clock pauses 1 time in 7, so 8 clocks per used word + 4 clocks unused total clocks = 300 per rotation 4.32 MHz clock, so 69.444 usec per rotation 2400 baud output takes 6 rotations per bit * 10 bits per char = 6 * 69.444 * 10 = 4.167 msec per char * lower 4 bits - status (break, char lost, start bit, buffer flag) - baud rate (3-0) - sample count (7-4) - baud rate (7-4) - sample count (3-0) - char size (10-8) - bit count * upper 4 bits - parameters (diagnose, enable, configure, echo/parity) - input accumulator (10-8, parity) - output buffer - input accumulator (6-3) - output buffer - input accumulator (2-0, 11) - output buffer Master reset (IORESET or DCONTSTB * D0): - sets INTMASK FF - clears INTREQ FF - clears INTACT FF - sets INITIALIZE FF - clears REQ XFER DN FF - clears the field counter - clears the address counter - clears AUX/MAIN FF Setting the initialize FF does: - clears XFER UP FLAG FF - clears XFER DN FLAG FF - clears the input buffer FF - clears the output buffer registers - clears the AUX CHAN MEMORY FF - clears all of the upper and lower recirculation path registers The FF clears when a DCONTSTB * ~D0 is done. For the 12920A, the flag must be removed before merging the status, as that device doesn't report the flag bit. The base product 30032 ATC consists of one TDI card. Option -001 added one TCI, and option -002 added two. Output modes UC, 7P, 7B, 8B. Input mode CAPSLOCK or no CAPSLOCK. New control structure: - call tmxr_set_modem_control_passthru() to enable modem control in atcc_reset() -P - call tmxr_set_get_modem_bits() in DCONTSTB to set/clear per control word if DTR drops, it calls tmxr_reset_ln() internally won't connect a telnet line with DTR low - call tmxr_set_get_modem_bits() in a loop in poll_service() to get line status call must be after tmxr_poll_rx() to pick up dropped lines line status must be stored in tci_lines[] for processing by scan_status() For 3.9, emulations are used in sim_txmr.c: - tmxr_set_modem_control_passthru() is a nop - tmxr_set_get_modem_bits() - DTR in clear_bits calls tmxr_reset_ln() - DCD and DSR are set or cleared, depending on lp->conn status TCI: - C2 = RTS (CA) - C1 = DTR (CD) - S2 = DCD (CF) - S1 = DSR (CC) Bell 103A has: - CTS (CB) - DSR (CC) - DCD (CF) - DTR (CD) - RI (CE) Hardware actions: - DTR on to allow dataset to answer a call - DTR off to tell dataset to disconnect a call - DCD on when the dataset receives the carrier (caller connects) - DCD off when the dataset loses the carrier (caller disconnects) - DSR on when the dataset has answered a call (line in data mode) - DSR off when the dataset has lost a call (line not in data mode) Simulator actions: - DTR on => allow new connection: set lnorder to line number - DTR off => drop line: tmxr_reset_ln(), DCD off, DSR off prevent new connection: set lnorder to TMXR_LN_SKIP [?] - DCD on => when tmxr_poll_conn() != -1 - DCD off => when DTR off or line drops within tmxr_poll_rx - DSR on => when tmxr_poll_conn() != -1 - DSR off => when DTR off or line drops within tmxr_poll_rx simulations: - telnet connects = modem answers a call = tmxr_poll_conn connects => DCD, DSR on - telnet disconnects = modem caller hangs up = tmxr_poll_rx closes a line => DCD, DSR off - :ABORTJOB = modem commanded to hang up = tmxr_reset_ln called => DTR off => telnet disconnected - SET ATCDn DISCONNECT [allow?] = modem commanded to hang up = tmxr_dscln called => DTR off => telnet disconnected - :REFUSE allows a modem to connect (DTR is on), but MPE ignores input for logon The MPE driver sets these control values: - %030324, << SET DTR (CD), MONITOR FOR DSR (CC) = 1 >> - %030017, << MONITOR FOR CDET (CF) AND DSR (CC) = 0 >> - %030217, << CLEAR RTS (CA), MONITOR FOR CDET (CF) & DSR (CC) = 0 >> - %030300, << CLEAR RTS (CA) & DTR (CD); STOP MONITORING CDET (CF) & DSR (CC) >> - %030255; << SET RTS (CA); MONITOR FOR CDET (CF)=1, DSR (CC)=0 >> ...for these control operations: - 0 - INITIALIZE AND MAKE READY FOR LOGON - 1 - START WRITE TURNAROUND ( LOWER CA ) - 2 - SET TO READING STATE - 3 - HANG UP - 4 - FINISH WRITE TURNAROUND ( RAISE CA ) boot (%031374 / initialize and make ready for logon): >>ATCC csrw: Channel 2 control is ~C2 | ~C1 | ~S2 | ~S1 >>ATCC csrw: Channel 2 control is scan | update | EC2 | EC1 | C2 | C1 | ES2 | ES1 | ~S2 | ~S1 logon: nothing logoff or abortjob (%031300 / hang up): >>ATCC csrw: Channel 2 control is ~C2 | ~C1 | ~S2 | ~S1 >>ATCC csrw: Channel 2 control is scan | update | EC2 | EC1 | ~C2 | ~C1 | ~S2 | ~S1 >>ATCC csrw: Channel 2 control is ~C2 | ~C1 | ~S2 | ~S1 >>ATCC csrw: Channel 2 control is scan | update | EC2 | EC1 | C2 | C1 | ES2 | ES1 | ~S2 | ~S1 TCI notes: - counter increments at 1.25 MHz, so 12.8 usec max delay to scan a channel - INTREQ FF sets only when scan is true - hardware scans continuously - sim scans only when something might change interrupt condition: - control word written - unlike 12920A, C2/C1 latches load with EC2/EC1 only rather than loading with UPDATE * EC2/EC1 (so UPDATE controls ES2/ES1/S2/S1 ram and EC2/EC1 controls C2/C1 latches) responds to: - SIN presets INTREQ FF - CIO - RIN clears INTACT FF - RIO (same as TIO) - TIO read status - SMSK set int mask - WIO, SIO ignored IORESET same as DCONTSTB * D0 = Master Reset - sets INTMASK FF - clears INTACT FF - clears INTREQ FF - clears control_word register - clears channel counter DCONTSTB - UPDATE must be set to load ESx, Sx into the RAM (write enable) - ECx must be set to load Cx into the addressable latch (load enable) DSTATSTB: - CST_I2 = CCN_ES2 * (CCN_S2 /= CST_S2) - CST_I1 = CCN_ES1 * (CCN_S1 /= CST_S1) - CST_ES2 = CCN_ES2 - CST_ES1 = CCN_ES1 - CST_S2 = if diag then CCN_C2_alt else CD - CST_S1 = if diag then CCN_C1_alt else DSR - real S2 and S1 are kept in stat_param [] bits 1 and 0 want to inhibit a telnet line answer if local modem control and DTR off? change lnorder to add TMXR_LN_SKIP (-2) to skip a line when connecting? better if a tmxr_en/disable_line call was possible as a SET ATCD LINEORDER command would wipe out this setting for reuse with hp 1000, move all mux processing out of interface to subroutines and choose non-specific names (e.g., not mux_ or atcd_) for common variables maybe "data_" and "cntl_" for the TDI/data card and TCI/control card if "scanning" status needed, perhaps reschedule poll service when scanning set and reset scanning when service entered use a shortened time for the scanning reset (0-69 usec) Term: "channel" (not line) Term: "line" for terminal multiplexer library and serial status lines only these are the same for 12920 and 30032. The message "MPE Table TBUF has overflowed!!!" appears on the system console while doing Reflection uploads and/or downloads. Terminal buffers are mentioned on pages 207-208 of the "System Manager/3000 Student Workbook" (22802-90001 Dec-1983). The number of buffers defaults to 48 (3 per port * 16 ports) and may be changed by a SYSDUMP (answer "YES" to "SYSTEM TABLE CHANGES?"). --------------------------------------------- 30229A Disc Controller Interface (7905/20/25) --------------------------------------------- Master Reset is asserted by IORESET or DCONTSTB * IOD0: - sets INTMASK FF - resets INTREQ FF - resets INTACT FF - resets XFERERR FF - resets INXFER FF - resets OUTXFER FF - resets SIOBUSY FF - resets XFACESEL FF - resets data overrun FF - resets end of data FF - resets TEST MODE FF - resets XFRNG latch - clears bits 3-15 of the status register - asserts CLEAR to controller if enabled by jumper W1 SIO Busy denying: - sets the EOD flag - sets the INTOK flag - clears the CMRDY flag - clears the DTRDY flag - clears the service request flip-flip - clears the JMPMET flip-flip - clears the WAIT flip-flip - clears the retry counter CLRIL pulses if XFER ERR FF, STINT from controller, or a borrow by the retry counter: - sets the EOD flag - clears the INXFER FF - clears the OUTXFER FF - clears the SIOBUSY FF - asserts REQ to the channel Interrupt Request - set by DSETINT, SETINT, STINT from controller, or a borrow by the retry counter XFER ERR FF - reset by master reset, STINT from controller or a borrow by the retry counter Test Mode FF - inhibits the CMRDY, DTRDY, XFRNG, INTOK, OVRUN, and EOD flags to the controller - presets device SR to assert CHANSR continuously - reported as DIO_OK (status bit 1), so prevents RIO, WIO unless set SIN sets the interrupt_request FF CIO enables D0 -> master reset enables D1 -> clears the interrupt request FF enables D2 -> sets the test mode FF SIO enables device number * 4 to SRn presets the SIO busy FF asserts REQ to SEL WIO stores inbound data into data buffer register RIN resets the interrupt active FF TIO enables the status register to the outbound data SMSK sets the interrupt_mask FF from the inbound value RIO reads the data buffer register to the outbound data SETJMP clears the JMPMET FF after returning the value (set by DVEND from controller) SETINT sets the interrupt request FF TOGGLESIOOK toggles the SIO busy FF PCMD1 sets SR clocks data bit 15 into the wait FF PCONTSTB resets SR stores inbound data into data buffer register sets the command ready FF PSTATSTB enables the status register to the outbound data PWRITESTB resets SR stores inbound data into data buffer register sets the data ready FF PREADSTB enables the data buffer register to the outbound data clears the data ready FF PFWARN presets XFERERR FF XFERERROR sets XFERERR FF EOT presets EOD FF flags (all flags except CLEAR are inactive if test_mode flip-flop is set): CLEAR = master_reset * W1-enable CMRDY data = 1 clock = PCONTSTB reset = ~sio_busy + IFGTC DTRDY data = ~DTRDY (toggle) clock = IFIN + IFOUT + PREADSTB + PWRITESTB reset = ~sio_busy + IFGTC action is to set on IFOUT and clear on PREADSTB or set on PWRITESTB and clear on IFIN eod_1 data = 1 clock = 1 preset = EOT * CHANACK reset = master_reset + RQSRV + IFGTC eod_2 data = eod_1 clock = ~EOT * (TOGGLEINXFER + TOGGLEOUTXFER) preset = CLRIL reset = master_reset + RQSRV + IFGTC EOD data = eod_2 clock = ~DTRDY preset = sio_busy reset = RQSRV + IFGTC action: - PREADSTB | EOT or PWRITESTB | EOT sets eod_1 only (intermediate chained read/write) - PREADSTB | TOGGLEINXFER | EOT or PWRITESTB | TOGGLEOUTXFER | EOT sets eod_1 and then eod_2 (final chained write) - DTRDY denies sets EOD (interface gets word with PREADSTB or controller gets word with IFIN) INTOK = ~sio_busy OVRUN = data_overrun * ~XFRNG data_overrun data = OUTXFER * ~DTRDY + INXFER * DTRDY + OVRUN (to keep it set) clock = IFCLK * (IFIN + IFOUT) * IFSEL reset = master_reset + RQSRV + IFGTC XFRNG = transfer_error_latch transfer_error_latch set = XFERERROR + IFOUT * ~EOD * (OUTXFER + ~INXFER) + IFIN * ~EOD * (INXFER + ~OUTXFER) reset = master_reset + INTRQ + retry_borrow device_sr_1 data = 1 clock = PCMD1 + OUTXFER preset = test_mode reset = PCONTSTB + PWRITESTB + ~sio_busy device_sr_2 data = 1 clock = RQSRV + IFGTC + IFOUT * ~EOD + IFIN * ~EOD preset = device_sr_1 reset = CHANSO * ~DEVEND + ~sio_busy ----------------------------------------- 30033A Selector Channel Maintenance Board ----------------------------------------- I/O INSTRUCTIONS. The following is a list of applicable I/O instructions and their effect upon the SCMB. a. SIN Instruction - Sets the SCMB interrupt request flip-flop. b. CIO Instruction - Loads a control word from the TOS into the SCMB control register. c. SIO Instruction - Initiates I/O program execution if the channel is inactive. The SIO instruction is rejected if the channel is currently active. d. WIO Instruction - Loads a data word from the TOS into the counter/buffer. e. RIO Instruction - Sends the contents of the counter/buffer to the TOS. f. TIO Instruction - Returns the SCMB status word to the TOS. g. SMSK Instruction - This instruction is ignored because the SCMB has no mask flip-flop. I/O PROGRAM ORDERS. The following is a list of applicable I/O program orders and their effect on the SCMB. a. Control - Selects operational states/test modes of the SCMB. b. Write - If control word bits 11 and 13 are "0", loads a data word from memory into the counter/buffer. If bit 11 is a "1", compares the data word from memory to the counter/buffer contents. Bit 11 = 0 means "do not terminate on miscompare", and bit 13 = 0 means that no counting is done (counts 0-3 are "count nothing" and three "count reads"). c. Read - Sends the contents of the counter/buffer to memory. d. End - Returns the SCMB status word to the End order IOAW location and terminates I/O program execution. If bit 4 is "1", an interrupt occurs. e. Interrupt - Sets the SCMB interrupt request flip-flop. f. Sense - Returns the SCMB status word to the Sense order I0AW location in memory. g. Jump - If bit 4 of the order is "1" and bit 2 of the current I0CW is "1", or if bit 4 of the order is "0", an I/O program jump occurs. h. Return Residue - If bit 4 of the I0CW is "0", causes the residue of the count to be returned to the I0AW. i. Set Bank - If bit 4 of the I0CW is "1", loads the bank register for that device with I0AW bits 14 and 15. CONTROL WORD. The control word is used to select the various operational states and test modes of the SCMB. A control word can be issued to the SCMB through a direct Control I/O instruction or through an I/O program Control order. If a Control order is used, the control word is located in the Control order I0AW location (the Control order I0CW is ignored by the SCMB). The control word is stored in the SCMB control register. CN_NOACK : inhibits CHANACK return from interface; channel detects this as timeout (inh on NEXT interface call, i.e., not the CIO that sets this bit) CN_NOSR : clears CHANSR return from interface; channel service entry is timeout (inh on NEXT interface call, i.e., not the CIO that sets this bit) => actually, MUST inhibit CHANSR immediately, or diag says NO SR TIMEOUT (diag checks IOPC returned on channel abort) CN_HSREQ : sets device_sr immediately; not set = schedule service entry to set device_sr (service time is 2 instr = 5 usec) Interrupt Request FF: - preset by CLRIL or SETINT or SIN instruction - reset by RST2 or PRSTINT or Interrupt Latch output set pulse - set by XFERERROR Interrupt Latch: - latched while INTPOLL IN is asserted - transparent while INTPOLL IN is denied - input value is (Mask FF *) Interrupt Request FF set * Interrupt Active FF clear - purpose is to provide a stable set of interrupt requests while the poll is active (prevents case where higher priority request usurps the poll just after a lower priority controller has set its Active FF) Interrupt Active FF: - preset by INTPOLL IN * Interrupt Latch - reset by RST3 or RIN - not clocked - purpose is to hold off lower priority controllers (inhibits INTPOLL OUT and Latch set, which disables device number to DEVNO bus, so IOP ignores interrupt request) Signals: - INTREQ is Interrupt Request set - INTPOLLOUT is INTPOLLIN * ~INTLATCH * ~INTACTFF - INTACK is INTPOLLIN * INTACTFF * ~SETINT Interrupt Request Process: - initial state is Interrupt Mask FF set, Latch clear, Active FF clear Channel SR FF: - toggled by TOGGLESR - BLS = CHANSO * sr_latch * ? - BLSE2 = MPX * BLS * SO + ~MPX * chan_enb Device SR FF: - cleared on the rising edge of BLSE2 - preset on input_xfer + output_xfer + PCMD1 + PCONTSTB. So it's cleared at the start of each cycle and preset as indicated. ------------------------------------------ 32341A HP-IB Interface Module ("Starfish") ------------------------------------------ Consists of: - 30030-60020 Port Controller (installed in Series III) - 30340-60001 Backplane (6 position) - 30340-60002 IMBA (intermodule bus adapter) (connects to IOP bus and to port controller) - 30070-60012 Processor - 31000-60053 BIC (bus interface controller) - 31262-60001 GIC (general I/O channel) [reference: CE handbook pages 111, 237-244 of 30000-90172 July 1981] The schematic for the Port Controller is in the "HP 3000 Series III Engineering Diagrams Set" (30000-90141 Apr-1980) pages 119-121. The IMBA and GIC are in the "HP 3000 Series 39/40/42/44/48 Computer Systems Engineering Diagrams Set" (30090-90034 Oct-1984) pages 66-70 and 71-76. The Processor and BIC are in the "HP 3000 Series 33 Engineering Diagrams Set" (30070-90009 Jan-1979) pages 95-97 and 106-108. Supports: - 7976 magnetic tape drive - 2680 page printer - 7933 disc drive - ? 12745A MAC to HP-IB Adapter - ? 7902 or 9895 floppy :LISTF @.HP32341.SUPPORT,2 ACCOUNT= SUPPORT GROUP= HP32341 FILENAME CODE ------------LOGICAL RECORD----------- ----SPACE---- SIZE TYP EOF LIMIT R/B SECTORS #X MX ADDDUS PROG 128W FB 48 48 1 49 1 1 MTCOPY PROG 128W FB 91 91 1 92 1 1 PD450A PROG 128W FB 265 265 1 266 1 1 PD451A PROG 128W FB 244 244 1 245 1 1 TAPEDUS 4096W FB 114 513 1 4160 2 8 UD450A USL 128W FB 445 1000 1 504 4 8 UD450A0 USL 128W FB 143 1000 1 252 2 8 UD450A1 USL 128W FB 138 1000 1 252 2 8 UD450A2 USL 128W FB 213 1000 1 252 2 8 UD450A3 USL 128W FB 67 400 1 201 1 2 UD450A4 USL 128W FB 156 1000 1 252 2 8 UD450A5 USL 128W FB 296 1000 1 378 3 8 UD451A USL 128W FB 391 1000 1 504 4 8 UD451A0 USL 128W FB 133 1000 1 252 2 8 UD451A1 USL 128W FB 267 1000 1 378 3 8 :LISTF @.HP32340.SUPPORT,2 ACCOUNT= SUPPORT GROUP= HP32340 FILENAME CODE ------------LOGICAL RECORD----------- ----SPACE---- SIZE TYP EOF LIMIT R/B SECTORS #X MX BASMON 80B FA 40 40 16 20 1 1 BCNTFX 80B FA 15 15 16 10 1 1 BUFSUB 80B FA 17 17 16 15 1 1 CKSTAT 80B FA 15 15 16 10 1 1 CMPSUB 80B FA 15 15 16 10 1 1 CNFG 80B FA 20 20 16 15 1 1 CNVR 80B FA 28 28 16 15 1 1 D467ENV 512W FB 72 1023 1 512 1 8 D467P1 1024W VB 38 1023 1 1152 1 8 D467P2 1024W VB 38 1023 1 1152 1 8 D88ENV 512W FB 53 1023 1 512 1 8 DIAPAT 80B FA 20 20 16 15 1 1 DMSSUB 80B FA 15 15 16 10 1 1 DSTATR 80B FA 14 14 16 10 1 1 EOISUB 80B FA 15 15 16 10 1 1 EROR2 80B FA 29 29 16 15 1 1 EROR3 80B FA 28 28 16 15 1 1 ERRTAB 80B FA 47 47 16 20 1 1 EXCUTE 80B FA 29 29 16 15 1 1 FLIP 80B FA 14 14 16 10 1 1 G00G340A 80B FA 233 233 16 80 1 1 INIT 80B FA 15 15 16 10 1 1 INTABL 80B FA 43 43 16 20 1 1 INTRP 80B FA 43 43 16 20 1 1 INTRSB 80B FA 38 38 16 20 1 1 JD466A 72B FA 11 11 16 10 1 1 JD467A 80B FA 11 11 3 5 1 1 JD467ENV 80B FA 11 11 3 5 1 1 JD470A 80B FA 11 11 16 10 1 1 MD466A 80B FA 1639 1639 16 520 15 15 MD467A 80B FA 601 601 16 195 13 13 MD470A 80B FA 65 65 16 30 1 1 MONITR 80B FA 34 34 16 20 1 1 MONLIST 72B FA 40 40 7 14 1 1 MTDCAT 80B FA 736 736 16 235 1 1 N00N340A 88B FA 81 81 29 40 1 1 ND466A 80B FA 98 98 3 34 1 1 ND467A 80B FA 39 39 16 20 1 1 NEWCATJC 80B FA 282 282 16 95 10 10 NEWENV PENV 512W FB 144 4092 1 1024 1 16 NEWFORMS PFORM 256B FA 989 1000 1 1001 8 8 OPCDE0 80B FA 25 25 16 15 1 1 OPCDE1 80B FA 28 28 16 15 1 1 OPCDE2 80B FA 23 23 16 15 1 1 OPCDE3 80B FA 28 28 16 15 1 1 OPCDE4 80B FA 36 36 16 20 1 1 OPCDE5 80B FA 16 16 16 10 1 1 OPCDE7 80B FA 22 22 16 15 1 1 PD466A PROG 128W FB 62 62 1 63 1 1 PD467A PROG 128W FB 134 134 1 135 1 1 PD467ENV PROG 128W FB 10 10 1 11 1 1 PD470A PROG 128W FB 106 106 1 107 1 1 PD471A PROG 128W FB 461 461 1 462 1 1 PHDR 80B FA 21 21 16 15 1 1 PRCMBF 80B FA 28 28 16 15 1 1 PRNT 80B FA 34 34 16 20 1 1 PURGEFLE 80B FA 46 46 16 20 1 1 RDREG 80B FA 15 15 16 10 1 1 RDSUB 80B FA 14 14 16 10 1 1 REGFIX 80B FA 17 17 16 15 1 1 REGTBL 80B FA 29 29 16 15 1 1 RGT 80B FA 25 25 16 15 1 1 RT020100 256W FB 4 4 1 10 5 5 RT020200 256W FB 4 4 1 10 5 5 RT020300 256W FB 4 4 1 10 5 5 RT020400 256W FB 4 4 1 10 5 5 RT020500 256W FB 4 4 1 10 5 5 RT020600 256W FB 4 4 1 10 5 5 RT021001 256W FB 4 4 1 10 5 5 RT021101 256W FB 4 4 1 10 5 5 RT021201 256W FB 4 4 1 10 5 5 RT022001 256W FB 4 4 1 10 5 5 RT023001 256W FB 4 4 1 10 5 5 RT024001 256W FB 4 4 1 10 5 5 RT024400 256W FB 4 4 1 10 5 5 RT024500 256W FB 4 4 1 10 5 5 RT027000 256W FB 4 4 1 10 5 5 RT027100 256W FB 4 4 1 10 5 5 RT030200 256W FB 8 10 1 20 5 6 RT030600 256W FB 4 4 1 10 5 5 RT031000 256W FB 4 4 1 10 5 5 RT031100 256W FB 4 4 1 10 5 5 RT031200 256W FB 4 4 1 10 5 5 RT032000 256W FB 4 4 1 10 5 5 RT033000 256W FB 4 4 1 10 5 5 RT034000 256W FB 4 4 1 10 5 5 RT041000 256W FB 4 4 1 10 5 5 RT042000 256W FB 4 4 1 10 5 5 RT043000 256W FB 4 4 1 10 5 5 RT043100 256W FB 4 4 1 10 5 5 RT043200 256W FB 4 4 1 10 5 5 RT043300 256W FB 4 4 1 10 5 5 RT044000 256W FB 4 4 1 10 5 5 RT044100 256W FB 8 10 1 20 5 6 RT051000 256W FB 4 4 1 10 5 5 RT051100 256W FB 4 4 1 10 5 5 RT052000 256W FB 4 4 1 10 5 5 RT052100 256W FB 4 4 1 10 5 5 RT055000 256W FB 4 4 1 10 5 5 RT056000 256W FB 4 4 1 10 5 5 RT057000 256W FB 4 4 1 10 5 5 RT057100 256W FB 4 4 1 10 5 5 RT100301 256W FB 4 4 1 10 5 5 RT100401 256W FB 4 4 1 10 5 5 RT110503 256W FB 4 4 1 10 5 5 RT110603 256W FB 4 4 1 10 5 5 RT111002 256W FB 4 4 1 10 5 5 RT111103 256W FB 4 4 1 10 5 5 RT111203 256W FB 4 4 1 10 5 5 RT111300 256W FB 4 4 1 10 5 5 RT112002 256W FB 4 4 1 10 5 5 RT112102 256W FB 4 4 1 10 5 5 RT112202 256W FB 4 4 1 10 5 5 RT112302 256W FB 4 4 1 10 5 5 RT112402 256W FB 4 4 1 10 5 5 RT112502 256W FB 4 4 1 10 5 5 RT112602 256W FB 4 4 1 10 5 5 RT112702 256W FB 4 4 1 10 5 5 RT113002 256W FB 4 4 1 10 5 5 RT114302 256W FB 4 4 1 10 5 5 RT116000 256W FB 4 4 1 10 5 5 RT124101 256W FB 4 4 1 10 5 5 RT124200 256W FB 4 4 1 10 5 5 RT124300 256W FB 4 4 1 10 5 5 RT126101 256W FB 4 4 1 10 5 5 RT126200 256W FB 4 4 1 10 5 5 RT126300 256W FB 4 4 1 10 5 5 RT130100 256W FB 4 4 1 10 5 5 RT130200 256W FB 4 4 1 10 5 5 RT131000 256W FB 4 4 1 10 5 5 RT131100 256W FB 4 4 1 10 5 5 RT131200 256W FB 4 4 1 10 5 5 RT131300 256W FB 4 4 1 10 5 5 RT132000 256W FB 4 4 1 10 5 5 RT132100 256W FB 4 4 1 10 5 5 RT132200 256W FB 4 4 1 10 5 5 RT132300 256W FB 4 4 1 10 5 5 RT140101 256W FB 4 4 1 10 5 5 RT140200 256W FB 4 4 1 10 5 5 RT140300 256W FB 4 4 1 10 5 5 RT144101 256W FB 4 4 1 10 5 5 RT144200 256W FB 4 4 1 10 5 5 RT144300 256W FB 4 4 1 10 5 5 RT157777 256W FB 1 1 1 4 2 2 RT166000 256W FB 4 4 1 10 5 5 RT166001 256W FB 4 4 1 10 5 5 RT166002 256W FB 4 4 1 10 5 5 RT166100 256W FB 4 4 1 10 5 5 RT166101 256W FB 4 4 1 10 5 5 RT166102 256W FB 4 4 1 10 5 5 RUNCMD 80B FA 42 42 16 20 1 1 SETSNS 80B FA 23 23 16 15 1 1 SETSTA 80B FA 14 14 16 10 1 1 STDVFC 72B FA 1 1 3 2 1 1 VFCTEST 72B FA 67 67 7 22 1 1 WRTSUB 80B FA 14 14 16 10 1 1 XEQ 80B FA 24 24 3 9 1 1 XEQCE 80B FA 125 125 3 43 1 1 :FCOPY FROM=G00G340A.HP32340.SUPPORT;TO= DESCRIPTION OF HP3000 ONLINE DIAGNOSTICS AND MISCELLANEOUS FILES SECTION 1 - DESCRIPTION ----------------------- BASMON - PART OF 7976 DOWNLOADED MONITOR PROGRAM (PD470A) BCNTFX - " " " " " " " BUFSUB - " " " " " " " CKSTAT - " " " " " " " CMPSUB - " " " " " " " CNFG - " " " " " " " CNVR - " " " " " " " D467ENV - ENVIRONMENT FILES FOR THE PRINTER VERIFIER (PD467A) D467P1 - PICTURE FILE FOR THE PRINTER VERIFIER (PD467A) D467P2 - PICTURE FILE FOR THE PRINTER VERIFIER (PD467A) D88ENV - ENVIRONMENT FILES FOR HP2688A (PD467A) DIAPAT - PART OF 7976 DOWNLOADED MONITOR PROGRAM (PD470A) DMSSUB - " " " " " " " DSTATR - " " " " " " " EOISUB - " " " " " " " EROR2 - " " " " " " " EROR3 - " " " " " " " ERRTAB - " " " " " " " EXCUTE - " " " " " " " FLIP - " " " " " " " G00G340A - GUIDE FILE. CONTAINS INFORMATION PERTAINING TO GROUP. INIT - PART OF 7976 DOWNLOADED MONITOR PROGRAM (PD470) INTABL - " " " " " " " INTRP - " " " " " " " INTRSB - " " " " " " " JD466A - JOB FILE FOR THE LINE PRINTER VERIFIER (PD466A) JD467A - JOB FILE FOR THE PAGE PRINTER VERIFIER (PD467A) JD467ENV - JOB FILE FOR ENVIRONMENT CONVERSION PROGRAM FOR D467ENV JD470A - JOB FILE FOR THE 7976 MAGNETIC TAPE DIAGNOSTIC (PD470A) JD471A - JOB FILE FOR THE 79974/78 MAGNETIC TAPE DIAGNOSTIC (PD471A) MD466A - MAINTENANCE FILE FOR THE PRINTER VERIFIER (PD466A) MD467A - MAINTENANCE FILE FOR THE PAGE PRINTER VERIFIER (PD467A) MD470A - MAINTENANCE FILE FOR TH 7976 MAG TAPE DIAGNOSTIC (PD470A) MD471A - MAINTENANCE FILE FOR TH 7974/78 MAG TAPE DIAGNOSTIC (PD471A) MONITR - PART OF 7976 DOWNLOADED MONITOR PROGRAM (PD470A) MTDCAT - CATALOG FILE FOR 7974/78 MAG TAPE DIAGNOSTIC (PD471A) MONLIST - " " " " " " " ND466A - NOTE FILE FOR THE LINE PRINTER VERIFIER (PD466A) ND467A - NOTE FILE FOR THE PAGE PRINTER VERIFIER (PD467A) NEWCATJC - MESSAGES FOR MESSAGE SET 22 IN THE SYSTEM CATALOG NEWENV - ORIGINAL ENVIRONMENT FILE (BEFORE CONV) FOR PD467A NEWENV88 - ENVIRONMENT FILE OF HP2688 FOR PD467A NEWFORMS - FORMS FILE FOR THE ENVIRONMENT FILE "NEWENV" N00N340A - NOTE FILE FOR THIS GROUP. DOCUMENTS CHANGES BEING MADE. OPCDE0 - PART OF 7976 DOWNLOADED MONITOR PROGRAM (PD470A) OPCDE1 - " " " " " " " OPCDE2 - " " " " " " " OPCDE3 - " " " " " " " OPCDE4 - " " " " " " " OPCDE5 - " " " " " " " OPCDE7 - " " " " " " " PD466A - PROGRAM FILE FOR THE LINE PRINTER VERIFIER PD467A - PROGRAM FILE FOR THE PAGE PRINTER VERIFIER PD467ENV - PROGRAM FILE FOR ENVIRONMENT FILE CONVERSION. PD470A - PROGRAM FILE FOR THE 7976 MAG TAPE DIAGNOSTIC PD470A - PROGRAM FILE FOR THE 7974 MAG TAPE DIAGNOSTIC PHDR - PART OF 7976 DOWNLOADED MONITOR PROGRAM (PD470A) PRCMBF - " " " " " " " PRNT - " " " " " " " PURGEFLE - STREAM JOB TO CREATE THE INSTALLATION TAPE FROM THE MMT RDREG - PART OF 7976 DOWNLOADED MONITOR PROGRAM (PD470A) RDSUB - " " " " " " " REGFIX - " " " " " " " REGTBL - " " " " " " " RGT - " " " " " " " RT020100 - AMP SENSOR PICK AND DROP ROUTINE (PD470A) [5 SECS] RT020200 - AMP SENSOR DECODE ROUTINE (PD470A) [2 MIN 20 SECS] RT020300 - PE WRITE ONES ROUTINE (PD470A) [4 SECS] RT020400 - PE WRITE ZEROS ROUTINE (PD470A) [4 SECS] RT020500 - PE WRITE ZEROS-P TRACK ROUTINE (PD470A) [4 SECS] RT020600 - GCR WRITE ONES LWR ROUTINE (PD470A) [4 SECS] RT021001 - PE READ 20% PHASE ERROR ROUTINE (PD470A) [13 SECS] RT021101 - PE WRITE 20% EARLY ERROR ROUTINE (PD470A) [7 SECS] RT021201 - PE WRITE 20% LATE ERROR ROUTINE (PD470A) [7 SECS] RT022001 - PE READ 30% PHASE ERROR ROUTINE (PD470A) [15 SECS] RT023001 - PE WRITE 35% PHASE ERROR ROUTINE (PD470A) [15 SECS] RT024001 - PE WRITE 40% PHASE ERROR ROUTINE (PD470A) [15 SECS] RT024400 - PE READ 40% ERR BIT FLIP(+) ROUTINE (PD470A) [7 SECS] RT024500 - PE READ 40% ERR BIT FLIP(-) ROUTINE (PD470A) [8 SECS] RT027000 - GCR 50% LATE ERROR FLIP ROUTINE (PD470A) [2 SECS] RT027100 - GCR 25% ERROR FLIP ROUTINE (PD470A) [2 SECS] RT030200 - PE LWR BYTE COUNTS 1-2048 ROUTINE (PD470A) [38 SECS] RT030600 - PE READ ONES BACKWARDS ROUTINE (PD470A) [2 SECS] RT031000 - PE LWR SINGLE DEAD TRACK ROUTINE (PD470A) [2 SECS] RT031100 - PE READ FORWARD SINGLE DEAD TRACK ROUTINE (PD470A) [2 SECS] RT031200 - PE READ BACKWARD SINGLE DEAD TRK ROUTINE (PD470A) [2 SECS] RT032000 - PE READ FORWARD MULTI TRACK ERROR ROUTINE (PD470A) [5 SECS] RT033000 - PE RDF BAD PARITY NO POINTER ROUTINE (PD470A) [1 SEC] RT034000 - PE LWR-ONE POINTER-NO CORRECTION RTN (PD470A) [1 SEC] RT041000 - GCR RDF 0-F TRANSLATIONS ROUTINE (PD470A) [9 SECS] RT042000 - GCR RDB 0-F TRANSLATIONS ROUTINE (PD470A) [8 SECS] RT043000 - GCR RDF - 7 BYTE RECORDS ROUTINE (PD470A) [1 SEC] RT043100 - GCR RDB - 7 BYTE RECORDS ROUTINE (PD470A) [1 SEC] RT043200 - GCR RDF - 6 BYTE RECORDS ROUTINE (PD470A) [1 SEC] RT043300 - GCR RDB - 6 BYTE RECORDS ROUTINE (PD470A) [1 SEC] RT044000 - GCR WRITE PATH 7 BYTE RECORD ROUTINE (PD470A) [1 SEC] RT044100 - GCR LWR BYTE COUNTE 1-2048 ROUTINE (PD470A) [16 SECS] RT051000 - RDF 1 TRACK CORRECTIONS ROUTINE (PD470A) [5 SECS] RT051100 - RDF 1 TRACK CORRECTIONS ROUTINE (PD470A) [4 SECS] RT052000 - RDB 1 TRACK CORRECTIONS ROUTINE (PD470A) [4 SECS] RT052100 - RDB 1 TRACK CORRECTIONS ROUTINE (PD470A) [E SECS] RT055000 - RDF - ILLEGAL TRANSLATIONS ROUTINE (PD470A) [9 SECS] RT056000 - RDB - ILLEGAL TRANSLATIONS ROUTINE (PD470A) [9 SECS] RT057000 - RDF - 2 TRACK CORRECTIONS ROUTINE (PD470A) [18 SECS] RT057100 - RDB - 2 TRACK CORRECTIONS ROUTINE (PD470A) [22 SECS] RT100301 - CTL CABLE, DRV STAT: TACK RDY ROUTINE (PD470A) [4 SECS] RT100401 - READ CABLE - AMP SENSOR TEST ROUTINE (PD470A) [23 SECS] RT110503 - PE WRT STAT,INH,DIS,FEEDTHRU ROUTINE (PD470A) [2.33 MINS] RT110603 - GCR WRT STATUS,INH,DIS,FEEDTHRU ROUTINE (PD470A) [55 SECS] RT111002 - TACK SYMMETRY ROUTINE (PD470A) [5 SECS] RT111103 - TACH PERIOD ROUTINE (PD470A) [20 SECS] RT111203 - ACCELERATION RAMP & VELOCITY ERR ROUTINE (PD470A) [5 SECS] RT111300 - COLUMN TEST ROUTINE (PD470A) [15 SECS] RT112002 - PE GAP PLOT ROUTINE (PD470A) [36 SECS] RT112102 - PE STOP AND CREEP ROUTINE (PD470A) [53 SECS] RT112202 - PE FWD AND BKWD ACCESS TIME ROUTINE (PD470A) [2.28 MINS] RT112302 - GCR GAP PLOT ROUTINE (PD470A) [22 SECS] RT112402 - GCR STOP AND CREEP DISTANCE ROUTINE (PD470A) [32 SECS] RT112502 - GCR FWD & BKWD ACCESS TIME ROUTINE (PD470A) [1 MIN 41 SECS] RT112602 - PE CREASE BIT POSITIONING ROUTINE (PD470A) [5 SECS] RT112702 - GCR CREASE BIT POSITIONING ROUTINE (PD470A) [5 SECS] RT113002 - ERASE GAP DISTANCE ROUTINE (PD470A) [25 SECS] RT114302 - PE AND GCR MOTION TEST ROUTINE (PD470A) [10 SECS] RT116000 - POSITIONING TEST ROUTINE (PD470A) [1 MIN 25 SECS] RT124101 - PE WRITE BYTE CNTS 1-2048 ROUTINE (PD470A) [1 MIN 15 SECS] RT124200 - PE READ FWD BYTE CNTS 1-2048 ROUTINE (PD470A) [2.41 MINS] RT124300 - PE READ BKWD BYTE CNTS 1-2048 ROUTINE (PD470A) [3.2 MINS] RT126101 - GCR WRT BYTE COUNTS 1-2048 ROUTINE (PD470A) [50 SECS] RT126200 - GCR READ FWD BYTE CNTS1-2048 ROUTINE (PD470A) [2.15 MINS] RT126300 - GCR READ BKWD BYTE CNTS 1-2048 ROUTINE (PD470A) [3.22 MINS] RT130100 - GCR WRITE SINGLE TRK CORRECTION ROUTINE (PD470A) [6 SECS] RT130200 - GCR RD FWD SINGLE TRK CORRECTION ROUNTING )PD470A) [5 SECS] RT131000 - PE COMPLEX BLOCK SPACING ROUTINE (PD470A) [23 SECS] RT131100 - PE COMPLEX WRITE ROUTINE (PD470A) [23 SECS] RT131200 - PE COMPLEX WRITE VERIFIER ROUTINE (PD470A) [28 SECS] RT131300 - PE COMPLEX POSITIONING ROUTINE (PD470A) [37 SECS] RT132000 - GCR COMPLEX BLOCK SPACING ROUTINE (PD470A) [16 SECS] RT132100 - GCR COMPLEX WRITE ROUTINE (PD470A) [15 SECS] RT132200 - GCR COMPLEX WRITE VERIFIER ROUTINE (PD470A) [7 SECS] RT132300 - GCR COMPLEX POSITIONING ROUTINE (PD470A) [8 SECS] RT140101 - PE WRITE RELIABILITY ROUTINE (PD470A) [2 MIN 40 SECS] RT140200 - PE READ FWD RELIABILITY ROUTINE (PD470A) [4 MIN 3 SECS] RT140300 - PE READ BKWD RELIABILITY ROUTINE (PD470A) [4 MINS] RT144101 - GCR WRT RELIABILITY ROUTINE (PD470A) RT144200 - GCR READ FWD RELIABILITY ROUTINE (PD470A) RT144300 - GCR READ BKWD RELIABILITY ROUTINE (PD470A) RT166000 - PE WRT RANDOM DATA ROUTINE (PD470A) RT166001 - PE READ FWD RANDOM DATA ROUTINE (PD470A) RT166002 - PE READ BKWD RANDOM DATA ROUTINE (PD470A) RT166100 - GCR WRITE RANDOM DATA ROUTINE (PD470A) RT166101 - GCR READ FWD RANDOM DATA ROUTINE (PD470A) RT166102 - GCR READ BKWD RANDOM DATA ROUTINE (PD470A) RUNCMD - PART OF 7976 DOWNLOADED MONITOR PROGRAM (PD470A) SD466A - SOURCE FILE FOR THE LINE PRINTER VERIFIER SD467A - SOURCE FILE FOR THE 2680 PAGE PRINTER VERIFIER SD467ENV - SOURCE FILE FOR THE ENVIRONMENT FILE CONVERSION PROGRAM SD470A - SOURCE FILE FOR THE 7976 MAG TAPE DIAGNOSTIC SD471A - SOURCE FILE FOR THE 7974 MAG TAPE DIAGNOSTIC SETSNS - PART OF 7976 DOWNLOADED MONITOR PROGRAM (PD470A) SETSTA - " " " " " " " STDVFC - STANDARD VFC FILE FOR TESTING 2608 PRINTER (PD466A) VFCTEST - TEST VFC FILE FOR TESTING 2608 PRINTER (PD466A) WRTSUB - PART OF 7976 DOWNLOADED MONITOR PROGRAM (PD470A) XEQ - PD470A DIAGNOSTIC EXECUTION FILE (SHORT TEST - 11 MIN) XEQCE - PD470A DIAGNOSTIC EXECUTION FILE (COMPLETE TEST > 1HR) SECTION II - MIT SUBMITTAL PROCEDURE Four tapes are produced: A) First tape contains all files in the group and is kept by the development team. A complete list of all the files as well as a copy of the MIT submittal form should also be maintained by the development team for a minimum of 18 months. :file t;dev=tape :store @;*t {Make a master tape of the group} :file lp;dev=lp :listf @,2;*lp {Make a list of the files} B) Second is made if any sources change and goes to production engineering. :store sd@;*t C) Third tape contains the files which are not sources and goes to the person who builds the MIT. :File syslist;dev=lp (obtain a list of files for submittal) :store B@,C@,D@,E@,F@,G@,I@,J@,M@,N@,O@,P@,R@,SE@,ST@,V@,W@,X@;& *T;SHOW D) Fourth tape contains the note file (N00N340A) and it goes to the SRB coordinator. Note: If a change is made long after the initial MIT freeze date, the FIELD.SUPPORT,HP32340 files may have been changed for the next MIT cycle. The best way to make the change is the following: 1) Store the entire group on tape (see a above). 2) Restore the tape made in step A for the last freeze date. 3) Make the necessary changes. 4) Change the N00N340A file to reflect the changes. 5) Follow the MIT submittal procedure above (A-C). 6) Restore the tape made in step 1. SECTION III - MISCELLANEOUS Any new files added to this group must be described in this document. A review needs to be done to insure that MIT submittal procedure IIC does not require modification. A check should also be made to the file "PURGEFLE". This file contains a list of the files that will be purged from the master maintenance tape (MMT) to produce the field installation tape. The MMT is what is produced from section IIC. Files that should be included in "PURGEFLE" are: a) Maintenance files (MD____). b) Job files (JD____). c) Note files (ND____). d) Miscellaneous files, such as NEWCATJC, that are not required during diagnostic program execution. ------------------------------ HP-IB Systems I/O Description ------------------------------ The "HP 3000 Series 44 and HP 3000 Series 40 Computer Systems Reference/Training Manual (30090-90001) describes the I/O system in Section 7. The CPVA format is mentioned briefly on page 7-10. The channel program instruction set is described on page 7-15. The GIC description starts on page 7-21, and the register description starts on page 7-29. =================== Series 6x Microcode =================== Notes: - Each ALU may independently skip the execution of its half of the following line of microcode by use of its skip field. This technique keeps both of the ALUs busy executing useful code as much of the time as possible, since it is necessary to skip the effect of only half the line of microcode rather than the entire line. - Either ALU may specify transfer of control to another point in the microcode by a conditional or unconditional jump instruction. If neither of the jump conditions is met, execution continues in sequence. If only one of the conditions is met, execution transfers to the location specified by that ALU. But, if both conditions are met, then one of the ALUs has priority over the other. Data-dependent jumps (such as those based on the results of the ALU operations) are executed from Rank 3. Non-data-dependent jumps (such as those based on flags), and unconditional jumps preceded by data-dependent skips, are executed from Rank 2. Unconditional jumps are executed from Rank 1. Jumps executing from Rank 3 override those from Rank 2 or 1. Jumps from Rank 2 override those from Rank 1. Jumps from any Rank in ALUB override those from the same Rank in ALUA. JSBs in either ALU have priority over RSBs. - JSB results in the transfer of microcode execution to the subroutine target address. When a JSB is executed, the target address from either Rank 1, 2, or 3 is placed on the VBUS, depending on the speed of the JSB (fast, medium, or slow, respectively), and the address of the following line of microcode is placed at the top of the Return Address Register (RAR). The RAR is not automatically incremented or decremented for JSBs and RSBs. Incrementing is done in microcode, using Special Field options Push Register (PSHR) and Pop Register (POPR). ======== Starfish ======== DUS-III starts up with the following calls: - 00.030467 030240 TIO 0 to get status -- expects %160000 - 00.030524 030161 SIO 1 to execute SLFT (Initiate self-test) 00.000770: 000007 SLFT 00.000771: 000006 (this is copied from absolute location 1) 00.000772: 177777 (self test result) 00.000773: 000000 00.000774: 000000 (status; cleared before SIO) 00.000775: 100402 00.000776: 000000 00.000777: 000000 Location 771 is copied from location 1, which is set ~100 instructions after starting. Location 1 is set by a DRT scan and appears to be the DRT number of the LP. Location 774 bit 0 = 1 is "mailbox not busy." So program clears 774 (meaning: mailbox is now busy) and loops until 774 bit 0 = 1. - 00.017322 030161 SIO 1 to execute IOCL (I/O Clear) 00.000770: 000005 IOCL 00.000771: 000006 00.000772: 000000 00.000773: 000000 00.000774: 000000 00.000775: 100402 00.000776: 000000 00.000777: 000000 - 00.017322 030161 SIO 1 to execute SED2 (Enable CPP interrupts, called twice) 00.000770: 000004 SED2 00.000771: 000001 enable 00.000772: 177777 00.000773: 000000 00.000774: 000000 00.000775: 100402 00.000776: 000000 00.000777: 000000 - 00.017322 030161 SIO 1 to execute WIOC (Write I/O Channel) 00.000770: 000003 WIOC 00.000771: 100000 SMSK (IMB command) 00.000772: 000000 clear all mask bits 00.000773: 000000 00.000774: 000000 00.000775: 100402 00.000776: 000000 00.000777: 000000 IOMAP is an AID program. It does: 3780 RIOC 14,FF(5) 3790 IF FF(5) AND !F EQ 1 THEN 3870 3800 LET NORESPONS:=1 3810 INIT 3820 HIOP 3825 PROC 3830 BSIO ZZ 3840 IDENT FF(5) 3845 IN H,1,1 3850 RSIO ZZ,,3851 3851 RDRT 3,E .DONE? 3852 IFN E THEN 3870 .BRANCH IF DONE 3853 HIOP .DON'T WAIT FOR GIC TIMEOUT 3854 INIT 3855 LET E:=FALSE 3856 GOTO 3875 3870 LET E:=TRUE 3875 PROC N 3877 LET XX(0):=FF(5) .SAVE ID - SIO 1 to execute SED2 (disable CPP interrupts) - SIO 1 to execute SED2 (enable CPP interrupts, executed twice) - 00.017322 030161 SIO 1 to execute RIOC (Read I/O Channel, executed 11 times) 00.000770: 000002 RIOC 00.000771: 120010 ROCL (IMB command) 00.000772: 000020 channel 11 responds 00.000773: 000000 00.000774: 000000 00.000775: 100402 00.000776: 000000 00.000777: 000000 - 00.017322 030161 SIO 1 to execute RIOC (Read I/O Channel, executed 2 times) 00.000770: 000002 RIOC 00.000771: 007130 RIOD (IMB command, channel 11, register E) 00.000772: 000000 00.000773: 000000 00.000774: 000000 00.000775: 100402 00.000776: 000000 00.000777: 000000 - 00.017322 030161 SIO 1 to execute INIT (Initialize Channel) 00.000770: 000006 INIT 00.000771: 000130 channel 11 00.000772: 000000 00.000773: 000000 00.000774: 000000 00.000775: 100402 00.000776: 000000 00.000777: 000000 - 00.017322 030161 SIO 1 to execute HIOP (Halt I/O Program) 00.000770: 000001 HIOP 00.000771: 000130 channel 11 device 0 00.000772: 000000 00.000773: 000000 00.000774: 000000 00.000775: 100402 00.000776: 000000 00.000777: 000000 - 00.017322 030161 SIO 1 to execute WIOC (Write I/O Channel) 00.000770: 000003 WIOC 00.000771: 100000 SMSK (IMB command) 00.000772: 000020 mask channel 11 00.000773: 000000 00.000774: 000000 00.000775: 100402 00.000776: 000000 00.000777: 000000 - 00.017322 030161 SIO 1 to execute SIOP (Start I/O Channel) 00.000770: 000001 SIOP 00.000771: 000130 channel 11 device 0 00.000772: 000000 00.000773: 101140 channel program pointer 00.000774: 000000 00.000775: 100402 00.000776: 000000 00.000777: 000000 00.101140: 0600 Identify 00.101141: FFFF (result) 00.101142: 0181 Interrupt, halt, CPVA = 1 00.101143: 0001 interrupt code 00.101144: FFFF (end of program?) S6BS0002C seems to implement (some) IOMAP. It determines the channel type by reading register E of each responding channel and checking bits 12-15 of the returned data word. The bits are interpreted as: ID Channel Type ---- ------------ 0 GIC 1 ADCC 2 PIC 3 unknown 4 TIC 5-14 unknown 15 ATP "GIC as a device" is detected by issuing an INIT and checking for CCG. ------------------------- Channel Program Processor ------------------------- The CPP is entered indirectly to start or halt a channel program. The SIOP and HIOP instructions set a bit in a channel register that causes the channel to assert CSRQ. This causes CPP entry when the next machine instruction is fetched. External interrupts are also generated indirectly. The Interrupt channel instruction writes the device number into Register C. This causes the channel to assert the IRQ line. The Starfish inserts an extra level of indirection into both of these operations. A channel program is started or halted by placing the SIOP code and the channel program pointer or the HIOP code into the mailbox and executing an SIO instruction. The IMBA reacts to the DSTARTIO signal by asserting CSRQ. The CPP sends an SPOLn command, sees that the channel is the IMBA (channel 1), looks in the mailbox, picks up and then executes the SIOP or HIOP instruction. The target channel then reacts as above. When the IMB IRQ line is asserted, the CPP is entered, executes an IPOLL IMB command, picks up the channel and device numbers, forms a device number from these, and then executes a WIOC command to write the device number to the IMBA (channel 1). The IMBA reacts by storing the received data word in its DEVNO response register and sets its Interrupt Request flip-flop, asserting INTREQ to the IOP. When the IOP does its INTPOLL, the IMBA gates its DEVNO response register, not its own DEVNO, onto the DEVNO bus. This causes the Series III to use the DRT of the channel and device that originally generated the interrupt. If the IRQ and CSRQ lines are asserted simultaneously, IRQ has priority. The following Channel Program Processor (CPP) description is based on the Series 6x microcode. A channel program is started by executing an SIOP instruction. This sets bits 0 and 1 of DRT3 to indicate that the channel program is to be started and then sends an IMB SIOP command. This sets the bit associated with the device in the channel's New Status register (so named, apparently, because it is used to notify the CPP that the channel program status has changed). Setting the status bit asserts CSRQ, which causes CPP entry after the SIOP instruction completes. This is detected as a bit in the CPX1 (run-time interrupt) register. The CPP is entered at microode label CSRQ (via TCSQ). It sends a SPOLn command to the IMB to obtain the number of the channel asserting CSRQ. It then issues an OBSI command to obtain information describing the request. The channel returns the contents of Register F, which contains the device number corresponding to the New Status register bit; the Device Request bit is set to indicate the request is from the New Status register. The CPP then calls the PAUL (p.191) routine to pause the OBSI response. It: - Branches to CPEX if bit 8 (not valid) is set. - Branches to DMCK (p.192) if bit 7 (channel request) is set. - Branches to EXAM (p.192) if bit 6 (device request) is set. The EXAM routine looks at DRT3 bits 0, 1, and 15 to decide what action is required. EXAM reads DRT3 and: - Branches to NRUN (p.193) if bits 0-1 = 00 (halt the channel program). - Branches to STRT (p.194) if bits 0-1 = 11 (start the channel program). - Branches to AE (p.193) if bits 0-1 = 10 and bits 12-15 = 000x (channel program is running and not suspended). STRT sends another SIOP command to clear the device bit in the New Status register, removing CSRQ assertion. It then changes bits 0-1 to 10 to indicate that the channel program has started and then branches to label AD (p.193). AD writes the device number to Register F and writes 077777 to Register 3 to enable PHI interrupt recognition. The next channel instruction is then fetched at FCH1 (p.195). A channel instruction that writes something to the HI-IB and then waits for a reply (e.g., Identify) reenters the same microcode. It differentiates the cases by testing bit 13 of Register 2 (data available in the inbound FIFO). --- The microcode appears to show that the CPP executes continuously until a Wait, Interrupt/Halt, or Read/Write/Execute DMA instruction is executed. That would seem to suggest that a channel program containing a Jump * would execute forever and not permit the CPU to execute instructions. However, the DUS-III AID diagnostic manual (30341-90006) accepts an HIOP command, which "will terminate the channel program executing on the currently selected device." It gives as an example a channel program that does Jump *+1 and Jump *-1 instructions. So it must be possible to break out of an infinite channel program loop! However, the Machine Instruction Set manual says that the HIOP instruction does not terminate a program immediately. Instead, an HIOP command is "sent to the channel to stop execution of that device's channel command program at the occurrence of the next WAIT channel command." Also, "If the channel program was not at a wait instruction when the HIOP was issued, an interrupt request will be generated when the channel program is halted." So this is not clear. ------------------------------ HP-IB Cold Load/Dump Microcode ------------------------------ The system disc contains the disc label at sector 0, the defective sector table at sector 1, the cold load channel program for HP-IB systems and discs on the Series III HP-IB adapter at sector 2, and the cold dump channel program at sector 3. For SIO systems, the disc label begins with the six-word cold load program (Control, Read, Jump). For HP-IB systems, the label begins with the twelve characters "SYSTEM DISC ", and words %25 and %26 contain the cylinder and head/sector continaing the microcode to be loaded into the Series 6x/7x WCS. Note that the cold dump process is entirely different for HP-IB systems. Rather than having the microcode perform the actual transfer from memory to tape, a cold dump loads a "soft dump" program from the system disc. In this aspect, the process is more like an auxiliary cold load. The tables manual shows a "Firmware Area" located between the System Global Area (ending location %1527) and the Sysglob Extension (starting location %1740). The Series 3x/4x load and dump procedures are outlined in the Machine Instruction Set Reference Manual (July 1984) pages 2-125 through 2-130. The manual also says that the Series 37 DUMP instruction ends with a cold-load trap. [Machine Instruction Set pp.152] Logically, the cold load process does this for discs: 1. Build a MAC or CS/80 program starting at memory location %1423. 2. Set DRT + 0 to %1423 and issue an SIOP to start the program. 3. The program reads disc sector 2 into memory starting at location %1530. [ but program wants to load at %7100 !!! ] 4. Set DRT + 0 to %1530 and issue an SIOP to start the program. 5. The program reads disc sectors 19-21 into memory starting at location %7100. [STOP] 3. The program reads tape record 0 into memory starting at location %7100. ----- The Series 64 cold load microcode performs these actions [LOAD p.57]: - Write %30370 (HALT 10) to each word of memory. The dump microcode performs these actions [DUMP p.59]: - Copy the contents of CPU registers to memory locations %1401-%1422. - Copy the system halt code to %1514. - Copy the cold load device DRT to memory locations %1516-%1521. - Copy the DRT bank and offset to memory locations %1522-%1523, and the interrupt mask to location %1524. The cold load and dump routines then perform these actions together [CLD0 p.61] - Issue I/O CLEAR to all channels. IMB (IOCL) -- [CLD1 p.62] - Initialize the channel for the cold load device [CINT p.66]. IMB (INIT) -- [CINT p.66] if reg1(8) = 0 then -- if not sys cntlr system_halt (%14) -- [NSYC p.29] else reg6 := %10 -- set poll response [?] reg7 := %200 -- go online reg6 := %60 -- assert REN + IFC wait 100 usec reg6 := %40 -- deny IFC reg2 := %177777 -- clear all interrupt conditions if reg1(11) = 0 then -- if not cic system_halt (%21) -- [NCON p.29] else reg0 := !4014 -- send DCL end if end if - Identify the type of device (the first IDENT byte indicates disc or tape; this does not use a channel program but instead issues the ID sequence directly): reg0 := !403E -- [CRT1 p.62] Listen 30 reg0 := !405F -- Untalk reg0 := !4060 + device -- secondary address reg0 := !C002 -- remove ATN, receive 2 bytes reg3 := %2 -- enable outbound FIFO empty interrupt for cntr := 0 to 255 loop -- loop while waiting for ID to arrive delay 13 msec -- tight loop 65536 times if reg2 /= 0 then exit end loop if reg2 = 0 then -- if ID never arrived id := %177777 -- use an invalid ID else id := reg0 and %377 -- read first byte dummy := reg0 -- toss second byte reg0 := !405E -- talk 30 reg0 := !403F -- unlisten end if - Reinitialize the channel for the cold load device [CINT p.66]. (Does the same thing, except DCL is done only if ID is 0, i.e., MAC disc) - Issue DEVICE CLEAR. - Copy the appropriate channel program to memory locations %1423-%1505, based on the high byte of the Identify return (0 = MAC disc, 1 = magnetic tape, 2 = CS/80 disc). if id = 0 then -- 13037 disc write MAC disc program to %1423 -- [DSCP p.67] elsif id = 2 then -- CS/80 disc or tape write CS/80 program to %1423 -- [NSDV p.113] and [CLCT p.71] elsif id = 1 then -- 7970E tape write 7970E tape program to %1423 -- [MTCP p.68] else -- illegal cold load device system_halt (%6) -- [CPTO p.29] channel timeout end if - For cold load, modify fhe disc I/O program to read from sector 2 and into location %7100 (the channel programs are written for cold dump, which reads from sector 3 and into location %1530). - Set up a DRT entry for the cold load device. drta := chandev * 4 -- [DMP1 p.63] set DRT address M [drta + 0] := %1423 -- channel program pointer M [drta + 2] := %1427 -- CPVA pointer M [drta + 3] := !C000 -- channel status (program starting) IMB (SMSK) -- set interrupt mask for device - Issue an SIOP command to load 256 bytes from the tape or disc. M [%1427] := 0 -- clear CPVA 0 IMB (SIOP) -- send SIOP to channel - When the channel program halts, compute and check the bootstrap checksum; the checksum initial seed value is %123456. If the checksum is OK, issue an SIOP command to execute the bootstrap. // instead of looking at CPVA 0, can also look at CPX1 for interrupt on IMBA while timeout < 48 sec loop -- [CCL p.64] if M [%1427] /= 0 then exit -- if INT/H instruction exeucted end loop if timeout then system_halt (%6) -- channel timeout else -- [LD2 p.65] completion cksum := M [%7100] -- checksum of sector accum := %123456 -- checksum accumulator for cntr := 1 to 255 loop accum := accum + M [%7100 + cntr] end loop if cksum /= accum then -- if they disagree system_halt (%7) -- bootstrap checksum error else reg12 := device -- clear interrupt M [drta + 0] := %7101 -- set channel program address M [drta + 3] := !C000 -- channel status (program starting) M [%1427] := 0 -- clear CPVA 0 IMB (SIOP) -- send SIOP to channel end if end if Actually, the completion test isn't quite right. We need to differentiate between a completion interrupt and a DMA abort. CCL seems to call CSRQ to enter the CPP directly under some condition. - When the channel program halts, check CPVA 0. If it is %100000, then set up ICS and trap to segment 1, STT #44. while timeout < 48 sec loop -- [CCL p.64] if M [%1427] /= 0 then exit -- if INT/H instruction exeucted end loop if timeout then system_halt (%6) -- channel timeout else -- completion reg12 := device -- clear interrupt if M [%1427] = %100000 then -- if normal interrupt halt set up ics [Q-9] := 1 -- indicates "CST extension" for V/E w/new microcode parameter := chan/dev cold_load_trap -- then trap to start MPE else -- othewise system_halt (%10) -- channel program abort end if end if Registers for all CPUs are copied as follows (note these are different than the Series III locations and are detailed in the MPE V/E tables manual): Location Contents -------- -------------------------- 1401 DUMP CHANNEL/DEVICE NUMBER 1402 X REGISTER 1403 DL REGISTER 1404 DB-BANK REGISTER 1405 DB REGISTER 1406 Q REGISTER 1407 SM REGISTER 1410 S-BANK REGISTER 1411 Z REGISTER 1412 STATUS REGISTER 1413 PB-BANK REGISTER 1414 PB REGISTER 1415 P REGISTER 1416 PL REGISTER 1417 CIR REGISTER 1420 NUMBER OF MEMORY BANKS The following locations are CPU-dependent; these are the Series 3x/4x/5x values: Location Contents -------- --------------------- 1421 System halt number 1422 SIR Register (labeled ISR in the dump) 1515 System interrupt mask 1516 DRT 0 1517 DRT 1 1520 DRT 2 1521 DRT 3 The manual states that "the contents depend on the type of CPU that MPE is running and whether a dump, powerfail, or CTRL+B halt has occurred." MAC Disc Channel Program [CLDD p.67] ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 0313: 0200 0000 WAIT FOR PPOLL 0315: 0408 0002 0000 0000 033E SET FILEMASK 031A: 0200 0000 WAIT FOR PPOLL 031C: 0408 0002 0000 0000 0343 READ STATUS 0321: 0308 0004 0000 0000 0344 READ 4 STATUS BYTES 0326: 0200 0000 WAIT FOR PPOLL 0328: 0408 0006 0000 0000 033F SEEK 032D: 0200 0000 WAIT FOR PPOLL 032F: 0408 0002 0000 0000 0342 READ 0334: 0300 0100 0000 0000 0E40 READ 256 BYTES TO ADDRESS %7100 0339: 0200 0000 WAIT FOR PPOLL 033B: 0180 0000 INTERRUPT/HALT 033D: FFFF 033E: 0F05 FILE MASK COMMAND 033F: 0200 0000 0002 SEEK COMMAND TO SECTOR 2 0342: 0500 READ COMMAND 0343: 0300 STATUS COMMAND 0344: 0000 0000 STATUS BUFFER Notes: 1. Word %1470 is changed from %1530 (!0358) for dump to %7100 (!0E40) for load. 2. Word %1501 is changed from sector 3 for dump to sector 2 for load. CS/80 Disc Channel Program [CBFD p.71] read to %1423 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 0313: 0600 0000 IDENTIFY 0315: 0200 0000 WAIT FOR PPOLL 0317: 0503 0000 0000 003C FFF6 003C DSJ 031D: 0405 0009 0009 8000 033F SET STATUS MASK 0322: 0200 0000 WAIT FOR PPOLL 0324: 0502 0000 0000 0030 FFEA DSJ 0329: 0405 000D 000D COOO 0343 SET ADDRESS, SET LENGTH, LOCATE AND READ 032E: 0200 0000 WAIT FOR PPOLL 0330: 030E 0100 0000 0000 0E40 READ IN CHANNEL PROGRAM TO ADDRESS %7100 0335: 0200 0000 WAIT FOR PPOLL 0337: 0503 0000 0000 001C 001C 001C DSJ 033D: 0180 0000 INTERRUPT/HALT 033F: 3E00 0000 0000 0008 74-- 0343: --11 0000 0000 0002 1800 0001 0000 034A: 000D CS/80 Read Status Program [SBFD p.71] read to %1531 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 0359: 0405 0001 0000 C000 034A REQUEST STATUS 035E: 0200 0000 WAIT FOR PPOLL 0360: 030E 0014 0000 0400 0367 READ STATUS 0365: 0180 0003 INT/HALT (ABNORMAL) Notes: 1. Word %1464 (!0334) is changed from %7100 (!0E40) for load to %1530 (!0358) for dump. 2. Word %1506 (!0346) is changed from sector 2 (for load) to 3 (for dump). 3. The checksum word count is changed from 128 (for load) to 64 (for dump). 4. For dump, the channel program is read into locations %1530, but that wipes out the Request Status command before QSTAT is tested. The DSJ that follows can jump to %1531 if QSTAT > 0. Maybe the idea is that if QSTAT > 0, then nothing has been read, and so the Read Status program is intact. Magnetic Tape Channel Program [CLDT p.54] ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 0313: 0401 0001 0000 4400 0314 SELECT UNIT 0 0318: 0200 0000 WAIT FOR PPOLL 031A: 0500 0000 0000 ISSUE DSJ 031D: 0401 0001 0000 4400 0341 READ RECORD 0322: 0200 0000 WAIT FOR PPOLL 0324: 0500 0000 0000 ISSUE DSJ 0327: 0300 0100 0440 8000 0E40 READ BOOTSTRAP PROGRAM TO ADDRESS %7100 032C: 0000 0002 RELATIVE JUMP COUNT DONE 032E: 0000 FFF2 RELATIVE JUMP BURST DONE 0330: 0407 0001 0000 4400 0342 END COMMAND 0335: 0302 0002 0000 0400 0343 READ BYTE COUNT 033A: 0200 0000 WAIT FOR PPOLL 033C: 0500 0000 0000 ISSUE DSJ 033F: 0180 0000 INTERRUPT/HALT 0341: 0008 READ RECORD COMMAND 0342: 0013 END COMMAND PARAMETER Notes: 1. Word %1453 (!032B) is changed from %7100 (!0E40) for load to %1530 (!0358) for dump. ------------------------- HP-IB Cold Dump Microcode ------------------------- (Reference: Console Operator's Guide Series II, III, 30, 33, and 44, 32002-90004 May-1981.) The cold dump for the HP-IB systems, e.g., Series 44, reads the channel program from sector 3 of the system disc. This loads the Software Dump Facility (SDF), which is an SPL program that performs the actual dump. The channel and device numbers for the cold load and cold dump operations are set with thumbwheel switches on the system control panel. The notes on page 2-16 say, "Pressing [the LOAD] switch initiates a cold load from the device and channel set in the thumbwheel switches directly below the LOAD switch," and, "Pressing [the DUMP] switch initiates a dump of the system's memory. The channel and device address of the system disc (or other device from which the Software Dump Facility is being loaded) are set in the thumbwheel switches below the DUMP switch." Typically, then, both sets of thumbwheel switches would be set to the same values, as both would reference the system disc. From page 5-82, the dump device is "a logical device specified by the device class DDUMP." (As an aside, a note on page 2-22 says, "The hardware channel boards which can be referenced by the thumbwheel switches are numbered 4 through 11.) The Starfish cold dump does not do this. The note on page 2-5 says, "For systems with the HP-IB Interface Module, but 0-7 are set to the octal address of the dump device; bits 8-15 are set to the octal address of the interface." Further, page 5-34 says, "On systems with a 7976A Tape Drive, a successful dump is indicated by the tape rewinding, and the drive going offline." Also, notes on the same page indicate that the memory module count in the CIR that displays the progress of the dump does not appear when dumping to the Starfish. --------------- Instruction Set --------------- MPE HARDRES (module 55) uses: - SIOP - HIOP - RIOC - WIOC - SED2 - INIT The ROCL and IOCL instructions are not used directly. Instead, ROCL is issued via a RIOC instruction, and IOCL is issued via a WIOC instruction. ------------------------ Channel Program Behavior ------------------------ A channel program begins or resumes execution as a result of CSRQ assertion. From the Series 6x microcode, it appears to run continuously until it suspends to wait for some channel action, such as the outbound FIFO emptying, data arriving in the inbound FIFO, or a parallel poll response. In particular, a program containing an infinite loop, e.g., a JUMP to itself, should lock the machine, as it simply alternates CP instruction fetches and JUMP executions. However, the AID manual shows that the HIOP instruction will stop such a program, and that indeed does occur when tested on a Series 37. The mechanism by which this works is not clear. The following AID programs were tested on a Series 37 with this configuration: IOMAP SYSTEM I/O CONFIGURATION ----------------------------------------------------------------- >Cold load switch register settings: Channel=4 Device=3 PATH=0 >System console is device 0 on channel 1 ----------------------------------------------------------------- Channel 1 ID=!4 Terminal Interface Channel (TIC) (CODE=3) ----------------------------------------------------------------- Channel 3 ID=!4 Terminal Interface Channel (TIC) (CODE=3) ----------------------------------------------------------------- Channel 4 ID=!2 Peripheral Interface Channel (PIC) Device 3 ID=!183 7970E Mag Tape Controller (CODE=2) Unit 0 7970E Mag Tape Drive ----------------------------------------------------------------- Explanation of '(CODE= )' 1 implies: NO LOOPBACK Capability. 2 implies: NO SELFTEST Capability. 3 implies: LOOPBACK/SELFTEST only available in product diagnostic. ------------------------------------------------------------------ This program was tested first. The run time was determined, line 30 was changed to GOTO 90 (bypassing the channel program execution), and run time was determined again. There is no apparent difference when the CPP is running vs. when it is idle. 10 LET CHANNEL:=3 20 LET DEVICE:=0 30 GOTO 40 40 PROC 50 BSIO AA 60 JUMP 70 70 JUMP 60 80 RSIO 90 FOR I:=1 UNTIL 100 100 PRINT "HELLO THERE" 110 NEXT 90 120 HIOP 130 END This program was also tested in the same manner. Again, there is no apparent difference regardless of whether the CPP runs or not. 10 LET CHANNEL:=3 20 LET DEVICE:=0 30 GOTO 40 40 PROC 50 BSIO AA 60 JUMP 70 70 JUMP 60 80 RSIO 90 FOR I:=1 UNTIL 10000 100 NEXT 90 110 HIOP 120 END If the micromachine switches between executing machine instructions and executing channel programs, and if the CPP executes continuously, then even if there is some mechanism by which the machine instruction part regains control, there should still be some CPU time absorbed in executing the channel program infinite loop. Yet, none is apparent. 10 LET CHANNEL:=11 20 LET DEVICE:=0 40 PROC 50 BSIO AA 60 JUMP 70 70 JUMP 60 80 RSIO 120 HIOP 130 END Read, Write, and DMA Instructions ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The Read [Control] and Write [Control] instructions receive and send data across the HP-IB. The Execute DMA instruction works identically, except that the [Un]Talk and [Un]Listen device protocol commands that normally bracket the transfers are omitted. Hence, all MPE drivers will use Read/Write instructions instead. These instructions support data chaining, record vs. burst modes, and output of a specified secondary address prior to the transfer of data. Execute DMA is provided to permit diagnostic testing of transfers between two GICs. The read and write instructions provide transfers either as a complete block ("Record Mode") or in smaller increments ("Burst Mode") that are repeated until the entire transfer is complete. Record Mode is more efficient, as the entire transfer is accomplished with a single CPP instruction. Burst Mode executes one burst per instruction, so successive instructions are required. These are typically performed in a loop. The intent of Burst Mode is to free up the bus after a relatively fast transfer between a device buffer and main memory while the buffer empties or refills relatively slowly. Burst mode is provided by the 7970E HP-IB tape drive and was used by the MPE driver (module 35, HIOTAPE0). Other tape drives, as well as all disc drives, use Record Mode exclusively. However, an update to the 7970 driver changed it to use Record Mode as well, with this comment: "This was done to prevent tape-runaway problems due to CPP going away for periods of time longer than the tape could stand." This change might be the reason why 7970 tape drives must be on their own GIC. The 7908/12/14 integrated cartridge tape driver (HIOCTAP0, module 42) uses burst mode, albeit with 256-byte bursts. DMA hardware on the GIC is used for all transfers except burst mode transfers with a burst size of one byte. Record mode sets up DMA to transfer the entire byte count. Burst mode limits the transfer to the smaller of the byte count and the burst size. The microcode handles a burst count of one by transferring directly, rather than setting up a one-byte DMA transfer. Burst Mode transfers of single bytes are used by the ADCC driver. The ADCC does not have DMA capability, so specifying a multibyte transfer with a one-byte burst length allows the entire transfer to be handled by the CPP. This avoids the per-character MPE interrupts that were required with the ATC. Each execution of a Burst Mode read or write instruction transfers one burst. In order to transfer a full block, multiple Burst-Mode instruction executions are usually required, necessitating a loop. To permit this, the instructions return to different locations, depending on whether additional bursts are needed. For the Read [Control] instruction, control transfers to one of three locations, depending on the transfer status. If the instruction ends by receiving a data byte tagged with EOI, then execution continues with the next instruction. If it ends by by burst count exhaustion and not byte count exhaustion, then the next two-word instruction is skipped, and execution continues with the following instruction. If it ends by byte count exhaustion, then the instruction's Termination Displacement field is added to the address of the next instruction to determine the execution target. In tabular form, where * represents the first location following the Read instruction: Location Reason for Read Termination -------- ----------------------------- * + 0 Byte tagged with EOI received * + 2 End of burst but not transfer * + Disp End of transfer without EOI For the Write [Control] instruction, control transfers to one of two locations (as these instructions do not have a Termination Displacement field). If the instruction ends by byte count exhaustion, then execution continues with the next instruction. If it ends by by burst count exhaustion and not byte count exhaustion, then the next two-word instruction is skipped, and execution continues with the following instruction. In tabular form, where * represents the first location following the Read instruction: Location Reason for Write Termination -------- ----------------------------- * + 0 End of transfer * + 2 End of burst but not transfer The following AID program was run under DUS-III: 10 DB BB,256,0 20 LET CHANNEL:=11 30 LET DEVICE:=0 40 BSIO AA 50 RB 3,BB(0),100 60 RB 5,BB(0),110,10 70 RB 5,BB(0),120,256 80 RDMAB BB(0),130 90 RDMAB BB(0),140,40 100 RDMAB BB(0),150,256 110 RDMAR BB(0),160 120 RR 7,BB(0),170 130 IN H 140 RSIO 150 END The read commands above produced these channel instructions: (RB) Read 3 count 100 burst 1 address 00100000 blocks 0 termination 100465 | burst mode | left byte (RB) Read 5 count 110 burst 10 address 00100000 blocks 0 termination 100472 | burst mode | left byte (RB) Read 5 count 120 burst 256 address 00100000 blocks 0 termination 100477 | burst mode | left byte (RDMAB) Execute DMA count 130 burst 1 address 00100000 termination 100504 | burst mode | left byte | read (RDMAB) Execute DMA count 140 burst 40 address 00100000 termination 100511 | burst mode | left byte | read (RDMAB) Execute DMA count 150 burst 256 address 00100000 termination 100517 | burst mode | left byte | read (RDMAR) Execute DMA count 160 burst 1 address 00100000 termination 100523 | record mode | left byte | read (RR) Read 7 count 170 burst 1 address 00100000 blocks 0 termination 100530 | record mode | left byte The following program was run under DUS-III: 10 DB BB,256,0 20 LET CHANNEL:=11 30 LET DEVICE:=0 40 BSIO AA 50 RR 3,BB(0),100,,R,80 60 JUMP 70 70 JUMP 80 80 JUMP 90 90 IN H 100 RSIO 110 END Producing: 00.100423 Read 3 count 100 burst 1 address 00100000 blocks 0 termination 100434 | record mode | right byte 00.100430 Relative Jump 100432 00.100432 Relative Jump 100434 00.100434 Relative Jump 100436 00.100436 Interrupt/Halt 0000 | CPVA 0 For the ADCC driver (IOTERM0, module 26), the displacement skips over "error" returns caused by BREAK or special character reads. Transfer Mode and Data Chaining ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ A data transaction across the bus consists of addressing the device to Talk or Listen, sending a command secondary to indicate the type of transaction, sending or receiving a stream of data typically ending with the last byte tagged with EOI, and unaddressing the device with an Untalk or Unlisten. A sequence of read or write (but not DMA) instructions may be chained together to form a single transfer. For the Series III, chained transfers were needed because channel instructions were limited to a transfer of 4K bytes. For the CPP, a single instruction can transfer up to 64K bytes. Still, chained transfers may also specify different source or destination buffers and different memory access modes (e.g., single address vs. incrementing address). A chained transfer is indicated by a non-zero value in the Data Chain field of the first read or write instruction. For a non-zero value N, the instruction is the first of N-1 consecutive instructions that collectively form a single transfer, with each succeeding instruction's field indicating the number of remaining fields that follow. For example, this four-sector disc read: 100 RR 0,JJ(0),256,DC=2 110 RR 0,BB(0),512,DC=1 120 RR 0,FF(128),256,DC=0 ...stores the first sector into buffer JJ, the next two into buffer BB, and the final sector into buffer FF starting at element 128. The usual transfer method is Record Mode. This transfers all requested data in a single transaction. For buffered devices that transfer relatively slowly, such as the 7970E, the bus can be used more efficiently if data is transferred in bursts corresponding to the buffer size. Burst Mode breaks up a transaction into a series of bursts that free the bus between transfers. The combination of transfer and chaining modes gives four possibilities: Transfer Chaining Data Transfer -------- -------- ----------------------------------------------------- Record None as a single block Record Chained as a single block consisting of several joined blocks Burst None as a small burst repeated for the full block Burst Chained as several small bursts repeated for the full block The partial AID programs corresponding to a 300-byte read transaction for the 7970E are as follows. These assume that the Read Record command has been sent, and the parallel poll response has been received. For Record Mode with no chaining: RR 0,AA(0),300 Unless the U (no update) bit is set in the instruction, the byte count in the second word, the R (left/right) bit in word 4, and the memory address in word 5 are updated and written back into the instruction parameters. For example, a odd-length transfer completes with the byte count set to 0, the R bit complemented, and the memory address incremented by the number of whole words transferred. For Record Mode with chaining: RR 0,AA(0),100,DC=2 RR 0,BB(0),100,DC=1 RR 0,CC(0),100,DC=0 [RDT1 p.214] Record mode data chaining executes entirely through the sequence before fetching another instruction. That is, upon DMA termination for an RR command, the next command in the sequence is set up and started before returning to the Fetch routine. For Burst Mode without chaining: RB 0,AA(0),300,50 JUMP WAIT JUMP Each time the RB instruction is executed, the number of bytes specified by the burst count is transferred. The device is addressed prior to the burst and unaddressed at the conclusion. Unless the U bit is set, each pass decrements the byte count and increments the address by the amount transferred. When the byte count reaches zero, the exit is taken. If the byte count is greater than the burst count, then it appears that executing a burst-mode instruction with the U bit set will continue to execute until a DMA abort or other terminating condition (e.g., EOI) is encountered. For Burst Mode with chaining: RB 0,AA(0),100,50,DC=2 RB 0,BB(0),100,50,DC=1 RB 0,CC(0),100,50,DC=0 JUMP WAIT JUMP In this example, the transfer reads two 50-byte bursts into buffer AA, then two 50-byte bursts into buffer BB, and finally two 50-byte bursts into buffer CC. Each pass through the loop transfers a single burst, skips any intervening chained instructions (by using the current instruction's DC field), and then executes the WAIT and JUMP instructions. Error termination of chained transfers similarly skips any intermediate chained instructions before resuming execution. When the transaction is complete, all of the byte counts will be zero. For record mode writes, the E bit is ignored; EOI is always asserted at the end of a transaction and never asserted at the end of intermediate chained transfers. For burst mode writes, the E bit specifies whether or not EOI is asserted for intermediate transfers. EOI is always asserted at the end of a burst transaction. Single-byte burst writes are tagged with EOI if E = 0. Setting E = 1 omits EOI unless the byte ends the transaction (i.e., when DC = 0 and byte count = 1). The Data Chain Optimization ~~~~~~~~~~~~~~~~~~~~~~~~~~~ Data chaining employs an optimization to skip over chained instructions that have completed their transfers. Consider this four-instruction transfer: RB 0,AA(0),100,50,DC=3 RB 0,BB(0),100,50,DC=2 RB 0,CC(0),100,50,DC=1 RB 0,DD(0),100,50,DC=0 JUMP WAIT JUMP The transaction begins with the channel program pointer at the first instruction. The first 50-byte transfer is made, the byte count and address are updated, and then the DC field is used to move the program pointer directly to the WAIT instruction. After the JUMP moves the pointer back to the first RB instruction, the second 50-byte transfer is made, and the byte count and address are updated. At this point, the first RB instruction is complete. When the JUMP is executed to return the pointer to the first instruction, the CPP would have to read the byte count, discover that it is zero, and then increment the pointer to execute the second RB instruction. As each instruction completes its two bursts, the process would repeatedly read-and-skip over the set of completed instructions before reaching the remaining active one(s). To eliminate these unnecessary program instruction reads, completion of the first instruction's bursts sets the DC field to 1, so that the field indicates the number of instructions to skip to reach the next active instruction. Completion of each succeeding instruction's bursts increments the first instruction's DC field. This allows the CPP to move directly from the first instruction (target of the JUMP) to the active instruction without having to examine the intermediate instructions for non-zero byte counts. In the example, updating of the first instruction's DC field proceeds as follows: RB DC=3 --> RB DC=1 --+ --> RB DC=2 --+ --> RB DC=3 --+ RB DC=2 RB DC=2 <-+ RB DC=2 | RB DC=2 | RB DC=1 RB DC=1 RB DC=1 <-+ RB DC=1 | RB DC=0 RB DC=0 RB DC=0 RB DC=0 <-+ Interpretation of the DC field occurs when the first instruction is re-executed and its byte count is zero. Note that when all instructions have executed, the original DC field value is automatically restored to the first instruction. This does not occur, however, if the transaction terminates abnormally, e.g., by receiving a byte with EOI before the count is exhausted. For example, if the second instruction receives an EOI, the first instruction's DC field will remain set to 1 instead of being restored to 3. This seems like a bug, as the CPP could restore the value by adding the active instruction's DC field to the first instruction's DC field and rewriting the latter. Note also that the program pointer remains at the first instruction when subsequent chained instructions are executing, rather than being updated to point at the current instruction. So when a DMA completion request causes the CPP to be reentered, the first instruction's DC field is again used to locate the current instruction. This is necessary to be able to increment the first instruction's DC field when a subsequent instruction's byte count is exhausted. Halt vs. Cleanup and Halt ~~~~~~~~~~~~~~~~~~~~~~~~~ Two channel termination routines are provided: CHRA and HLTP (PDF p.202 in the Series 68 microcode manual for both). The general error routine, CHR (p.194) stores the error code in the CPVA and branches to one of the two routines, depending on the setting of F1 (flag 1). If set, the branch is to HLTP to halt the channel program. If clear, the branch is to CHRA to "clean up the bus" before falling into the HLTP code. In particular, CHRA does an Unlisten and Untalk, whereas HLTP does not. F1 is set and cleared multiple times during CSRQ handling, so determining its setting when CHR is called to abort the program is difficult. It appears that these are the actions: Code Cleanup Meaning ---- ------- ---------------------------------------------------------- A000 Y HIOP During Active Service Cxxx Y DMA Abort E001 Y Invalid channel instruction E002 Y Data chain error E004 Y Channel hardware timeout E008 - Non-responding IMB module E010 - Memory parity error E020 * Illegal CSRQ E040 - Serial poll error E080 Y Processor handshake aborted due to FIFO overflow/underflow E100 Y Device Clear (DCL) universal command has been received E200 Y Status has changed E400 Y Parity error detected on received bus command E800 Y Address rollover (non-DMA) (*) No if halt pending and waiting for condition, else Yes. IOMAP ~~~~~ The IOMAP program sends Identify commands to all devices on the bus and displays the identities of the responding devices on the console. These channel programs are used: 7976 Tape Drive: Identify | response 0176 Interrupt/Halt 0001 | CPVA 1 7970E Tape Drive: Identify | response 0183 Interrupt/Halt 0001 | CPVA 1 Command HP-IB 224 [ Universal Clear ] Wait | CPVA 0 | response 0005 Device Specified Jump 101224 Write secondary 01 count 1 burst 1 address 00101116 chain 0 | record mode | right byte [ Select Unit 0 ] Wait | CPVA 0 | response 5252 Device Specified Jump 101236 Read secondary 01 count 3 burst 1 address 00101117 chain 0 termination 101243 | record mode | left byte [ Read Status ] Relative Jump 101245 Interrupt/Halt 0001 | CPVA 1 7906/7920/7925 Disc Controller: Identify | response 0002 Interrupt/Halt 0001 | CPVA 1 Clear 000 Write secondary 10 count 2 burst 1 address 00101115 chain 0 | record mode | left byte [ Request Status ] Read secondary 10 count 4 burst 1 address 00101113 chain 0 termination 101205 | record mode | left byte [ read status bytes ] Interrupt/Halt 0001 | CPVA 1 When starting IOMAP with the "GO 1" command, these optional tests are presented: Test Section 2 ---- IDENTIFY Test Section 3 ---- SELF TEST Test Section 4 ---- LOOPBACK Test 2 works as expected. It undestands these hex ID codes: Code Device ---- ------------------------------------------ 0001 7910 Fixed Disc 0002 7906/7920/7925 Disc Controller 0080 Flexible Disc Unit (Single sided) 0081 Flexible Disc Unit (Double-sided) 0100 31207 Writable Control Store 0101 2893 Card Reader 0102 9875 Cartridge Tape Controller 0176 7976 Mag Tape Unit 0183 7970E Mag Tape Controller 2000 9871 Character Printer 2001 2608 Dot Matrix Printer 2002 2631A Serial Printer 2003 2617 Line Printer 2004 2680 Page Printer 2005 9872 Plotter 2006 7245 Plotter/Printer 2009 2631B Serial Printer 2080 Integrated Display System 200A 2613/2617/2619A Line Printer 4000 31281 SDLC-EIA Interface 4001 BISYNC Interface 4002 30020A Intelligent Network Processor (INP) 4003 30020B Intelligent Network Processor (INP) 6000 31262 GIC acting as a device 6080 9845 Calculator 8000 31321 Processor Maint. Panel A000 9874 Digitizer Notably, none of the CS/80 drives ostensibly supported by the Starfish are included. Test 3 issues a Listen and Secondary 1F sequence and then waits for a one-byte response. Secondary 1F is the Amigo self-test command. CS/80 devices do not respond to this code, so the report: Initial SELFTEST Results = !100. Unit failed test. ...is bogus. Test 4 issues a Listen and Secondary 1E sequence and then sends 256 data bytes. Secondary 1E is the Amigo loopback command. CS/80 devices do not respond to this code, so the report: Loopback Error: pass 0 Byte 0 Received !1 Sent !0 Loopback Error: pass 0 Byte 1 Received !0 Sent !1 [...] Loopback Error: pass 0 Byte 255 Received !0 Sent !FF is also bogus. Other Commands ~~~~~~~~~~~~~~ 10 LET CHANNEL:=11 20 LET DEVICE:=0 30 BSIO XX 40 CHP 1,2,3,4,5 50 IN H 60 RSIO 10 LET CHANNEL:=11 20 LET DEVICE:=0 30 BSIO XX 40 JUMP 50 50 WRIM -3,4 60 JUMP 40 70 IN H 80 RSIO 10 LET CHANNEL:=11 20 LET DEVICE:=0 30 BSIO XX 40 IDENT X 50 IN H 60 RSIO 10 DB BB,7,0 20 CPVA BB(O) 30 LET CHANNEL:=11 40 LET DEVICE:=0 50 BSIO AA 60 DSJ 80,70;A 70 IN H,0,7 80 IN H 90 RSIO 100 PRINT "DSJ=";A;" CPVA0=";BB(0) ---------------------------- General I/O Channel Behavior ---------------------------- DMA Enable vs. DMA Inactive Signals ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Bit 0 of Register 8 (Enable bit) is the DMAENF signal, which reflects the state of the DMA Enable flip-flop. The signal asserts when Register 11 is written to initiate a DMA transfer. It denies when DMA is aborted (either by writing to Register 14 or by an operation timeout), a power-on clear occurs, a DMA interrupt is asserted by the DMA state machine, or a DMA error is detected (memory parity error, etc.). Bit 7 of Register 11 (Busy bit) is the ~DMAINACT signal, which asserts when DMA is inactive. DMAINACT = ~DMAENF * DMOFF, which asserts when the DMA Enable flip-flop is clear and the DMA state machine has returned to the idle state. These two bits indicate the condition of the DMA state machine, as follows: DMAENF DMAINACT E B DMA State ------ -------- - - ------------------------------- 0 1 0 0 Idle 1 1 1 0 (transient) 1 0 1 1 Active 0 0 0 1 DMA interrupt; waiting for OBSI The 11 state persists only until DMAENF assertion propagates to DMAINACT denial. When the DMA transfer either completes or is aborted, the DMA Enable flip-flop is cleared, but the DMOFF signal remains denied with DMINT is asserted until the OBSI is received, indicating that the channel request is being serviced. The DMA state machine then returns to the idle state. Consequently, a DMA interrupt codition is indicated by E = 0 and B = 1. DMA Status Flip-Flops ~~~~~~~~~~~~~~~~~~~~~ The two DMA status flip-flops produce the DMASTATAF and DMASTATBF signals. These are clocked by the DMASETEND signal when the DMA count register decrements to zero or the EOI signal is received during a read and are reflected in register B bits 5 and 6, respectively. The logic is: DMASTATA.D := ~D0 * DMAIN * DMAENF DMASTATA.PR = DMERR + ~DMAENF * (DMY1 + DMY3 + DMY4) DMASTATA.CL = WRREGB + PONCLR DMASTATB.D := D0 * ~D1 * DMAIN * DMAENF DMASTATB.PR = DMERR + ~DMAENF * (DMY1 + DMY3 + DMY4) DMASTATB.CL = WRREGB + PONCLR The D inputs are qualified by DMAIN, so the flip-flops can set only during a Read operation. Status A clears if the PHI received either the specified number of bytes for a counted transfer or a byte tagged with EOI, and sets otherwise (i.e., DMA terminated due to the DMA count expiring). Status B is sets if the last byte was counted and clears either if the last byte was tagged with EOI or was LF and termination on LF was specified. Both status bits are set if a DMA error occurred. Therefore, the combined termination status is: Status Flip-Flop States Read Write ------ --------------------- ----------- --------- 00 ~DMASTATA * ~DMASTATB tagged byte DMA count 01 ~DMASTATA * DMASTATB final byte (unused) 10 DMASTATA * ~DMASTATB DMA count (unused) 11 DMASTATA * DMASTATB error error The DMA count terminations are implied. For reads, the condition occurs only if DMA ended after receiving a normal data byte. For writes, the DMAIN qualification on the D inputs prevents the flip-flops from setting except via the Preset inputs, so only if DMERR is asserted or DMA is aborted by writing to register E. Reading register B obtains the DMA status. However, the microcode seems to differ from the schematic regarding interpretation: ------ schematic ------ ------ microcode ------ Status Record Mode Burst Mode Record Mode Burst Mode ------ ----------- ---------- ----------- ---------- 00 EOI seen EOI seen EOI seen EOI seen 01 abort count done abort count done 10 count done count done count done abort 11 abort abort abort abort The GIC diagnostic manual (30070-60068, December 1983) Volume 2 page 3-7 (PDF page 112) describes the DMA state machine test. It says, "Each [input and output state machine] loop also has two normal termination exits and two abort termination exits." It also says that Step 20, "Verifies that a data transfer can be aborted at states 8, 10, 26, and 24. All four aborts correspond to clearing the DMA Enable flip-flop. Page 3-8 (PDF page 113) says that Steps 25-27 verify the DMA abort conditions, which are listed as: - Memory handshake timeout - Memory parity error - Address overflow - Clear Error - Data Not Valid The DMABORT signal is DMASTATAF * DMASTATBF * DMINT, i.e., is asserted when the DMA status flip-flops are both set and a DMA interrupt occurs. Step 28 is the "DMA termination status test" and lists these termination states, based on the DMASTATA and DMASTATB flip-flops: Status Description ------ --------------- 00 count and end 01 count subrecord 10 count no end 11 error The manual does not differentiate between Record Mode and Burst Mode terminations. The PIC diagnostic (S28S231A.SPL) has this comment: << S T E P 2 8 -- DMA Termination Status Test << Verifies correct input DMA status: << 00 - Count and End. Byte count exhausted and last byte flagged << with EOI. Put a byte with the end flag set into the outbound << FIFO, then start an input DMA transfer of one byte. << 01 - End of Subrecord. Counted transfer complete. Enable serial << poll so that counted transfer command will be accepted in << outbound FIFO, put one data byte into outbound FIFO. << 10 - Count no End. Byte count exhausted. << 11 - DMA Error. This status should be set by aborting a DMA << transfer. Also: << S T E P 2 5 -- DMA Error and Abort Test << << The DMA enable flip-flop (DMAENF) is cleared by any of the following << signals: << 1. DMA abort (WREG 14) << 2. TIMEOUT DMA request timeout << 3. DMERR which is the OR of << a. ADROVF address rollover << b. PARERR memory parity error << c. MEMTIM memory timeout << 4. DMINT << 5. PONINCL << << NOTE: should also test clearing of error flags. << << DMASTAT is set to three whenever DMERR is asserted, or when DMAENF << is clear during any state except states 0, 1, 4, or 5. DMASTAT, << ADROVF, PARERR, MEMTIM, and TIMEOUT should all be cleared by CLRERR, << which is aserted by PONINCL or WREG11. Register 11 vs. Register 15 vs. OBSI Responses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Register 11 (DMA Control/Status) and Register 15 (Channel Service Information) are related in hardware. Writes to registers 11 and 15 are identical -- there is only one set of eight storage bits -- except that writes to register 11 additionally set the DMA Enable flip-flop. Reads from registers 11 and 15 are different, and while register 15 typically supplies the OBSI response, there are some differences. That is, reading register 15 and reading the OBSI response may not return the same information, as some of the values depend on the presence of the OBSI command on the IMB. The GIC asserts CSRQ to request service from the Channel Program Processor. There are several sources of channel requests, and the origin of the highest-priority request is reflected in the Channel Request, Device Request, and Device Number bits of the OBSI response. The CPP tests the validity of the response combination and will abort the channel program with an "Illegal CSRQ" indication if the response is not correct. In hardware, the internal MYCSRQ signal is asserted for a channel request. This signal is qualifed with the ~DIAG (SW5 not in the TEST position) signal and then split and qualified with the SW1 switch CPU/CPP positions to assert the CSRQ1 or CSRQ2 signals, respectively. Generation of MYCSRQ is qualified with the ~PFW (Power-Fail Warning) signal, which inhibits MYCSRQ when power is failing. The origin is the OR of the CHANRQ (Channel Request), DEVRQ (Device Request), and HPSRQ (HP Service Request) signals. HPSRQ is an AND of three signals, one of which (SRQB) is grounded on Revision D of the GIC PCA. So this term does not play a part in CSRQ assertion. (It appears that HPSRQ was used to generate a channel request when the PHI asserted the HP-IB SRQ signal. It was qualified with the Poll Enable signal and the +EO signal from the New Status encoder, which asserts only when the encoder is enabled but no New Status register bits are set. Revision C, date code 1830, was the last GIC revision to support this action.) The CHANRQ and DEVRQ signals are reflected in Register 15 bits 6 and 7, respectively, and the NOR of the signals is reflected in bit 8 (request not valid). Bits 13-15 (device number) of the register are multiplexed from three sources: the device number stored in from Register 11, the priority-encoded New Status register value, and the priority-encoded buffered and latched data output lines of the PHI. The device numbers in the latter two cases are simply ORed together and so depend on which encoder is enabled; if neither is, then the device number is read as 7. The CHANRQ line is also multiplexed, with the value being the DMRQEN signal for the first case and ground (i.e., denied) for the latter two cases. The selection of the multiplexer sources is controlled by the following equation (asserted = encoders, denied = DMA register): SELECTOR = (OBSIDOF + ~PHIINTBF) * (PHIDATAGS + ~PHIINTBF) * ~DMINT PHIINTBF.S = PHIINT * DMAINACT * ~OBSI PHIINTBF.R = ~PHIINT + ~DMAINACT OBSIDOF.D = PHIINT * DMAINACT * ATN * EOI * CIC * ~CSRQDIS OBSIDOF.C = OBSI OBSIDOF.R = ~DDOB PHIDATAGS = OBSIDOF (enabled) and one or more data lines asserted DMINT = DMA state machine requests an interrupt at completion or abort CSRQDIS = Inhibit CSRQ on a positive parallel poll response, i.e., poll responses will be ignored So in the absence of an active DMA interrupt or PHI interrupt, the selector asserts, passing the encoder device number and denying CHANRQ. Whereas the selector denies, passing the DMA device number and asserting CHANRQ, if a DMA interrupt is present, or if DMA is inactive and a PHI interrupt is present with an active poll response and the CSRQ disable bit clear. OBSIDOF pulses active only for the duration of the OBSI command, and then only for an uninhibited parallel poll. So if a PHI interrupt is present, a device request is asserted only if an active poll response is also present. If a poll is not present, then a PHI interrupt generates a channel request. In the absence of a PHI interrupt, a channel request is asserted only when a DMA interrupt is present. Because OBSIDOF is asserted only during an OBSI command, the response will be different from reading Register 15 directly if an active poll and PHI interrupt are present with no DMA interrupt pending. A direct read will have SELECTOR denied because both OBSIDOF and ~PHIINTBF are denied, so the result will obtain the device number from Register 11 and have CHANRQ asserted. An OBSI read will have SELECTOR asserted because OBSIDOF is asserted, so the device number will be obtained from the poll response priority encoder, and DEVRQ will be asserted. Note that a DMA abort, caused either by an Operation Timeout or by a write to Register 14, moves the state machine to the DMINT assertion state. The abort is detected by the two completion state flip-flops, DMASTATAF and DMASTATBF, being in the 1 1 state when DMINT is asserted. So: CHANRQ = ~SELECTOR * DMRQEN DMRQEN = (PHIINT + DMDIRIN) * ~DMOBSIF DMOBSIF.R = DMOFF DMOBSIF.D = DMINT DMOBSIF.C = ~OBSI (inhibits CSRQ after OBSI executed) So DMRQEN is asserted when DMIN (DMA direction is inbound) is asserted, or when PHIINT is asserted, and is then inhibited when the resulting OSBI is done. The idea is that an inbound DMA transfer asserts CSRQ as soon as the last byte is in, but an outbound transfer asserts CSRQ only when the PHI interrupts, presumably on a "FIFO Empty" condition. Note that in the first case, DMARQEN is asserted continuously, and the multiplexer is used to inhibit CSRQ generation until DMINT asserts to to switch the multiplexer source from the encoders to the DMA register. The DEVRQ signal asserts when the New Status encoder asserts its Group Status signal (enabled by ~NSEN assertion), or when the PHI data encoder asserts its Group Status signal (enabled by ~OBSIDOF assertion) with the ~OBSIDN signal asserted. Condition Request Device Source Indicator ----------------- ------- ------------------ ------------------------------- Operation timeout Channel Register 11 Bit 3 in Register F DMA abort Channel Register 11 Bit 4 in Register F DMA completion Channel Register 11 Bits 3-7 of Register 8 = 00101 PHI interrupt Channel Register 11 Bit 0 of Register B Parallel poll Device Poll encoder Bit 0 of Register B * ATN * EOI New Status Device New Status encoder (none) A PHI interrupt must occur with an active parallel poll response to assert DEVRQ. All other PHI interrupt conditions assert CHANRQ. Note that while there are six conditions that assert CSRQ, there are really only three sources: a DMA interrupt, a PHI interrupt, or the New Status encoder. An Operation Timeout asserts PHIINT, although in this case Register 2 will not show a PHI interrupt, presuming no other interrupting conditions exist. DMA Abort and DMA Completion assert DMINT; a timeout during a DMA transfer asserts both PHIINT and DMINT. A parallel poll response must be programmed to assert PHIINT before the poll response is recognized separately from other PHI interrupts. Channel vs. Device Request Priority ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ There are six sources that can assert CSRQ. The New Status priority encoder must be enabled by NSEN (New Status Enable) assertion in order to generate DEVRQ. NSEN terms include ATN, EOI, and ~OBSIDOF, meaning that a New Status request is honored only during a parallel poll (ATN * EOI) that does not result in a PHI poll response interrupt (OBSIDOF). An active poll response and accompanying PHI interrupt asserts OBSIDF, which enables the poll priority encoder. It also disables the New Status encoder, so a poll response preempts a New Status response. In the absence of a PHI or DMA interrupt, the request selection multiplexer is enabled for device requests. A DMA interrupt condition, either for completion, abort, or timeout, asserts DMINT, which enables the multiplexer for channel requests and asserts CHANRQ. A PHI interrupt without an active poll request also enables a channel request and so CHANRQ. Therefore, the request priorities, in decreasing order, are: DMA interrupt, poll PHI interrupt, non-poll PHI interrupt, and New Status (same as the table order in the preceding section). GIC Diagnostic Steps 33 to 35 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The GIC diagnostic tests the CSRQ logic. Step 33 tests device requests, Step 34 tests channel requests, and Step 35 tests the combined requests. The responses to a read of Register F and an OBSI command are verified. Diagnostic Step 33 tests DEVRQ under these input conditions: - Parallel poll response asserted - New Status active - Parallel poll active - PHI is CIC - DMA is busy - CSRQ is disabled The test matrix is as follows: Test #: 1 2 3 4 5 6 7 inputs: PHIDAT<>0 F T F NS<>0 F F T T T T T ATNEOID T T T F F F F CIC T T F F F DMABSY F T CSRQDIS F T ------------------------------ outputs: DEVRQ/RIOC F F T F T F F DEVRQ/OBSI F T F F T F F Device requests result in DEVRQ assertion, which is reflected in Register F bit 6. Step 33 begins with an INIT. It then sets Register 3 to 140377 to enable all PHI interrupts. An empty FIFO causes the PHI to assert its interrupt request line. Test 1 sets the PHI online and does an IFC to make the PHI the CIC. The PHI does a parallel poll. The GIC asserts CSRQ for the PHI interrupt. Trace reports PHI interrupt. The diagnostic verifies that DEVRQ is denied for both RIOC and OBSI reads. Expected RIOC: CHANRQ + Dev B. Expected OBSI: CHANRQ + Dev B. Test 2 sets PP 7 mask and sense to generate a PPR. Trace reports Poll response. The diagnostic verifies that DEVRQ is denied for RIOC and asserted for OBSI. Expected RIOC: CHANRQ + Reg B. Expected OBSI: DEVRQ + Dev 7. Test 3 clears the poll mask bit to inhibit the poll response, and it sets a New Status bit for device 0. Trace reports PHI interrupt + New Status change. The diagnostic verifies that DEVRQ is asserted for RIOC but not for OBSI. Expected RIOC: DEVRQ + CHANRQ + Dev B. Expected OBSI: CHANRQ + Dev B. Test 4 terminates the parallel poll by sending an uncounted transfer. Trace reports PHI interrupt. The diagnostic verifies that DEVRQ is denied for both RIOC and OBSI reads. Expected RIOC: CHANRQ + Dev B. Expected OBSI: CHANRQ + Dev B. Test 5 transfers control by executing a Take Control command. Trace reports PHI interrupt + New Status change. The diagnostic verifies that DEVRQ is asserted for RIOC (OBSI is not checked). Expected RIOC: DEVRQ + CHANRQ + Dev B. Expected OBSI: DEVRQ + CHANRQ + Dev B. Test 6 starts an inbound DMA transfer, clocks it out of State 0, and then aborts the transfer, leaving DMA busy. Trace reports DMA completion. The diagnostic verifies that DEVRQ is denied for both RIOC and OBSI reads. Expected RIOC: DMAABORT + CHANRQ + Reg B. Expected OBSI: DMAABORT + CHANRQ + Reg B. Test 7 sets the "Disable CSRQ for parallel polls" bit in Register F. Trace reports DMA completion. The diagnostic verifies that DEVRQ is denied for RIOC (OBSI is not checked). Expected RIOC: CHANRQ + Dev B. Expected OBSI: CHANRQ + Dev B. [NOTE: CHANRQ is inhibited because OBSI was seen in Test 6, but the DMA sequencer has not been clocked back to State 0. However, DMINT is still asserted, and so the multiplexer presents the device number from Register B/F, which is zero. The expected response shown in the the diagnostic comments, which is the idle response from the Parallel Poll and New Status register encoders, is wrong.] Diagnostic Step 34 tests CHANRQ under these input conditions: Test #: 1 2 3 4 5 inputs: DMINT F T T DMIN F T F PHIINT F F F T T ATNEOI T T PHIDATA<>0 F T ----------------------- outputs: CHANRQ/RIOC F T T T T CHANRQ/OBSI F T F T F Channel requests result in CHANRQ assertion, which is reflected in Register F bit 7. Step 34 begins with an INIT. It then sets Register 7 to set the PHI online and then offline. Test 1 verifies that CHANRQ is denied for both RIOC and OBSI. Expected RIOC: NOTVALID + Dev 7. Expected OBSI: NOTVALID + Dev 7. Test 2 starts an inbound DMA transfer, clocks it out of State 0, and then aborts the transfer, leaving DMA busy. Trace reports DMA completion. The diagnostic verifies that CHANRQ is asserted for both RIOC and OBSI. Expected RIOC: DMAABORT + CHANRQ + Reg B. Expected OBSI: DMAABORT + CHANRQ + Reg B. Test 3 does an INIT and then starts an outbound DMA transfer, clocks it out of State 0, and then aborts the transfer, leaving DMA busy. Trace reports (none). The diagnostic verifies that CHANRQ is denied for OBSI (RIOC is not checked). Expected RIOC: DMAABORT + CHANRQ + Reg B. Expected OBSI: DMAABORT + NOTVALID + Reg B. Test 4 sets the PHI online and does an IFC to make the PHI the CIC. The PHI does a parallel poll. The GIC asserts CSRQ for the PHI interrupt (empty FIFO). Trace reports PHI interrupt. The diagnostic verifies that DEVRQ is denied for both RIOC and OBSI reads. Expected RIOC: CHANRQ + Dev B. Expected OBSI: CHANRQ + Dev B. Test 5 sets PP 7 mask and sense to generate a PPR. Trace reports Poll response + PHI interrupt. Diag verifies that CHANRQ is asserted for RIOC and denied for OBSI. Expected RIOC: CHANRQ + Reg B. Expected OBSI: DEVRQ + Dev 7. -------------- GIC Diagnostic -------------- Sections 1-17 and 19-25 pass. Section 18 tests memory parity error detection (needs FLI) - Step 93 tests parity error during DMA writes 000000 to 00.147777 (PSTA) then executes CIO with RA = 004000 and DEVNO = 2 (FLI, disable write ECC) then writes 000003 to 00.147777 (PSTA) to set bad "parity" then executes CIO with RA = 100000 and DEVNO = 2 (FLI, master clear) then runs diag test then rewrites 00.147777 with proper parity See 30000-90143 (SIII R/T Manual) pp. 250 for FLI programming. -------------------- CS/80 Device Support -------------------- MPE-V/R supports these CS/80 drives only: Drive Subtype Driver ----- ------- --------------- 7933 8 HIOMDSC2 type 3 However, the 7911 (subtype 1) and 7912 (subtype 2) appear to have driver support. Option 140 is needed to delete the standard cartridge tape drive from the 7911A and 7912A disc drives. Driver HIOCTAPE0, which is used with the integrated cartridge tape drives, is not provided with MPE-V/R. MPE-V/E supports these CS/80 drives only: Drive Subtype Driver ----- ------- --------------- 7911 1 HIOMDSC2 type 3 7912 2 7914 4 7933 8 7935 8 7936 9 7937 10 7945A 5 7957A 11 7958A 12 7957B 13 7958B 14 7959B 15 7961B 13 7962B 14 7963B 15 9140A 0 HIOCTAP0 type 3 9144A 3 HIOCTAP1 type 3 9145A 0 HIOCTAP3 type 4 35401 6 HIOCTAP2 type 3 The 7911A, 7912A, and 7914A are supported only with option 140 to delete the integrated cartridge tape drive, or with option 001 to provide a separate HP-IB controller and port for the CTD. The standard configuration, where the CTD is unit 1 on the same HP-IB port, is not supported (probably due to GIC contention). ---------------- CS/80 Diagnostic ---------------- The CS80DIAG program is written in AID and runs under DUS-III. It is documented in 30070-60068 Volume I March 1982 (PDF pages 505-end) and December 1983 (PDF pages 509-end). Test 6 of this program provides the CS/80 External Exerciser. The other test sections exercise the GIC registers and some CS/80 device interactions. The version included with DUS-III is 0.11. Unit selection for multi-unit devices is buggy (it compares a user input of the unit number with the unit bitmap returned by DESCRIBE). This is fixed in version 0.16 that is included with DUS version 3.06 (Rev. 2913), However, the newer version dated 7/26/86 announces on startup: ************************************************ * NOTICE * * WITH REVISION 0.16 THE FOLLOWING SUPPORT * * CHANGES WERE MADE: * * * * TESTS 1-4 SUPPORTED * * TEST 5 NOT SUPPORTED * * TEST 6 NOT SUPPORTED * * * * #### NOTE: FOR TEST 6 USE CS80EXER #### * * * ************************************************ Test 5 is the "System Type Test" that tests common system operations. The manual says, "The system tests will execute all CS/80 commands applicable to the device except Initialize Media and Spare Block. The functionality of each command is tested as thoroughly as possible...." -------------------------- The Interrupt Mask Mystery -------------------------- Most HP 3000 interface cards contain an "interrupt mask flip-flop" that, when cleared, inhibits the card from asserting an interrupt request to the CPU. A few cards do not -- the system clock and selector channel maintenance board, for example. For these cards, interrupts cannot be masked. Mask flip-flops may be set or cleared by executing an SMSK instruction, which presents the associated "mask word" on the data lines of the interface card and asserts a "set mask" command to the card. Each 1-bit in the mask word sets a corresponding mask flip-flop, enabling interrupts for the card hosting it. 0-bits in the mask word clear the respective mask flip-flops. The SMSK instruction also stores the mask word in absolute location 7, and the word can be read by the complementary RMSK instruction. There is no provision for reading the states of the individual mask flip-flops. On the SIO machines, each interface contains a set of jumpers that assign the mask flip-flop to one of 16 possible "mask groups" that correspond to the 16 bits of the mask word. Assignments are arbitrary, and more than one card may be assigned to the same group. Therefore, SMSK enables or disables interrupting capability for groups of cards. The jumpers also include "always enabled" and "always disabled" positions to control the mask flip-flop independently of the SMSK instructions. Mask flip-flops are preset when the I/O system is cleared, so all cards are initially enabled to interrupt. Presumably the original MPE running on the 3000 CX machines used interrupt masking. It is unclear when this capability was removed, but the interrupt mask jumper "...must be set to the ENABLE position in all Series III systems." Indeed, the source for MPE V shows that SMSK and RMSK are never executed on these systems. For the HP-IB machines, the GIC and ADCC also contain mask flip-flops, as well as SMSK and RMSK instructions. Rather than using jumpers to control the mask flip-flop addressing, these machines uses the interface card's channel number. So an individual mask flip-flop responds to the mask word bit corresponding to the configured channel number. Another difference is that clearing the I/O system resets all of the mask flip-flops, preventing all cards from interrupting. SMSK and RMSK are issued in the MPE HARDRES module for HP-IB systems as part of interrupt handling. Presumably, this is to implement proper interrupt priority. On the SIO systems, interrupt priority is established by the daisy-chain connection of the INTPOLLIN and INTPOLLOUT signals cable. Hardware associated with the Interrupt Active flip-flop on these interfaces blocks the poll signal at an active interface, preventing lower-priority cards from asserting INTREQ while the blocking card's Interrupt Active flip-flop is set. This still allows higher-priority cards to interrupt a lower-priority service routine. For the HP-IB machines, this daisy-chain has been eliminated. For concurrent interrupts, priority is established by the responses to an OBII (Obtain Interrupt Information) command. Each interrupting interface asserts the bit that corresponds to its channel address, and the lowest address (highest bit in the response word) is selected for service. After the interrupt request is cleared on the highest-priority interface, however, the lower-priority request still persists. Were it allowed to interrupt, then the higher-priority service routine would be preempted. To prevent this, the interrupt mask is used to clear the mask flip-flops of all interfaces of lower priority than the one being serviced. As with the SIO daisy-chain, this still permits higher-priority interfaces to interrupt. The HP 300 Architecture Guide, page 4-29 (PDF page 86) says: "A 16 bit mask is provided for the purpose of masking off different channels. It is the responsibility of the interrupt handler, using the SMSK instruction, to clear the mask bits of the channels it wishes to deny interrupt capabilities before enabling the interrupt system with ION." On page 4-30, it also notes that after fetching the interrupt handler program label, "The status register is set to privileged mode, external interrupts disabled." The "mystery" comes with the behavior of the Starfish. While the GIC will respond to a SMSK bus command, the Starfish command set does not include an HP-IB SMSK instruction. The command can be issued indirectly via a WIOC command, but it does not appear that MPE V/R issues such a command. Yet clearly SOMETHING must do so; otherwise, the GIC could never interrupt after the initial power-on reset. Actually, the situation is even worse. The cold-load sequence issues an IOCL (I/O Clear) command shortly before INITIAL completes and calls the dispatcher to begin MPE operation. IOCL performs a hardware-clear of all interrupt mask bits. Also, INITIAL issues an INIT (I/O Initialize) command prior starting each channel program that sends read or write commands to the disc. INIT performs a hardware clear on the selected channel's mask flip-flop. The mystery is: by what mechanism is the interrupt mask reenabled? For the Starfish at least, it appears that INIT and IOCL issue SMSK IMB commands to set the specified channel or all channel (respectively) interrupt mask bits on. ------------- IOCL vs. INIT ------------- While the INIT instruction is documented in the Machine Instruction Set manual and is present in the Series 68 microcode manual, the IOCL instruction is not. The HP 300 Architecture Guide says that IOCL is not an instruction but rather is a "special I/O function" that "...is executed by first issuing a SMSK to all zeros, then loading %120000 in S-1 and zero in S and issuing a WIOC instruction." It then follows with a list of actions that is identical to the INIT instruction, except that "Clearing the 4th word of every DRT entry for this channel" is omitted. The problem with this description is that issuing a WIOC does none of those things -- all that occurs is that the IOCL command is asserted on the IMB. The action list is performed by the INIT microcode, which involves setting up the PHI on the GIC after is it cleared and idled by the reset that occurs as a result of the INIT and IOCL IMB commands (and the power-on clear). Moreover, as MPE issues an IOCL during INITIAL and then expects the GIC(s) to be responsive, skipping the PHI setup prevents the system from coming up. Further, a comment in INITIAL says, "RESETSTARFISH ZEROES THE LAST WORD OF EVERY DRT ON THE GIC CHANNEL." The RESETSTARFISH procedure does an IOCL (code = 5). So it appears that IOCL, at least the Starfish variety, essentially performs an INIT on each channel that responds to a roll call. Also, IOCL must also enable interrupts, because if it doesn't, then MPE won't boot after the IOCL. ---------------- MPE-V/E Firmware ---------------- The "HP 3000 Software Update Manual Version G.01.03 of MPE V/E (T-Delta-3)" manual, 32033-90036 Nov-1985, says in part: As you know, we have been offering MPE V/P-based and MPE V/E-based operating systems on current HP3000 systems. [...] Since we believe that quality and expandability of MPE V/E will provide you with the best foundation for meeting your future computing needs, all HP3000 installations with MPE V/P or MPE V/E-based support contracts are receiving T-Delta-3. If your system is currently running on an MPE V/P-based software release, you may update to T-Delta-3 when you feel that it is appropriate. For Series 39,40,42, 44, and 48 systems, we will continue to support your old firmware after you update to T-Delta-3 or any other MPE V/E-based software release. When you do decide to order the new firmware, you will be able to take full advantage of the added expandability which MPE V/E has to offer. That clearly states that MPE-V/E will run without the expanded CST firmware. ---------------- HIOP Instruction ---------------- The HP 300 manual says that the logic is: if DRT3 (0..1) = 00 then CC := CCE else if DRT3 (0) = 1 then if DRT3 (1) = 1 then DRT3 (15) := 1 end if DRT3 (0..1) := 01 IMB_Write (HIOP) end if if DRT3 (15) = 0 then CC := CCG else CC := CCE end if end if This bases the decision on bits 0, 1, and 15 of DRT3: Initial Condition Old New CCA IMB New Condition --------- --- --- --- ---- --------------------- Stopped 00x 00x CCE -- Stopped (no change) Stopping 010 010 CCG -- Stopping (no change) Stop-wait 011 011 CCE -- Stopping (no change) Running 100 010 CCG HIOP Stopping at next WAIT Run-wait 101 011 CCE HIOP Stopping Starting 11x 011 CCE HIOP Stopping ==== ADCC ==== The Series 33 ADCC driver is HIOTERM0, S26S033C.SPL ADCCDIAG ~~~~~~~~ The ADCC diagnostic is ADCCDIAG, S20S231A.SPL. The program is written in SPL-II and so requires the SPL-II compiler. SPL-II apparently uses the same :FILE equations as SPL, i.e., SPLTEXT, SPLLIST, SPLUSL, etc. Running under SDUPII ~~~~~~~~~~~~~~~~~~~~ The diagnostic is designed to run under DUS. It might be able to run under DUS-III, although I cannot verify this, because the library and tools needed to create a DUS-III tape with the diagnostic added are not available. So the next best thing might be to run it under SDUPII. But that requires the addition of shims to handle the externals provided by DUS that aren't available with SDUPII. The SDUPII global procedures are documented in "Stand-Alone Diagnostic Utility Program II (SDUP II)" (03000-90125 March 1977) from Bitsavers. It should be possible to produce a "Type 2" (stand-alone I/O) tape with ADCCDIAG that can be cold-loaded on the Series III. The externals called by the diagnostic are: - PROCEDURE CLEAROFFLINE; - PROCEDURE CRLF; - LOGICAL PROCEDURE GETIO(N); VALUE INTEGER N; - PROCEDURE IIX'TIMER(TIMES); VALUE LOGICAL TIMES; - PROCEDURE PRINT(MSG,LEN,CNTL); BYTE ARRAY MSG; VALUE INTEGER LEN,CNTL; - INTEGER PROCEDURE READ(MSG,MAXLEN); BYTE ARRAY MSG; VALUE INTEGER MAXLEN; - PROCEDURE SETOFFLINE; - PROCEDURE STARTIDLE; All of the routines are in S05S231A.SPL, module SAD. The only comparable procedures in SDUPII are "PUT" for "PRINT" and "GET" for "READ". ADCCDIAG BUG ~~~~~~~~~~~~ ADCCDIAG step 14 has this line of code: DO'WIOC0(4040+DEV); <
> 12590000 It should be: DO'WIOC0(!4040+DEV); <
> 12590000 i.e., the constant should be hexidecimal, not decimal! === AID === The AID diagnostic language has a few bugs and one behavior that causes problems with the 7970 diagnostic. BUG: The LOCATE command does not work in version 1.01 (DUS-III). It is fixed in version 2.00. BUG: The COPY command does not work in version 1.01 (DUS-III). It is fixed in version 2.01. BUG: The HIOP command may report an "Interrupt from Illegal Device" and terminate the program. Appearance of the bug depends on exactly where the CPP is in the channel program when the HIOP is executed. When AID encounters the HIOP command, it executes an HIOP instruction but also marks the device to reject any further interrupts. The problem is that if the HIOP occurs in the middle of a data transfer, the channel will not halt until the transfer is complete and the channel program reaches the following WAIT instruction. If this occurs, HIOP returns CCG to indicate that the program will halt later, and when it does halt, an interrupt request is asserted. But because the HIOP executor has marked the device as "finished," the interrupt causes an AID error, "Interrupt from Illegal Device." This error has been reproduced on a Series 37, so it is not a simulator fault. A workaround is to clear the "bad interrupt" reserved variable that causes the AID error with a "LET BADINTP:=0" statement after the HIOP command. This bug appears in Step 305 of the D7970S13 diagnostic. BEHAVIOR: The S parameter (wait for status) sets bit 15 of the WAIT channel instruction for versions up to 2.00 and bit 13 for versions 2.00 and after. The difference is due to the Series 3x and Series 4x microcode using different bits for the S option. BEHAVIOR: A channel program that uses the same variable in more than one DSJ or RREG instruction will save only the value from the last one defined in the program. Because these instructions initialize their return locations to -1, if the last one is not executed, then the value will always be -1 when the program completes. For example: 10 LET CHANNEL:=11,DEVICE:=0 20 BSIO ZZ 30 RREG 2,X 40 JUMP 60 50 RREG 2,X 60 IN H 70 RSIO 80 PRINT X 90 END This program always prints -1. The reason is that AID builds a table of program locations that contain return values from the DSJ and/or RREG instructions, and this table is used to copy the values into their respective variables after the program terminates. In the above case, the table has two entries: one for statement 30 and one for statement 50. When the program ends, AID reads the table, copies the value returned from the RREG in statement 30 to variable X, and then copies the value returned from statement 50 to variable X also. Because statement 50 was never executed, the value copied from the instruction (-1) overwrites the value obtained by statement 30. The actual execution order of the instructions is irrelevant, as the table is built in linear sequence before execution occurs. The bottom line is that each program can contain only one reference to a given variable, as only the value from the final sequential instruction will be retained.