HP 3000 Hardware Notes ====================== IMPORTANT: the 3000 numbers bits with 0 = MSB and 15 = LSB. This convention carries over to the schematics, so SIGNAL0 is MSB and SIGNAL15 is LSB (e.g.). The HP 3000 Series III hardware consists of: - CPU - I/O Processor (IOP) and IOP Bus - Multiplexer Channel and MUX Bus supporting 16 controllers - Selector Channel and SEL Bus supporting 8 controllers - Device Controllers - Interconnection Buses (Central Data Bus, IOP Bus, Multiplexer Channel Bus, and Selector Channel Bus). The system console is connected to a dedicated card (30031A System Clock/Console Interface) on the original 3000, CX, and Series I. On the Series II and III, the console is connected to port 0 of the first ATC, and a dedicated clock card (30135A System Clock/Fault Logging Interface) is used (per the "HP 3000 Computer Systems Price/Configuration Guide", 5953-0538, Dec-1977). ============================ Series III Central Processor ============================ The CPU is a microcoded 16-bit machine. Four microcode addresses are reserved: 0 = unimplemented instruction (microcode wraparound) 1 = power-up 2 = CPU reset 3 = interrupt Jumps to locations 1-3 are performed by hardware mapping. The jump to location 0 occurs when microcode execution wraps around from the end of ROM. The ROM address is forced to location 1 when the system powers up and to location 2 when the -CPURST signal is asserted. The address is forced to location 3 in two cases: - when the NEXT micro-order is executed, and an interrupt is asserted - when the -JBNDV signal is asserted (-JBNDV is asserted when a UBNT or BNDT micro-order is executed, and the test value exceeds the bound value). Interrupts are recognized when the current instruction ends with the NEXT micro-order. Certain long instructions, e.g., MOVE, test for interrupts during instruction execution and jump explicitly to location 3000 (IRD) if one is pending. Instruction resumption is ensured by decrementing P to point at the current instruction and updating the address and count parameters on the stack for the progress so far. --------- Microcode --------- The micromachine is controlled by a lookup table and control store. The LUT contains 256 20-bit words, divided into a 12-bit address and an 8-bit control bus. It is located on the CIR PCA (30003-60006) and is physically constructed of five 256 x 4-bit PROMs (Am27S21?), as follows: Desig Function ----- ----------------- U165 VBUS 4-7 U175 VBUS 8-11 U185 VBUS 12-15 U145 SRP0-SRP3, Z U155 PC0, PC1, W, JLUI LUT ROM addresses are driven by a mapper that derives the LUT entry from the machine instruction. The LUT ROMs may not be socketed. The control store contains 4096 32-bit words. It is located on the ROM PCA (30003-60021) and consists of 64 512 x 4-bit PROMs (Am27S13?). The control store ROMs should be socketed. The microinstruction format is shown on page 5-4 of the HP 3000 Series III Reference/Training Manual (30000-90143). More decoding information is shown on page 4-03 of the HP 3000 Series II System Microprogram Listing (30000-90023). There appear to be five instruction types; the type is determined by the contents of the Function field (bits 10-14) and one bit of the Skip field (bit 15), as follows: Typ Function D15 RBUS SBUS FUNC SHFT STOR SPEC SKIP --- ------------------ --- ---------------------------------- I REPN - ** ** REPN ** ** ** nn II other - ** ** ** ** ** ** ** III JMP/JSB - nop ** Jxx LABL ** nop ** IV ROM/ROMI/ROMX/ROMN 0 nop ** ROMx nop ** nnnn ** V ROM/ROMI/ROMX/ROMN 1 nop ** ROMx nop ** nnnnnn nop In addition, if RBR is coded in the SBUS field, or BSP1, BSP0, SBR, or BUS is coded in the STOR field, then the SPEC field contains MCU micro-orders instead of SPEC micro-orders. Microprograms may contain subroutines. There is a single subroutine return address register (the "Save Register"). It is loaded by a JSB micro-order with the contents of the RAR (ROM Address Register). When an RSB micro-order is executed, the Save Register is loaded back into the RAR to return from the subroutine. An important point of the design is that the Save Register is effectively disabled by a NEXT micro-order, rather than cleared as in the HP 1000. A Subroutine Flag flip-flop is cleared by NEXT or a bounds violation and set by JSB. RSB reloads the RAR from the Save Register only if the Subroutine Flag is set. So encountering an RSB without a preceding JSB results in execution continuing inline. There are a number of instances in the system microcode that take advantage of this behavior. Note, though, that RSB does not clear the Subroutine Flag flip-flop, so executing a second RSB without an intervening JSB will return to the last JSB's return location. ----------------- Machine Registers ----------------- In addition to the programmer-visible registers, there are four scratch-pad registers (SP0-SP3) available to the microprogrammer. ----------------- Instruction Fetch ----------------- A two-stage instruction pipeline is used. The current instruction is decoded from the Current Instruction Register (CIR), while the next sequential instruction is loaded into the Next Instruction Register (NIR). The NEXT micro-order terminates the current microinstruction sequence and initiates an instruction fetch. If the first of two stack operations is finishing, the second stack operation is performed, and P is unchanged. Otherwise, the P register value is loaded into the ACOR (memory address) register and a memory read is started, the NIR is loaded into the CIR, and P is incremented. When the read completes during execution of the current instruction, the DCOR (memory data) is loaded into the NIR. Therefore, while an instruction is being executed, P points at the instruction beyond the next instruction, i.e., two locations ahead of the current instruction. When the machine is halted or an interrupt occurs, P is decremented to point at the next instruction. If the machine is halted, pressing RUN loads P into ACOR and initiates a memory read. The resulting data is stored in the NIR, P is incremented, and a NEXT micro-order is executed to begin executing instructions. -------------------- Instruction Decoding -------------------- The sixteen bits of the CIR drive the mapper (eight '151 8-to-1 multiplexers) to produce an eight-bit address for the LUT ROMs. Twelve bits from the LUT output provide the starting microcode address to the RAR. Not all LUT addresses are used; unused entries load the RAR with address 7777. This causes a wraparound when the next microinstruction is executed, resulting in an Unimplemented Instruction trap. The mapping is quite complex. Short of simulating the logic (perhaps in PLPL) and driving all possible values, the opcodes that result in unused LUT addresses are not obvious. However, based on information in the Machine Instruction Set manual, initial decoding is based on the four MSBs, and most instructions are fully decoded. These instructions directly cause Unimplemented Instruction traps via transfers to ROM address 7777 (the transfer source is shown in parentheses): - subopcode 00, stack op 72 (LUT 372) - subopcode 03, immediate op 14 (LUT 234) - opcodes 020400-020407 (ROM 3400-3403) - opcodes 020416-020417 (ROM 3407) - opcodes 020560-020567 (ROM 3470-3473) - opcodes 020572-020577 (ROM 3475-3477) - opcode 020600 (EIS ROM 12360) - opcodes 020615-020617 (EIS ROM 12375-12377) - opcodes 020400-020777 if optional firmware is absent (ROM 1613) (One odd condition is that opcodes 020560/01 execute as DMUL/DDIV if F3 is set. However, NEXT clears F3, so I don't see how this works; maintenance panel, maybe?) The remaining instructions are only partially decoded. None result in Unimplemented Instruction traps. Decoding is as follows: Subop Notes Inst Reserved Defined As Decoded As ----- ----- ---- -------- ----------- ----------- 01 SCAN 10-15 0 0 0 0 0 0 x x x x x x 01 TNSL 10-15 0 0 0 0 0 0 x x x x x x 02 MOVE 12-13 0 0 x x 02 MVB 12-13 0 0 x x 02 MVBL 13 0 x 02 SCW 13 0 x 02 MVLB 13 0 x 02 SCU 13 0 x 02 CMPB 12-13 0 0 x x 02 RSW 12-14 0 0 0 x x x 02 LLSH 12-14 0 0 0 x x x 02 PLDA 12-14 0 0 0 x x x 02 PSTA 12-14 0 0 0 x x x 02 LSEA 12-13 0 0 x x 02 SSEA 12-13 0 0 x x 02 LDEA 12-13 0 0 x x 02 SDEA 12-13 0 0 x x 02 1 IXIT 12-13 0 0 0 0 02 1,2 LOCK 12-13 0 0 n n 02 1 PCN 12-13 0 0 n n 02 1,2 UNLK 12-13 0 0 n n 03 PAUS 12-15 0 0 0 0 x x x x 03 3 SED 12-14 0 0 0 x x x 03 4 XCHD 12-13 0 0 0 0 03 4 PSDB 12-13 0 0 n n 03 4 DISP 12-13 0 0 n n 03 4 PSEB 12-13 0 0 n n 03 5 SMSK 12-14 0 0 0 0 0 0 03 5 SCLK 12-14 0 0 0 n n n 03 5 RMSK 12-14 0 0 0 0 0 0 03 5 RCLK 12-14 0 0 0 n n n 1. For bits 12-15, IXIT = 0000, PCN = nnn0, LOCK = nn01, and UNLK = nn11. 2. Presumably, 020361 LOCK and 020363 UNLK cause Unimplemented Instruction traps on non-Series II systems, though we'd need a Series III microcode listing to be certain. 3. SED only works correctly if opcodes 030040 and 030041 are used. Opcodes 030042-030057 also decode as SED, but the status register is set improperly (the I bit is cleared, bits 12-15 are rotated right twice and then ORed into the status register). 4. For bits 12-15, XCHD = 0000, DISP = nnn0, PSDB = nn01, and PSEB = nn11. 5. For bits 12-15, SMSK and RMSK = 0000, SCLK and SMSK = nnnn. Key: x = 0 or 1, n = any collective value other than 0. The extended instructions also decode partially, as follows: Opcode Notes Inst Reserved Defined As Decoded As ------ ----- ---- -------- ----------- ----------- 020601 DMPY 9-11 0 0 0 x x x 020602 7 CVAD 9-10 0 0 x x 020604 7 CVBD 9-10 0 0 x x 020605 7 CVDB 9-10 0 0 x x 020606 8 SLD 9 0 x 020607 8 NSLD 9 0 x 020610 8 SRD 9 0 x 020611 8 ADDD 9 0 x 020612 8 CMPD 9 0 x 020613 8 SUBD 9 0 x 020614 8 MPYD 9 0 x 7. Bit 11 is the S decrement field (0-1). 8. Bits 10-11 are the S decrement field, which decode as follows: 00 = delete no parameters, 01 = delete two parameters, 10 = delete four parameters, 11 = undefined but decodes as delete four parameters. ------------------------ Stack Register Preadjust ------------------------ Instructions that reference any of the top four locations of the stack are microcoded to use the stack registers RA-RD, which must contain the associated values before execution of the instructions may begin. Each instruction specifies a two's complement stack register preadjust count in bits 0-2 (SP0-SP2) of the lookup table ROM that indicates the number of valid TOS registers required for the instruction. The count is fed to a four-bit adder (74283, U156 on CIR sheet 1 at grid D8) that sums the negative preadjust count with the current SR contents to obtain the difference, which represents the number of values that must be moved from memory into TOS registers before the instruction may execute. If register moves are not required, the LUT-to-V buffer at B7-C7 passes the instruction starting ROM address to begin microcode execution. However, if register moves are required, the SRP-to-V buffer at D10-E10 generates a microcode ROM address of 20, 24, 30, or 34, corresponding to four, three, two, or one register move(s) required. Microcode at those addresses accomplishes the moves before executing a JLUI skip micro-order to jump to the instruction's starting ROM address. Note: the register moving microcode checks for stack underflow (i.e., SM < DB and non-privileged) only after all of the moves have been accomplished, rather than after each move. The abort occurs before the last value is moved to the TOS, SR has been incremented, and SM has been decremented. -------- Preadder -------- Many instructions include offsets or counts within the instruction words. For example, memory reference instructions include displacements, shift instructions include shift counts, etc. For memory reference instructions in particular, the effective address calculations involve summing a base register, an offset, and possibly an index register value. To improve execution speed, a preadder is implemented that sums the offset contained in certain bits of the CIR with the index register (if enabled). The primary use is to save a microinstruction cycle during memory reference instructions, which must add a base register, the offset in the CIR, and potentially the X register (either directly or shifted left or right by one place for LDD/STD or LDB/STB, respectively). The preadder also serves to hold other counts obtained from the CIR, e.g., shift counts, although in these cases, the addition function is not used. The preadder consists of four '181 ALUs (U51, U31, U151, and U171 on R-Bus sheet 1 locations B4-D4) with the MODE pins wired low for arithmetic functions, and a '182 Look-Ahead Carry Generator (U181 at E4). The A-Bus is driven by eight '153 Dual 4-to-1 Line Multiplexers (U23, U24, U33, U34, U153, U154, U163, and U164 at B5-D6). The multiplexers present the values X, X/2 (logical), X*2, or 0 from the X register, as determined by the PADDXS0 and PADDXS1 signals, and are enabled by the ~PADDX signal. The ALU B-Bus is tied low for the upper byte and driven by the PADDIN and CIR signals for the lower byte. One of two functions is selected by the PADDSUB signal: A + B if low, and A - B if high. The outputs of the preadder may be placed on the R-Bus or S-Bus by octal buffers U45 and U145 or U46 and U144, respectively. The comments for the LUT entries for the memory reference instructions (subopcodes 04-17) say, "PADD, BASE FORCED ON FIRST LINE OF MICROCODE DURING NEXT+1 CYCLE" (Microcode, p8). The corresponding offset calculation microcode (e.g., AC1S on p 20) says, "IF ENTERED AT AC1S, SBUS=SM- RBUS=PADD+(XC IF NOT INDR)," and "IF ENTERED AT AC1D, SBUS=DB+ OR Q+- RBUS=PADD+(XC IF NOT INDR) INSTEAD OF SR=>SBUS." The first line of microcode at AC1S or AC1P simply has "ADD", and the first line at AC1D has "SR UBUS ADD...." The hardware to substitute PADD for the R-bus function and P/Q/DB/SM for the S-bus function consists of buffers U133 and U124 on page 2 of the ROM schematic (center right edge) and buffer U178 on page 1 of the R-Bus schematic at F4-G4. The former send the associated ROR bit fields to the R- and S-Bus field decoders and are disabled by ~NXTG (NXTG = NXT+1 * MEMREF). The latter substitute 04 (PADD) and 2x (P/Q/DB/SM, as derived from the associated CIR bits) to the field decoders and are enabled by ~NXTG. One important point is that the P value obtained from the S-Bus on entry points at the next instruction (i.e., P+1), whereas the P value obtained from an explicit S-Bus field reference points at the instruction following the next instruction (P+2). This is because the P register increment that occurs as part of a NEXT micro-order is coincident with the R-Bus and S-Bus register loads; both operations occur at NXT+1. Therefore, the microcode handling P-relative memory reference address resolution subtracts one to get the P value corresponding to the CIR, whereas branches on overflow, carry, etc. subtract two. ------------ Front Panel ------------ The front panel consists of two 16-bit displays, one 16-bit momentary push- button switch bank, two status LEDs, and two two-position momentary push-button switches, as follows: - Current Instruction Register display - System Switch Register display - System Switch Register switch bank - System Halt status - Run status - LOAD and DUMP switch - RUN/HALT and ENABLE switch The CIR display is simply a buffer/driver of the CIR register output lines from the CIR PCA. Therefore, for the microdiagnostics to display values in the CIR, some handwaving is required: - a "BUS NIR" micro-order stores the U-Bus into the NIR during the next "select" cycle ("NIR" stores U-Bus to DCOR, then DCOR to NIR) - bit 8 (%000200) in CCPX sets the "NIRTOCIR" bit, clocking NIR to CIR - a "REPC" and "PNLR TEST" loops until the RUN/HALT switch is pressed Note that this is only possible from microcode, as any normal instruction fetch would overwrite the CIR (and hence change the display). The System Switch Register consists of latches on the front panel PCA that follow the action of the associated (set/clear) switches. The latches are read onto the SBUS by the SWCH micro-order. The System Halt and Run lights are driven via buffers from the System Halt and Run flip-flops, respectively. The LOAD and DUMP switches assert the -LDSW and -DUMPSW signals, which are reflected in bits 2 and 1 of the CPX2 register, respectively. In addition, the LOAD switch asserts the -CPURSTSW and -IORSTSW signals, and the DUMP switch asserts -IORSTSW only. -CPURSTSW and -IORSTSW are synchronized with the system clock to become -CPURST and -IORESET; a power-on condition pulses both of these signals. The ENABLE switch develops a local signal to qualify the LOAD and DUMP switch signals. It is not transmitted externally. The RUN/HALT switch asserts the -RUNSW signal which is reflected in bit 0 of the CPX2 register. The rear of the front panel consists of two two-position toggle switches, one momentary toggle switch, and two 8-bit jumper blocks, as follows: - Power-Fail Auto-Restart Enabled/Disabled switch - Front Panel Enabled/Disabled switch - CPU Reset switch - DUMP switch register preset for the I/O control byte - DUMP switch register preset for the I/O device number The Power-Fail Auto-Restart switch position determines whether the CPU will halt (disabled) or automatically restart (enabled) when power is applied after a power failure. The Front Panel switch position determines whether the LOAD, DUMP, and RUN/HALT switches are inhibited (disabled) or operational (enabled). The CPU Reset switch asserts the -CPURSTSW signal to initialize the CPU. The System Halt flip-flop set output inhibits recognition of the RUN switch. Toggling CPU Reset is required to clear a system halt condition. The dump control and device numbers are normally set to 4 (Write Record) and 6 (magnetic tape DRT number), respectively. The -DUMPSW signal causes these values to be loaded into the System Switch Register and to appear on the front panel LEDs (per 30000-90013 page 5-32). ----------------- Illegal Addresses ----------------- A switch (S3) on the S-Bus PCA is set to the installed memory size. The switch setting is encoded into a 3-bit number and then compared to the bank address supplied when the ACOR is set. If the address is greater than the installed memory, the Illegal Address bit in CPX1 is set, causing an interrupt. Reading from non-existent memory returns an all-zeros word. Writing to non-existent memory is ignored. [confirm? uc p232 says "The bus transmission for this attempt is inhibited."] --------------- Bounds Checking --------------- Bounds checking is performed explicitly in microcode. A BNDT function field code subtracts the S-Bus value from the R-Bus value; if the result is negative, a bounds violation occurs. If the CPU is not in privileged mode, a bounds violation causes an immediate microcode jump to address 3. The UBNT function field code operates the same as BNDT, except that the microcode jump to location 3 for a bounds violation is not conditional upon the mode. The bounds violation microcode is invoked directly via an explicit JMP to label BNDV in three cases: 1. 2131 (MB26): MVBW bounds violation 2. 2220 (GSCB): SCU and SCW bounds violations 3. 2446 (SXIT): SXIT bounds violation (R < PB or > PL) These are explicit jumps, whereas BNDT/UBNT are implicit via IRQ. There does not appear to be any bounds checking on the next instruction fetch (i.e., P increment). All instructions that modify P, e.g., branches or PB-relative data accesses, do check that P remains between PB and PL. But it appears that a program could execute instructions and "run on" above PL. MPE doesn't seem to place any sort of "guard instruction" at PL+1 to catch this situation. (Something as simple as a BR * at PL+1 would cause a bounds violation interrupt.) Note that on page 10-2 of the tables manual, 32033-90147, under "Program File Format", there appears this note: S = Segment STT format: 0 = old format; 1 = new (extended) format ...implying that the STT format changed at some point (perhaps for MPE-V/E?). The STT is documented only in the SRM. For program accesses, EA < PB or EA > PL causes a bounds violation trap. For data accesses, EA < DL or EA > SM causes a bounds violation trap if the CPU is not in privileged mode. For stack accesses, SM < DB causes a stack underflow trap if the CPU is not in privileged mode. SM > Z causes a stack overflow trap regardless of mode. SM points at the TOS word in memory. ----------------- Overflow Checking ----------------- Integer overflow is detected in hardware and sets the O bit in the status register if enabled in microcode (by the ADDO, CADO, INCO, and SUBO micro-orders). Overflow is also set explicitly by the SOV micro-order. In either case, if the T bit in the status register is also set, CPX1.0 sets, and an interrupt occurs when the NEXT micro-order is executed. Interrupts are checked on the clock cycle following the execution of "NEXT" in RANK2. Therefore, a line of microcode containing "SOV NEXT" will cause an interrupt if the T bit is set. Replacing SOV with CLO would prevent an overflow interrupt. One explicit microcode check is made for integer overflow at FIX4 (1247) for the FIX instruction. The handler checks the T bit. If it's set, overflow is cleared, and the trap handler is entered. If it's clear, the O bit is set, and execution resumes with NEXT. ---------- Interrupts ---------- Interrupts are classified as run-mode or halt-mode, external or internal, and ICS or non-ICS. Run-mode interrupts (all internal and external interrupts) occur when the Run FF is set, and halt-mode interrupts (from the front panel and maintenance panel switches) occur when the Run FF is clear. External interrupts are those originating with the device controllers, and internal interrupts are conditions detected by the microcode (e.g., a bounds violation or arithmetic overflow). ICS interrupts execute their handlers on the system Interrupt Control Stack. Non-ICS interrupts execute on the user's stack. A run-mode interrupt is indicated by a jump to microcode location 3 with the corresponding bit set in the CPX1 micromachine register, as follows: Run-Mode Interrupt Status (CPX1) ---------------------------------------- * 0 = integer overflow * 1 = bounds violation * 2 = illegal address * 3 = CPU timer; non-responding module * 4 = system parity error * 5 = address parity error * 6 = data parity error * 7 = module interrupt * 8 = external interrupt * 9 = power fail interrupt 10 = 0 11 = ICS flag 12 = DISP flag 13 = emulator 14 = I/O timer 15 = firmware option present * = interrupt sources Note that integer overflows and bounds violations are generated by hardware, but the associated handlers also may be invoked by microcode aborts via direct jumps. The following conditions cause interrupts but allow the current instruction to run to completion (the result of the instruction is indeterminate): - illegal address - non-responding module - system, address, or data parity error - module interrupt A halt-mode interrupt is indicated by a jump to microcode location 3 with the corresponding bit set in the CPX2 micromachine register, as follows: Halt-Mode Interrupt Status (CPX2) ----------------------------------- * 0 = run switch * 1 = dump switch * 2 = load switch * 3 = load register * 4 = load address * 5 = load memory * 6 = display memory * 7 = single step * 8 = execute switch 9 = increment address 10 = decrement address 11 = 0 12 = 0 13 = inhibit auto-restart switch 14 = system halt flip-flop state 15 = run flip-flop state * = interrupt sources Note: "increment address" and "decrement address" appear together with "load memory" or "display memory." They do not generate interrupts on their own. The microcode always executes continuously, so run vs. halt mode is simply a matter of executing different microcode routines. While the machine is halted, the micromachine is executing a REPC / PNLR TEST pair of micro-orders. PNLR enables the maintenance panel to control the CPU. TEST causes the instruction repeat to end if an enabled interrupt occurs. Upon resumption, the microcode jumps explicitly to ROM location 3 to handle the halt-mode interrupt. External interrupts are indicated by the IOP asserting the EXTINT signal, which sets CPX1 bit 8 and causes the microcode to vector to address 3 when the NEXT micro-order is executed, i.e., at the end of the current instruction. External interrupts may be inhibited selectively by setting the interrupt mask with SMSK. Only those device controllers that are part of an enabled interrupt group will assert INTREQ. Note, though, that the interrupt mask jumper "...must be set to the ENABLE position in all Series III systems." So it appears that interrupt masks are not used in the later systems. External interrupts also may be inhibited globally with SED. SED sets or clears the I (interrupt) bit in the status register. If the I bit is clear, the INTREQ signal to the IOP is inhibited, so an interrupt poll is not conducted, so an INTACK is not received, so the EXT INT flip-flop is not set, so the External Interrupt bit in CPX1 will not set. Internal interrupts are either deferred or immediate. Deferred interrupts (e.g., arithmetic overflow) set the corresponding bits in CPX1 but allow the current instruction to run to completion. Interrupt processing begins at ROM location 3 when the NEXT micro-order is executed. Immediate interrupts are a result of microcode aborts, which terminate the current instruction immediately and vector to the start of the appropriate interrupt handler. Except for Bounds Violation, immediate interrupts do not jump to location 3. Finally, the external, overflow, module, module error, and CPU timer interrupts are enabled only if the run FF is set and the system halt and power fail interrupt FFs are clear. In addition, the module interrupt is qualified by the I bit in the status register. The MCU MODINT flip-flop sets when the CPU receives an unsolicited Central Data Bus message, but its output is inhibited by the clear I bit, so the Module Interrupt bit in CPX1 will not set. ---------------- Microcode Aborts ---------------- Microcode routines for machine instructions are entered via the look-up table (LUT) during processing of the NEXT micro-order. Normally, a routine exits via NEXT, which loads NIR into CIR and the LUT, starts a read of the following instruction into NIR, and increments P. However, the routine may detect a condition that does not allow the instruction to complete. This causes instruction execution to be aborted. There are two mechanisms that are employed to abort an instruction: 1. A bounds check via BNDT or UBNT forces a branch to microcode ROM address 3, the interrupt handler. 2. An explicit JMP out of the current routine is performed. The latter is employed in these cases: - system halt - unimplemented instruction - stack underflow - stack overflow - privilege violation - STT violation - CST violation - DST violation - absent code segment - absent data segment - STT entry uncallable - trace - user traps (integer overflow, divide by zero, floating-point underflow, etc.) If user traps are disabled, NEXT is executed to terminate the affected instruction normally. Note that some detected errors do not cause microcode aborts. For example, an instruction causing an arithmetic overflow will complete normally. Then, if enabled by the microcode, the overflow will assert an internal interrupt request, which will be handled as part of the normal interrupt handling when the arithmetic instruction routine ends with NEXT. The following conditions cause interrupts but allow the current instruction to run to completion (the result of the instruction is indeterminate): - illegal memory address - non-responding module - system, address, or data parity error - module interrupt Finally, a system halt abort does not cause an interrupt. Rather, the SYSH routine is called directly, which sets the System Halt bit in CPX2 and then loops until the CPU is reset. ------------------------- Interrupt Classifications ------------------------- Label STT Param Stack Source Entry ROM Type ------ --- ------ ----- ------ ----- ---- ------------------------------------------------- -- - -- - abort SYSH 2762 System Halt (DRT) - devnum ICS CPX1.8 IR 3001 External Interrupt 100401 1 label user CPX1.1 IR 3001 Bounds Violation 100401 1 label user abort BNDV 3001 Bounds Violation 101001 2 label user CPX1.2 IR 3001 Illegal Memory Address 101401 3 label user CPX1.3 IR 3001 Non-Responding Module 102001 4 label ICS CPX1.4 IR 3001 System Parity Error 102401 5 label ICS CPX1.5 IR 3001 Address Parity Error 103001 6 label ICS CPX1.6 IR 3001 Data Parity Error 103401 7 module ICS CPX1.7 IR 3001 Module Interrupt 104001 10 -- - -- - (Unused) 104401 11 label ICS CPX1.9 IR 3001 Power Fail 105001 12 -- - -- - (Unused) 105401 13 -- - -- - (Unused) 106001 14 -- - -- - (Unused) 106401 15 -- - -- - (Unused) 107001 16 -- - -- - (Unused) 107401 17 -- - -- - (Unused) 110001 20 label user LUT TRP7 3124 Unimplemented Instruction 110401 21 label user abort STTV 3123 STT Violation 111001 22 label user abort CSTV 3122 CST Violation 111401 23 label user abort DSTV 3121 DST Violation 112001 24 label user abort STUN 3120 Stack Underflow 112401 25 label user abort TRP6 3117 Privileged Mode Violation 113001 26 -- - -- - (Unused) 113401 27 -- - -- - (Unused) 114001 30 label ICS abort EX11 2527 Stack Overflow 114401 31 000001 user abort TRP1 3133 User Trap (integer overflow) 114401 31 000002 user abort TRP2 3132 User Trap (floating-point overflow) 114401 31 000003 user abort TRP3 3131 User Trap (floating-point underflow) 114401 31 000004 user abort TRP4 3130 User Trap (integer divide by 0) 114401 31 000005 user abort TRP5 3127 User Trap (floating-point divide by 0) 114401 31 000010 user abort EFOV 0214 User Trap (ext. prec. floating-point overflow) 114401 31 000011 user abort EFOV 0214 User Trap (ext. prec. floating-point underflow) 114401 31 000012 user abort EFV1 0215 User Trap (ext. prec. floating-point divide by 0) 114401 31 000013 user abort TRP1 User Trap (decimal overflow) 114401 31 000014 user abort TRP1 User Trap (invalid ascii digit) 114401 31 000015 user abort TRP1 User Trap (invalid decimal digit) 114401 31 000016 user abort TRP1 User Trap (invalid source word count) 114401 31 000017 user abort TRP1 User Trap (invalid decimal length) 114401 31 000020 user abort TRP1 User Trap (decimal divide by 0) 115001 32 -- - -- - (Unused) 115401 33 -- - -- - (Unused) 116001 34 -- - -- - (Unused) 116401 35 -- - -- - (Unused) 117001 36 -- - -- - (Unused) 117401 37 P labl user abort EXI8 2520 Absent Code Segment (on PCAL) 117401 37 N user abort EXI8 2520 Absent Code Segment (on EXIT) 117401 37 0 user abort EXI8 2520 Absent Code Segment (on IXIT) 120001 40 P labl user abort EXI8 2520 Trace (on PCAL) 120001 40 N user abort EXI8 2520 Trace (on EXIT) 120001 40 0 user abort EXI8 2520 Trace (on IXIT) 120401 41 P labl user abort INT5 3067 STT Entry Uncallable 121001 42 DST # user abort DSG2 2372 Absent Data Segment 121401 43 label ICS PS PWR 2742 Power On 122001 44 000000 ICS LOAD COLD 3206 Cold Load (system I/O) 122001 44 label ICS LOAD COLD 3206 Cold Load (direct I/O) All User Traps (STT No. %31) are enabled by the User Traps bit in the Status register. Note that the Series III Reference/Training Manual refers to user trap %17 as "Result Word Count Overflow," but the trap also occurs on source count overflows. The microcode refers to this as a decimal length trap, which is more descriptive. ------------------------ Firmware Option Presence ------------------------ Optional extension instruction sets decode from CIR values 020400-020777, including 020570 (DMUL) and 020571 (DDIV), which are part of the base set. All extension instructions initially branch via the main lookup table to label OPTX (ROM 1613), which checks the "firmware option present" bit in CPX1 before branching to a calculated address for the extension microcode. This bit is set by comparing jumpers W1-W8 on the CIR PCA to CIR bits 8-11. If the present bit is clear, the firmware branches to the unimplemented instruction label at 7777 and then wraps around to location 0, causing a UI trap. A machine with no options has all jumpers installed. Removing jumpers sets the "firmware option present" bit for specific CIR ranges, as follows: Jumper CIR 8-11 CIR Range Option ------ -------- ------------- --------------------------------------------- W1 0000 020400-020417 Extended Instruction Set (Floating Point) W2 0001 020420-020437 32105A APL Instruction Set W3 0010 020440-020457 W4 0011 020460-020477 32234A COBOL II Instruction Set W5 0100 020500-020517 W6 0101 020520-020537 W7 0110 020540-020557 -- 0111 020560-020577 Base Set (DMUL/DDIV) W8 1000 020600-020777 Extended Instruction Set (Decimal Arithmetic) The range occupied by the base set has no jumper and is hardwired as "present". For other ranges, if the jumper is absent, the microcode at OPTX branches as follows: - for CIR range 020400-020577, RAR = 3400 + CIR(8:15)/2 - for CIR range 020600-020777, RAR = 12360 + CIR(12:15) The microcode implementations are: RAR = (3400 + CIR(8:15) + 3400) / 2 and: RAR = 12360 OR CIR(8:15) ...respectively. Note the constant operand in the second operation has bits 8-11 set, so the inclusive OR effectively adds CIR(12:15). ----------- System Halt ----------- The 3000 has two halt conditions: a normal halt, and a system halt. A normal halt occurs when the RUN flip-flop is reset, either by a programmed HALT instruction or by pressing the RUN/HALT button on the front panel. The status of the RUN flip-flop is indicated by the RUN LED on the front panel. A system halt occurs when a microcode jump to the SYSH label is done. This executes a CCPX micro-order with bit 2 of the U-BUS set, which asserts the J input to the System Halt flip-flop. The K input is grounded, so the only way to reset the System Halt flip-flop is via a CPU reset. These conditions cause a system halt in microcode: - I/O timeout on RIN from IXIT - PSEB with dispatcher already enabled - STT violation or CST violation or CS absent or Trace and segment = 0 or 1 - CS absent while executing on the ICS - stack overflow while executing on the ICS - I/O timeout on SIO from cold load - no interrupt after cold load program completes (hardware does infinite loop) - LOCK instruction with external interrupts disabled ----------------- System Halt Codes ----------------- System halt codes (series 64/68, 30140-90006, April 1984, p 4-25; series 37, 30457-90039 February 1989, p 5-49): 0 = unexpected/unknown interrupt 1* = STT violation in segment 1 2* = Absent code segment while on ICS 3* = Absent segment or trace in segment 1 4* = ICS stack overflow 5 = CST length violation 6* = bootstrap channel program timeout; Initial program load failure 7 = bootstrap channel program checksum; Illegal S-bank at QI-5 during IXIT 8* = bootstrap channel program abort 9* = Pseudo-enable while enabled (QI-18 < 0) 10 = module send message timeout 11 = invalid module responding 12 = channel not system controller 13* = code segment violation in segment 1 14 = non-responding channel 15 = Channel 0 responding to IPOLL 16 = Message interrupt without IRQ or CSRQ assertion 17 = Channel cannot be made controller-in-charge 18 = Module receive message timeout 19 = I/O error, parity or timeout 20 = WCS checksum error 21 = LUT checksum error 22 = Bad DCU Command Code * = Series II system halt Series 3x/4x/5x system halt table in 30070-90010 list codes 1-9. Remainder are Series 6x codes. The full set are listed in the V/E tables manual. "CST length violation" is described in the tables manual as, "CST table length (word 0) is zero." Using a segment number > CST length produces a CST Violation Trap. For the Series II/III, the system halt code must be inferred from the values in SP1 (scratch pad register 0), SP2, and CIR. For the Series 30/33, NIR contains the halt code. For the Series 44, SP0 contains the halt code. This is copied to memory location %1421 during a cold dump. ---------------- Stack Operations ---------------- Stack machine instructions may contain 0, 1, or 2 operations by encoding two NOPs, one non-NOP and one NOP, or two non-NOPs; the first form results in an all-zeros word. The R bit in the status word indicates when the right stack operation is being executed. This is only significant if an interrupt occurs between the two stack ops. In this case, P points at the instruction word and R is set. When the IXIT occurs, the second operation will be executed, and then P will be incremented to point at the next instruction word. Execution is from left to right. -------------------- The Stack Pointer(s) -------------------- The logical stack pointer, S, does not exist as a physical register. Instead, it is the arithmetic sum of the values of two physical registers, SM and SR. SM is the stack memory pointer. It contains the address of the last stack word stored in memory. SR is the stack register pointer. It contains the count (0-4) of stack words that are stored in the TOS registers. To improve speed, up to four TOS locations are stored in registers instead of memory. Micro-orders RA, RB, RC, and RD refer to the current top-of-stack (i.e., [S]), next-to-top ([S-1]), etc. SR indicates which of these registers contain valid data. For example, if SR = 0, then RA-RD are all invalid, and [S] is actually in memory (at [SM]). If SR = 1, then RA is valid and contains [S], RB-RD are invalid, and [SM] contains [S-1]. Hardware renaming is performed so that RA (etc.) always points to the TOS register that represents the current top-of-stack value. Microcode for the stack instructions only manipulates the TOS registers. Each stack instruction indicates, via the lookup table, how many stack locations must be in registers before the instruction is dispatched. If SR is less than the required number, microcode is executed to load values into the TOS registers from memory, incrementing SR and decrementing SM. If SM drops below DB, a stack underflow exception occurs. Micro-orders PUSH and POP only change SR and the TOS renaming. If SR = 4 when a PUSH is needed, a subroutine is called to increment SM and write the RD value to memory. If SM goes above Z, a stack overflow exception occurs. The TOS registers are flushed to memory in several cases: during execution of the PSHR, SETR, ADDS, SUBS, SCAL, PCAL, SXIT, EXIT, HALT, and PAUS instructions, for certain interrupts, and for the cold load and dump microroutines. Because SM and not S is bounds-checked, the stack may extend up to four locations beyond the stack limit Z. The diagnostic surely will test for this; however, MPE apparently allocates extra space (128 words) above Z for this, as well as for stacking during an interrupt. See p 182 (5-1) of 30000-90143. For simulation, it is unclear whether it is necessary to model the TOS registers. However, note that move, compare, and scan instructions (e.g., MOVE, CMPB, SCU) will access memory, and not the TOS parameters, if the source or target address advances into the stack area containing the parameters. See p 157 (4-26) of 30000-90143. ----------------------- Power Fail and Power On ----------------------- When power is initially applied or restored following a power failure, the -CPURST and -IORESET signals are pulsed [ALU], and then the microcode ROM address is forced to location 1 [CIR], causing a jump to PWR (2742). The microcode: 1. Reads the value of CPX2 at the time of the power failure (or zero if this is an initial power application). PWR (2742): subroutine for power fail and entry for power restore - ABS BANK = 0 - F1 = SET - OPND = M [6] (ZI, permanent ICS stack limit) - SP2 = LABEL (35,1) - OPND = M [M [6] + 1] (CPX2 value at time of power fail) - M [M [6] + 1] = CPX2 (writes current CPX2 value) - RSB if power fail; continue if power restore - if OPND.15 = 0, then goto CPRS (2765) (enter halt mode if run FF not set) - STA = %100000 (priv mode) - run FF = SET - SP3 = SP2 - goto INT2 (3033) (do power-on trap) 2. Continues processing as with other ICS interrupts: INT2 -> INT3 -> INT4 -> INT5 -> INT6 -> PCL3 -> PCL5 -> PCL6 -> PW2. PW2 (2755): check for auto-restart enabled (0) or inhibited (1) - if CPX2.14 = 0, then NEXT - fall into HALT (2757) (auto-restart is inhibited) If the CPU was running at the time of the power failure, the power on routine now executes. In MPE, this prints "**POWERFAIL**" on the system console and restarts the system clock and all interrupted I/O operations. The power failure sequence begins when the power supply asserts -PFWARN to indicate that input power has dropped below sustainable levels. On the ALU, -PFWARN triggers an 8-millisecond one-shot that asserts the PWRFAIL signal. -PFWARN is also distributed to the device controllers on the IOP/Power bus, so that devices have warning of an impending power failure (e.g., the disc controller asserts an XFERERROR condition in response to abort any transfer in progress). PWRFAIL is ANDed with the not-Q output of the PWR INH (power fail interrupt inhibit) flip-flop and asserts the INTRP signal [CIR]. If the CPU is halted when power failed, the microcode: 1. Detects the interrupt while looping in the halt-mode idle loop in CPRS (2765). Note that while in the halt state, all CPX1 bits EXCEPT power fail are held off [microcode p.230]. 2. Stores CPX1 into the counter before jumping to IR (3001). 3. Transfers to HMOD (3143), which calls PWR (2742) to store CPX2 in ZI + 1 and then enters an infinite loop (3144) to wait for power to die. If the CPU is running when power failed, the microcode: 1. Begins interrupt processing with CPX1.9 = 1. IR (3001): process a hardware interrupt - SP2 = CPX2 - if CPX2.15 = 0, then goto HMOD (3143) for a halt-mode interrupt - if CPX2.0 (run switch) = 1, goto STOP (2760) to halt the machine - SP3 = CPX1.0-CPX1.9 (this is the set of run-time interrupts) - if CPX1.8 (external interrupt) is the only bit set, then goto INT1 with SP2 = 0 to handle the external interrupt - CNTR = CPX1.4-CPX1.9 - if SP3 = 0, goto STOP (2760) because a halt-time interrupt occurred - if CPX1.0 (integer overflow) = 1, goto TR1E (1251) to handle the overflow - if CPX1.9 (power fail) = 1, call PWR (2742) to write CPX2 at ZI + 1 - set CNTR to 0-8 for the first bit within CPX1.1 -> CPX1.9 that is set - [BNDV 3013] if CNTR = 7 (external interrupt), then goto INT1 with SP2 = 0 to handle the external interrupt - SP2 = %100001 | (CNTR + 1) << 8 (external label CNTR+1,1) - SP3 = SP2 (parameter = label) - F2 = 1, fall into INT0 2. Continues processing as with other ICS interrupts: INT0 -> INT1 -> INT2 -> INT3 -> INT4 -> INT5 -> INT6. INT6 sets the PWR INH flip-flop [CIR]; this locks out the RUN switch and inhibits all other halt-mode (CPX2) and run-mode (CPX1) interrupts until the CPU is reset [microcode p.230]. 3. Continues processing: INT6 -> PCL3 -> PCL5 -> PCL6 -> NEXT. The power fail routine now executes. In MPE, this ends with a HALT 7 to wait for power to die. If multiple interrupts are present, the microcode stacks them in left-to-right order of appearance in CPX1 bits 0-9. As the power fail interrupt is CPX1 bit 9, it is the last one stacked and therefore the first one serviced. When the microcode "resets" the interrupt, the PWR INH flip-flop sets, which prevents any new interrupts from being seen. This allows the power-fail software handler to execute to completion. The Memory Control and Logic PCA guarantees 3.0 msec for the CPU to execute its power-fail routine. After 3.0 msec, clock timing to memory is disabled until power is restored [ref/training p.237]. A power failure causes internal interrupt (STT %11, ICS). A power restoration with ARS enabled causes internal interrupt (STT %43, ICS). In MPE, the handlers are in module 10, ININ. The Power-Fail Auto-Restart Enabled/Disabled switch is a two-position toggle located on the rear of the front panel. The switch position determines whether the CPU will halt (disabled) or automatically restart (enabled) when power is applied after a power failure. ------------- Process Clock ------------- The process clock register increments at a 1.001 ms interval if the CPU is not halted or executing on the ICS (ICS flag = 0). [SRM p. 3-63] The clock is implemented by eight 74161 synchronous binary counters on sheet 2 of the S-Bus PCA. The lower four counters (U57, U67, U77, and U87; 16 bits) are preset by a CPU Reset to 59822 (0xE9AE) and count continuously. The value is reloaded whenever the count rolls over, giving a periodic count of 5714. The upper four counters (U55, U75, U85, and U105; 16-bits) are cleared by a CPU Reset and count only when the RUNFF signal is high and the ICSFLAG signal is low. The SCLK and RCLK instructions use the PCLK micro-order to load the counters from the U-Bus and enable them onto the S-Bus. Note that ICSFLAG and RUNFF do not inhibit the lower four counters, nor are their contents altered by SCLK, so any partial count is retained. All counters are clocked synchronously by the -CLK backplane signal, which is generated on sheet 3 of the Skip and Special Field PCA. The base clock is generated by crystal oscillator U21 at a frequency of 22.8571 MHz. The frequency is divided by two by toggle flip-flop U27 to produce the 11.42855 MHz master clock. The master clock is delayed 20 nanoseconds by delay line U117 and applied to flip-flop U87. U87 divides the frequency by two to produce the 5.714275 MHz (175.000328 ns) -CLK signal. Therefore, the lower 16-bit counter produces a carry pulse every 999.952 us (the SRM says 1.001 ms, which would require a lower count of 5712 instead of 5714). ------------------- Miscellaneous Notes ------------------- General: - A store to CCPX bits 0, 1, or 2 puts the values on the Run FF K-input, Run FF J-input, and the System Halt FF J-input, respectively, so that setting both CCPX 0 and 1 will /toggle/ the Run FF. CPU Reset (gen a5 alu; used by all): - cpx1.1 bndv - cpx1.2 illegal address - cpx1.3 cpu timer - cpx1.4 system pe - cpx1.5 address pe - cpx1.6 data pe - cpx1.7 module int - cpx1.8 ext int - cpx1.9 power fail int - cpx1.11 ics flag - cpx1.12 disp flag - cpx1.14 i/o timer - cpx2.14 sys halt ff - cpx2.15 run ff - intrp - pclock - cntr - int poll - jumps to microcode location 2, which: - jumps to CPRS (2765) - CNTR = SR - push all TOS registers - loop until interrupt I/O Reset: gen a5 alu; used a9 mcu, a10 iop CPU Timer: - The CPU freezable clock keeps a 4.6 ms one-shot [ALU] from timing out. - If the one-shot terminates, the CPU Timer signal asserts, setting bit 3 in the CPX1 register [MCU] and causing a "non-responding module" interrupt to occur [CIR]. - The CPU Timer is cleared by a write to CCPX with 4-7 code = 03. I/O Timer: - A DATA POLL (HSREQ) or IOP SO signal starts a 3 usec one-shot. - If the signal is still active when the one-shot terminates, the I/O Timer signal will assert, setting bit 14 in the CPX1 register. - This does NOT cause an interrupt; instead, I/O instructions test for a timeout and abort the instruction with CCL if it occurs. - An I/O timeout causes a system halt if a front-panel LOAD or STORE is in progress. - The I/O Timer is cleared automatically by a read of CPX1. General: - ~IODPE from IOP to MUX for illegal memory address, et. al. (30035-90001 p 4-5). - stack underflow redefined with the series 44 to be S < Q (rather than S < DB) per p 25 of Communicator 26, Feb-1981 uc p51 comments for SED say: UBUS(1) = CIR(15) IN 6C SO ANY PENDING INT OCCURS IMMEDIATELY FOLLOWING SED IF DISABLING INTERRUPTS It appears that an intentional microcode delay (of six cycles) is introduced here to satisfy this statement for the SED instruction in the Machine Instruction Set manual: If the instruction changes bit 1 of the status register from 1 to 0, any pending interrupts will occur immediately following the SED instruction. uc p245 says: It is legal to do "STORE" and "NEXT" on the same line of microcode; however, interrupt information based on the state of the "USER TRAPS BIT" and "OVLFO" (STA(2) and STA(4)) will be from the old state of the STA register -- not the new. It is NOT legal to do this if STA(1) (External Interrupt bit) is changed from 1 to 0. Since IPOLL can take up to 925 ns. to detect the interrupting device, it could be possible to have an external interrupt occur on the following instruction even though STA(1) had been turned off in the current instruction. If STA(1) is to be disabled, it should be done 1 usec (6 clocks) BEFORE executing "NEXT". The CPU diagnostic (section 4, step %21) tests that a SED 1 with a pending interrupt executes the next instruction before interrupting. So we must model this action correctly. FIX: Have SED set "int_defer" to "STATUS_I", clear "int_defer" after irq test, and change irq test to (STA & STATUS_I ^ int_defer) so that SED 1 defers int poll by one instruction and SED 0 allows int poll for one more instruction. (Actually, in simulation, an irq cannot occur during SED 0 execution, so if it's not present before execution, it will not be present after. But it's simpler to allow both cases.) ---------------- I/O Instructions ---------------- The CPU supports ten I/O instructions. I/O is either "direct" or "programmed." Direct I/O uses the RIO, WIO, CIO, and TIO instructions to transfer a word of data or control/status at a time. Programmed I/O uses the SIO instruction and programmed I/O orders to transfer multiple words without CPU intervention. The remaining I/O instructions (SED, SMSK, RMSK, CMD, and SIN) are mode agnostic. Note that SMSK affects all device controllers simultaneously. The RIO, WIO, CIO, TIO, SIO, SIN, and SMSK instructions are sent to the IOP by the CPU microcode, and the IOP forwards them on to the device controllers. The SED instruction clears or sets the I bit in the status register. RMSK pushes the value in absolute location 7 onto the stack. The CMD instruction sends a module number (0-7) and module command (0-3) over the Central Data Bus to a Module Control Unit. MOP(0:1) gets the command and TO(2:4) gets the module number, and the ACOR gets the data word. - Memory modules decode MOP as NOP, Write, Read, and Read/Write Ones (or NOP for Series III). Read and Write are sent with the address (low request); NOP is sent with the write data (high request). - CMD is used to send a command to a module. - A module interrupt (CPX1 bit 7) is used when a module wants to send a command to the CPU. The RIO, WIO, and SIO instructions first issue a TIO to the device via the IOP to obtain the device status word. RIO and WIO look for bit 1 = 1 before executing; if it is zero, the instruction is abandoned. SIO looks for bit 0 = 0 before executing. CPU to IOP transfers use Store Field IOA and IOD micro-orders. The sequence is: - Store data to IOD (Direct Output Data register) (optional) - Store command/device number to IOA - Read data from IOD (Direct Input Data register/MUXMA) - Check bit 14 of CPX1 for I/O timeout (no response to Service Out in 3 usec) If timeout, set CCL and abandon instruction Direct I/O instructions are sent via the IOP Bus to all device controllers. A microcoded store from the U-Bus to the IOA writes 16 bits to the IOP. The IOP places bits 5-7 onto the IOP Bus as IOCMD0-2 as follows: Store IOCMD Internal Inst IOA 0 1 2 Signal Action ==== ====== = = = ========== =============== SIN 100000 0 0 0 DSETINT Set Interrupt CIO 100400 0 0 1 DCONTSTB Control I/O SIO 101000 0 1 0 (STARTIO) Start I/O WIO 101400 0 1 1 DWRITESTB Write I/O IXIT 102000 1 0 0 RESETINT Reset Interrupt TIO 102400 1 0 1 DSTATSTB Test I/O SMSK 103000 1 1 0 (SETMASK) Set Mask RIO 103400 1 1 1 DREADSTB Read I/O Bits 8-15 of the U-Bus are placed on the IOP Bus as DEVNO0-7. Bit 0 of the U-Bus is 1 -> service out to device. The SIO instruction stores the TOS value in DRT entry 0 and then sends an SIO IOCMD to the device controller via the IOP. The I/O orders are shown on page 4-36 of the HP 3000 Series III Reference/Training Manual (30000-90143). Each order is a pair of 16-bit words: an I/O Control Word and an I/O Address Word. They are encoded as follows: IOCW IOCW IOAW External 0 1 2 3 4-15 0-15 Signal Action = = = = ============== ============== =========== ===================== 0 0 0 0 0 XXXXXXXXXXX Jump Address -- Unconditional Jump 0 0 0 0 1 XXXXXXXXXXX Jump Address SETJMP Conditional Jump 0 0 0 1 0 XXXXXXXXXXX Residue Count -- Return Residue 0 0 0 1 1 XXXXXXXXXXX Bank Address -- Set Bank 0 0 1 0 X XXXXXXXXXXX --- XXXXXX --- SETINT Interrupt 0 0 1 1 0 XXXXXXXXXXX Status Value TOGGLESIOOK End without Interrupt 0 0 1 1 1 XXXXXXXXXXX Status Value SETINT End with Interrupt 0 1 0 0 Control Word 1 Control Word 2 PCONTSTB Control 0 1 0 1 X XXXXXXXXXXX Status Value PSTATSTB Sense C 1 1 0 Neg Word Count Write Address PWRITESTB Write C 1 1 1 Neg Word Count Read Address PREADSTB Read The "Unconditional Jump," "Return Residue," and "Set Bank" orders are executed entirely by the channel and are not sent to the device controller. The Device Reference Table contains one four-word entry for each device. DRT entries are calculated from device 0 = address 0, but the first available device number is 4 (so the DRT starts at %20). Each entry is as follows: Word Content ==== ================================================ 0 I/O program absolute address 1 Interrupt handler program label 2 Interrupt data base (data area absolute address) 3 (reserved) RIO Instruction --------------- Pre: S-K = device number Post: S = data word, CCE (ready) S = status word, CCG (not ready) CCL (timeout) Action: - Set SP1 to device number from stack (call "AS-K") - Trap 6 if not in privileged mode - Read S-K into low byte of SP1, zero high - Set SP3 to TIO (102400) + SP1 - Send SP3 to device (call "IOPA") - Write SP3 to IOA (IOCMD and DEVNO) - Read IOD into SP3 - If CPX1:14 (I/O timeout) = 0, return - If counter <> 0, system halt - Set CCL, exit to next instruction - If SP3:1 is 0, push SP3 (status), set CCG, exit to next instruction - Set SP3 to RIO (103400) + SP1 - Send SP3 to device (call "IOPA") - Push SP3 (data), set CCE, exit to next instruction WIO Instruction --------------- Pre: S-K = device number S = data word to write Post: S popped, CCE (ready) S = status word, CCG (not ready) CCL (timeout) Action: - Set SP1 to device number from stack (call "AS-K") - Set SP2 to data word from stack (S) - Set SP3 to TIO (102400) + SP1 - Send SP3 to device (call "IOPA") - If SP3:1 is 0, push SP3 (status), set CCG, exit to next instruction - Set SP3 to WIO (101400) + SP1 - Send SP3 and SP2 to device (call "IOPD") - Write SP2 to IOD - Write SP3 to IOA (IOCMD and DEVNO) - Read IOD into SP3 - If CPX1:14 (I/O timeout) = 0, return - If counter <> 0, system halt - Set CCL, exit to next instruction - Pop stack to delete data, set CCE, exit to next instruction TIO Instruction --------------- Pre: S-K = device number Post: S = status word, CCE (ready or not ready) CCL (timeout) Action: - Set SP1 to device number from stack (call "AS-K") - Set SP3 to TIO (102400) + SP1 - Send SP3 to device (call "IOPA") - Push SP3 (status), set CCE, exit to next instruction CIO Instruction --------------- Pre: S-K = device number S = control word to write Post: S popped, CCE (ready or not ready) CCL (timeout) Action: - Set SP1 to device number from stack (call "AS-K") - Set SP2 to control word from stack (S) - Set SP3 to CIO (100400) + SP1 - Send SP3 and SP2 to device (call "IOPD") - Pop stack to delete control word, set CCE, exit to next instruction SIO Instruction --------------- Pre: S-K = device number S = address of I/O program Post: memory [device number * 4] = S, S popped, CCE (ready) S = status word, CCG (not ready) CCL (timeout) Action: - Set SP1 to device number from stack (call "AS-K") - Set SP3 to TIO (102400) + SP1 - Send SP3 to device (call "IOPA") - If SP3:0 is 0, push SP3 (status), set CCG, exit to next instruction - Write S to memory [SP1 * 4] (device number * 4) - Set SP3 to SIO (101000) + SP1 - Send SP3 to device (call "IOPA") - Pop stack to delete address, set CCE, exit to next instruction SIN Instruction --------------- Pre: S-K = device number Post: CCE (ready or not ready) CCL (timeout) Action: - Set SP1 to device number from stack (call "AS-K") - Set SP3 to SIN (100000) + SP1 - Send SP3 to device (call "IOPA") - Set CCE, exit to next instruction SMSK Instruction ---------------- Pre: S = interrupt mask word Post: memory [7] = S, S popped, CCE CCL (timeout) Action: - Trap 6 if not in privileged mode - Set SP2 to mask word from stack (S) - Set SP3 to SMSK (103000) - Send SP3 and SP2 to device (call "IOPD") - memory [7] = S - Pop stack to delete mask, set CCE, exit to next instruction --------- Cold Load --------- Pressing the LOAD+ENABLE buttons asserts a cold-load switch signal that is detected by the halt-mode microcode. This is one of 14 "halt-mode interrupts" (bit 2 of the CPX2 register). The CPU services this while halted by executing the cold-load microcode. The microcode builds an SIO program in memory and executes it. When the device interrupts, indicating the end of the SIO program, the CPU sets up an internal interrupt on the ICS to the cold-load handler that was loaded from the target device. It is unclear whether the machine halts with the cold-load handler interrupt pending, or whether it proceeds to execute the routine. The SRM says that the "CPU halts" and that "when RUN is pressed, system is in control." However, the Series II microcode sets the Run FF (this is necessary to enable the external interrupt) and does not appear to reset it. >> MPE IV sysman/sup manual p 6-69 says, "For Series II/III startup...while pressing (and holding) the ENABLE switch, press the LOAD switch. This action causes the cold load operation to begin. The Initiator program is read into main memory. Wait for the RUN light to go out. The SYSTEM HALT light should not be lit. Press the RUN/HALT switch. The Initiator program is now in execution." The last micro-order executed as part of the Series II cold-load microcode is NEXT, implying that the interrupt handler is executed. The CX microcode has an explicit jump to the WAIT microroutine to return to halt mode. Perhaps this is series-specific? - Executes microcoded tests if devno (lower byte) < 3 - CPU register test if SWCH = %000001 - Memory pattern test if SWCH = %100000 - Memory address test if SWCH = %000000 - TIO test if SWCH = %000002 - SIO test (all devices) if SWCH = %100002 - SIO test (one device) if SWCH = %005000 - Mag tape test if SWCH = %006000 - ATC test if SWCH = %007000 - Display memory logging errors if SWCH = %001000 - Write/incrementing memory test if SWCH = %002000 - Read/incrementing memory test if SWCH = %003000 - Write/decrementing memory test if SWCH = %102000 - Read/decrementing memory test if SWCH = %103000 - Display register test if SWCH = %004000 Series II Execution ------------------- - Set control byte and device number into the switch register - Press ENABLE and LOAD concurrently on the front panel - pulses CPURESET and IORESET - sets LOAD SWITCH bit 2 in CPX2 register - asserts CPU interrupt line (forces execution to location 0003) - [IR 3001] jumps to halt-mode code because Run FF is clear - [HMOD 3143] Halt-mode code sets run FF (sets if any RUN/DUMP/LOAD switches) - Clears F2 and jumps to cold-load code (as CPX2.2 is set for LOAD switch) - [COLD 3206] If SWCH bit 8 not set, initializes memory to %030370 (HALT 10) - fills abs bank 0-3 (for Series II), locations 0-177777 - CCPX = 041000 = Run + Clear Illegal Address in case less than max memory installed - [DUMP 3221] Save SBANK + 1 in counter and set SBANK = 0 - Jumps to front panel diagnostics [PADT 3520] if SWCH devno < 3 - SP2 = 122001 (cold load prog label: 1 = ext, 22 = STT #44, 001 = SEG #1) - Jumps to direct I/O load/dump [DCLD 7773] if SWCH bit 9 set (devno > 63) - SR = 0 - [PUL8 3232] - if dump, saves DRT * 4 through DRT * 4 + 7 into RA-RD, SP3, SP2, NIR, OPND because that's where the SIO dump program will be written - if load, copies OPND to RA-RD without reading memory so values will be whatever value was present before cold load (OPND not set) - in either case, SR = 4 when the routine finishes - [DMP1 3244] Set STA = 0 (clear I bit) - [DMP8 3261] Build an eight-word SIO program starting at %1430 and set DEVNO * 4 to point at it (per Series III CE handbook; Series II is different): - 1430/1 = 014000 000000 ; SET BANK 0 - 1432/3 = 040000 SWCH(0-7) ; CONTROL unit 0, read record - 1434/5 = 077760 001400 ; READ 16 words to address 001400 - 1436/7 = 000000 001400 ; JUMP to 001400 - [DMP9 3272] Issue an SIO command to the device controller If no device or device doesn't respond (I/O timeout), sys halt (CNTR non-zero) - Wait in loop for external interrupt CPX1.8 - Device reads in SIO program - If read succeeds, SIO program will do additional reads; eventually, End/Interrupt will be executed - If read fails, %001400 will contain %030370, which is End/No interrupt if interpreted as an I/O order - If interrupt never occurs, microcode hangs until CPU reset - CCPX = 044000 = Run + Clear Interrupt (clears the external interrupt) - Clear F1 and send RIN to device; if not the cold load device, jump to wait loop above - Jump to interrupt processing [INT2 3033] with CPU run flag set; SP2 = 122001 (label), SP3 = 0, F1 = 0, F2 = 0 - [INT2 3033] S bank = 0 - [INT3 3045] Q = M [5] (QI) - Z = M [6] (ZI) - set ICS flag in CPX1 - SR = 0 - DL = %177777 - M [QI-6] = S - M [QI-4] (= S - STK DB) ("meaningless if CLD") - [INT4 3055] SM = Q + 2 - [INT5 3067] STA = 100000 (priv mode) - [INT6 3071] TOS = 0 (param) - X = CIR (?value for cold load?) - ABS Bank = 0 - [PCL3 3077] if SEG# < 192 then CSTP = M [0] else M [1] - RC = label & 077400 (isolate STT#) - call [SSEG 2712] to set up code segment from CST - RD = STA & 177400 | SEG# - if SEG# >= 192, SEG# = SEG# - 192 - if SEG# == 0, CST Violation trap [CSTV 3122] - SP0 = CSTP + 4 * segment number - if SEG# > table length, sys halt [via EX10 2522 because SEG# < 2] - PBANK = M [SP0 + 2] - M [SP0] = M [SP0] | R-bit - PL = (M [SP0] & 007777) * 4 - 1 (get length - 1) - if M [SP0] & M-bit, RD = RD | 100000 (set priv) - if not M [SP0] & A-bit, PL = PL + M [SP0 + 3] - PB = M [SP0 + 3] (F2 = not absent, RD = new status, SP2 = AMRT/length from CST entry) - RC = RC >> 8 (STT#) - read stt length (M [PL]) - jump to [EXI8 2520] if A or T bit set in CSTE[0] (absent or tracing) - if CS absent or tracing, sys halt via [EXI8 2520 because SEG# < 2] - call [CLAB 2705] to check STT access - if STT# > M [PL] (stt length), sys halt via [EXI9 2521 because SEG# < 2, else STTV trap] - read label at M [PL - STT#] - if E-bit (external label), sys halt via [EXI9 2521 because SEG# < 2, else STTV trap] - if U-bit (uncallable) and STA M-bit not set (not priv), jump to [INT5 3067] (but is always priv because priv mode set above) - RC = local label from STT - [PCL5 2422] SP0 = PB + RC & 037777 (call address) - NIR = M [SP0] - if SP0 > PL, jump to BNDV - if SP0 < PB, jump to BNDV - P = SP0 + 1 - STA = RD (new status) - if F1 set, jump to [PW2 2755] (but F1 = 0 from COLD) - if F2 set, Q = RA and SM = RB (but F2 = 0 from PCL3) - Exit to next instruction fetch --------------------------- Series II Cold Load Summary --------------------------- bits 0- 7 = I/O control byte bits 8-15 = I/O device number (DRT) bit 8 0/1 = init/don't init all memory to %030370 (halt 10) warm/coolstart: SR = %000004 (7920 disc: control 0 [cold load read], DRT 4) coldstart: SR = %003006 (mag tape : control 6 [read record], DRT 6) ucode cpu reg test: SR = %000201 (II) or %000001 (III) ucode mem test: SR = %000200 (II) or %000000 (III) ucode i/o test: CR = %000202 (II) or %000002 (III) DRT pointer is absolute %000010 (bank) and %000011 (address) DRTs are assigned by jumpers on the I/O interfaces Procedure: - enter control byte/DRT into switch register - press ENABLE and LOAD simultaneously Microcode: (DRT*4+0) := DRT*4+1 (DRT*4+1) := 014000 (set bank = 0) (DRT*4+2) := bank # (DRT*4+3) := 040000 (control, word 1 = 0, word 2 = cntlbyte from SSR) (DRT*4+4) := I/O cntl byte (DRT*4+5) := 077740 (read, count = 32, address = DRT*4+7) (DRT*4+6) := DRT*4+7 (DRT*4+7) := 034000 (end with interrupt) form SIO (101000+DRT*4+1) send to device status := 044000 wait for interrupt [ Device reads 32 words into DRT*4+7. Failure to read executes End/Interrupt. Otherwise, I/O program continues with first words of record 0. ] send RIL to interrupting device(s) continue at INT2 (%3033) to set up system for execution --------- Cold Dump --------- - default value for SWCH is set by jumpers on the rear of the control panel. - dumps 4K word blocks to tape starting at address 0 and continuing through the end of memory. - after dump, computer halts with system memory size in the CIR (implies that CIR must be separate register for correct sim halt message) ------------------------------------------ Series III Cold Load/Dump Firmware Actions ------------------------------------------ This is Section 5.14 of the "Preliminary ERS for the HP 3000-35 CPU and I-O System:" It was necessary to modify the cold-load and system dump firmware. The new microcode makes use of a 32 word (decimal) reserved area of memory beginning at location 001400 in bank 0. When a cold-load or dump is initiated from the control panel, the firmware begins by initializing the reserved area of memory as follows: (For cold-loads to device numbers greater than 3 all of memory is first initialized with HALT 10 = 030370 instructions.) 1400 STARFISH DRT (0:8), MACHINE ID (8:8) = 0 FOR SERIES II, 1 FOR SERIES III 1401 OLD CONTENTS OF DEV#*4 1402 SM 1403 SP1 1404 SP2 1405 DB 1406 (0:4)=DB BANK; (4:4)=PB-BANK; (12:4)=S-BANK 1407 Z 1410 DL 1411 X 1412 Q 1413 CIR 1414 PB 1415 PL 1416 P 1417 CPX1 1420 STATUS 1421 (0:8)=CPX2(8:15); (8:8)=# BANKS 1422 SIO CONTROL 1423 BACK SPACE RECORD/WRITE EOF COMMAND 1424 SIO CONTROL 1425 WRITE GAP/REWIND-OFFLINE 1426 SIO JUMP 1427 JUMP ADDRESS = 001436 1430 SIO SET BANK 1431 BANK 1432 SIO CONTROL 1433 COMMAND FROM SWITCH REGISTER BITS (0:7) 1434 WRITE 4K IF DUMP/READ 16 IF COLD LOAD 1435 ADDRESS (INITIALLY 0 FOR DUMP, 001400 IF COLD LOAD) 1436 SIO END WITH INTERRUPT IF DUMP/SIO JUMP IF COLD LOAD 1437 JUMP ADDRESS= 001400 IF COLD LOAD The firmware then modifies the SIO program pointer for the device whose DRT number is in switch register bits (9:7) to point to the SIO program starting at 1430. It then sends an SIO command to the device and proceeds as follows. Cold-load: A 16 word continuation of the SIO program is read into memory beginning at 1400. The SIO program continues to run until an "END WITH INTERRUPT" order is executed. The CPU enters a firmware wait loop until the device interrupts. Any other interrupting devices are sent RILs (reset interrupts), and the CPU continues to wait for the device specified in the switch register. When the interrupt is received. the CPU sends a RIL to the device and then treats "cold-load" as an internal interrupt executing on the ICS. Cold dump: The SIO program starting at 1430 dumps 4K word blocks of memory to the tape unit whose device number is preconfigured into the system control panel (usually 6). The bank and address of the 4K block to be dumped (at 1431 and 1435) are continually updated by the firmware. The program is restarted until all of memory has been dumped. If an error occurs, the SIO program pointer is modified to point to the error recovery SIO program starting at 1422, and an SIO command is issued to the device. This program does a "backspace-record" and "write-gap" on the tape unit. If the error recovery SIO program completes successfully, another attempt is made to write the record that got the error. The error recovery procedure can be repeated indefinitely as long as it completes successfully. If it fails, the machine environment prior to the dump is restored, and the system halts. The dump can be tried again without the loss of information (except for the contents of CIR). During a dump, the CIR displays the sum of the bank and beginning address of the 4K block being dumped. If the tape unit is not on-line or no write-ring has been installed when the dump is initiated, the machine will halt immediately with CIR displaying 000000. No system information is lost except for the contents of CIR. The dump may be attempted again after the problem is corrected. When a successful dump completes, an end-of-file will be written, and the tape will rewind off-line. The system environment prior to the dump is restored (except for CIR) so that another dump will produce the same results. Page 5-34 of the "Console Operator's Guide Series II, III, 30, 33, and 44" (32002-90004 May 1981) says that an HP 7976 tape drive on the Starfish can be used as the dump device by placing its DRT in the upper byte of the SWCH register and the IMBA DRT (%175) in the lower byte. The upper byte is stored in the upper byte of memory word %1400, and the four-word DRT entry for that device is copied to memory words %1422-1425 prior to dumping. When it sees that the upper byte is non-zero, DPAN4 will restore these words to the indicated DRT entry before dump interpretation. The manual also notes that the CIR does not count 64K memory blocks when dumping to a Starfish device. It says, "On systems with a 7976A Tape Drive, a successful dump is indicated by the tape rewinding and the drive going offline." Dumps to SIO devices clear the upper byte of memory word %1400. ====================== Series III Main Memory ====================== The Series II supports a main memory size of 64K to 256K words in 32K increments. It uses four types of memory PCAs: - 30007-60002 MCL (Memory Control and Logging, up to 128K words) - 30008-60002 SMA (Semiconductor Memory Array, 32K words, 17 bits, 4K RAMs) - 30009-60001 FCA (Fault Correction Array, up to 128K words, 4 bits) - 30009-60002 FLI (Fault Logging Interface, up to 256K words) A 64K system uses one of each PCA. A 256K system uses 2 MCLs, 8 SMAs, 2 FCAs and 1 FLI. Five check bits (one on the SMA, four on the FCA) are used. Jumpers W1-W6 on each SMA PCA indicate the board number (0-3); this controls which PCA responds to what address for a given MCL. The Series III supports a main memory size of 128K to 1024K words in 128K increments. It uses three types of memory PCAs: - 30007-60005 MCL (Memory Control and Logging, up to 512K words) - 30008-60003 SMA (Semiconductor Memory Array, 128K words, 22 bits, 16K RAMs) - 30009-60002 FLI (Fault Logging Interface, up to 1024K words) 30135-60063 CLK/FLI (System Clock/Fault Logging Interface, up to 1024K words) A 128K system uses one of each PCA. A 1024K system uses 2 MCLs, 8 SMAs, and 1 FLI. Six check bits (all on the SMA) are used. Main memory consists of from one to eight 128K word memory arrays. Memory is divided into two 512K modules, each with its own Module Control Unit and Memory Control and Logging PCA. The two modules respond to module numbers 0 and 1 or 2 and 3. Switch S1 on each SMA PCA indicates the board number (0-3); this controls which PCA responds to what address for a given MCL. ---------------- Error Correction ---------------- Error correction is implemented by storing five (Series II) or six (Series III) check bits with the sixteen data bits. The Series III check bits reflect the parity of sets of eight data bits, as follows: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C0 C1 C2 C3 C4 C5 Parity -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ------ X X X X X X X X X Even X X X X X X X X X Odd X X X X X X X X X Even X X X X X X X X X Odd X X X X X X X X X Even X X X X X X X X X Even -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 07 13 23 03 15 25 11 21 16 06 32 22 34 14 24 30 00 20 10 04 02 01 Syndrome The check bits are generated by setting C0-C5 to zero. When read, the parity computations (syndrome) will result in all zeros if the data and check bits are correct and non-zero values if one or more bits are in error. If a single bit (either data or check) is in error, the syndrome itself will have odd parity and will indicate the bit in error as indicated above. If the syndrome is non-zero and has even parity, i.e., does not contain either one or three 1-bits, then a double-bit error has occurred, and the syndrome value is not significant. The MCL will correct single-bit data errors (single-bit check errors need not be corrected). Double-bit errors will result in data parity interrupts. Each MCL contains one 1024 x 1 static RAM ELA (Error Logging Array). The array stores a 1 in an address corresponding to the 4K or 16K RAM chip containing the bit in error. The address is 10 bits wide, consisting of a 5-bit chip-row address (2-bit SMA PCA address and 3-bit row address) and a 5-bit bit-in-error code (the lower five bits of the 6-bit ECC syndrome). The bit-in-error code is decoded as: Code Bit Code Bit Code Bit Code Bit ---- --- ---- --- ---- --- ---- --- 00 C0 10 C2 20 C1 30 D15 01 C5 11 D6 21 D7 31 -- 02 C4 12 ** 22 D11 32 D10 03 D3 13 D1 23 D2 33 -- 04 C3 14 D13 24 D14 34 D12 05 * 15 D4 25 D5 35 -- 06 D9 16 D8 26 -- 36 -- 07 D0 17 -- 27 -- 37 -- * Forced double-error write ** Missing SMA If a parity error occurs on the data sent from the MCU to the SMA for a write, the MCL asserts a data parity error (CPX1.6) and forces a double-bit error into the check bits by complementing the C3 and C5 bits. This ensures that a read of the location will always cause a data parity error interrupt. If an addressed SMA is not present, the all-zeros data and check bits result in a syndrome of 12, due to the odd parity of the C2 and C4 calculations. ----------------------- Fault Logging Interface ----------------------- Documentation is sketchy, but some information is provided here: - 30000-90018 para 4-103, page 4-44 - 30000-90143 para 6-23, page 6-21 - 30008-90001 pages 14-16 The diagnostic is PD430B, FLT.CORR.MEM SER-III. The closest manual is 30008-90001, "Stand-Alone HP 30008A/30009A Error Correction Memory Diagnostic," which describes PD430A, the diagnostic for the Series II. Page 9-20 of the CE Handbook describes PD430B. ======================== Series III I/O Processor ======================== The I/O Processor is not really a processor in the conventional sense, in that it does not execute the I/O program orders (the multiplexer and selector channels do). Nor does it execute the direct I/O instructions (the device controllers do). It is more of an I/O controller. It acts as a gateway from the CPU and memory to the device controllers with bidirectional buffers. It also handles service requests from the multiplexer channels and interrupt requests from the device controllers. General: - INTREQ from device -> INTPOLL from IOP -> highest priority device controller places device number on DEVNOn, asserts INTACK -> load DEVNOn into IOA Address In, assert EXTINT to CPU. - Catches SIO read/write requests from/to memory addresses beyond the installed capacity and aborts the operation (asserts XERR, a.k.a. IODPE). - IOP passes IOA (U Bus) over IOP Bus directly to device controller for processing (gated) - The IOP executes the direct I/O commands and interacts with the target device controller appropriately. - The multiplexer or selector channel executes the programmed I/O commands, i.e., interprets the SIO program and interacts with the target device controller appropriately. Registers: - I/O Direct (IOD) data registers interface with CPU. - I/O Programmed (IOP) data registers interface with memory. - I/O Address (IOA) register/gates interface to IOP bus control lines. - IOD Data Out register: - input from U-Bus - output to IODn - IOD Data In register: - input from IODn - output to S-Bus or MCU-bus - IOP Data Out register: - input from MCU-Bus - output to IODn or IOP Data In register - IOP Data In register: - input from IODn or IOP Data Out register - output to MCU-Bus - IOA In register: - input from DEVNOn - output to S-Bus - IOA Out gates: - input from U-Bus - output to SO, IOCMDn, and DEVNOn CPU Microcode Control: - IOD in S-Bus field reads IOD Data In register. - IOA in S-Bus field reads IOA register (interrupting device number). - IOD in store field stores U-Bus to IOD Data Out register. - IOA in store field gates U-Bus bits 5-7 to IOCMDn, bits 8-15 to DEVNOn, and bit 0 to SO (although I can find no connection from bit 0 to SO!). - CPU freezes until SI or I/O Timer asserts. ============================== Series III Multiplexer Channel ============================== General: - executes I/O programs from memory - decodes I/O orders to individual strobe lines - fetches IOCW and IOAW from memory as needed via IOP - 16 word memory (one word per device controller): - 16-bit IOCW (4-bit register for order, 12-bit up-counter for word count) - 16-bit IOAW (16-bit up-counter for address) - 6-bit Auxiliary (for memory bank number, transfer complete, in block) (bank number forced to zero unless transferring data for Read/Write) - 4-bit State - transfers one word per service request between memory and the device controller via the IOP Bus (DMA) - connects to one of sixteen device controllers, each having a different SR - controllers request connection by asserting a service request - mux responds to highest priority SR by force-denying that line. card SR buffer FF set + SR line pulled low -> mux signals enabled on card. enable allows card to respond to CHANSO, SO, PREADSTB, etc. i.e., only card with active SR will respond to mux signals common to all cards - service requests are prioritized (0 = highest, 15 = lowest) - SRs are always handled in priority order - SRn from device -> HSREQ to IOP -> DATAPOLL to MUXes -> highest priority multiplexer channel enabled - each mux SIO operation is driven by a SR from the device controller (DATAPOLL generates LOAD signal that clocks state and other RAMs) - device controller's SR FF is set by SIO command to kick off mux operation - mux asserts TOGGLESR to reset controller's SR FF at the start of a Read, Write, or Control order (device controller is responsible for asserting SR when ready to transfer), and to set the FF when these orders are complete - device controller asserts SR for each word of Control order, for a Read or Write order data transfer, and at the completion of a read or write sequence (ACKSR asserted to clear SR for these); set SR FF provides SR for all other orders and DRT/IOCW/IOAW fetch - mux asserts EOT either at word-count rollover or at DEVEND assertion from the device controller. - mux permanently asserts SIOENABLE, so SIO OK if device not currently in SIO - mux has a device number, responds to CIO, TIO, RIO, WIO for diagnostics State Machine: - Only five states are used, corresponding to none or one of the four state lines active (A, B, C, or D): - 0 = SIO Program Complete - A = Fetch IOCW - B = Fetch/Store IOAW - C = Fetch/Store DRT - D = Transfer Data - REQ from device controller sets initial State = C. - Transitions are dependent on SIO orders: - Read or Write: C -> A -> B -> D (until EOT) -> C (normal) or A (DEVEND) - End: C -> A -> B -> 0 (stops) - Set Bank: C -> A -> D -> C - All others: C -> A -> B -> C - Note: DEVEND assertion at the start of State D processing alters mux execution from Transfer Data to Fetch DRT to avoid having an unused channel cycle. - Note: DEVEND assertion during a set of chained read or write orders must remain valid through all of the orders, as the mux will cycle through the states for each order (subsequent States D will be aborted by DEVEND upon entry). - Note: the mux asserts SETJMP for a Conditional Jump order in State B but tests the JMPMET signal from the device controller in State C. So the controller must latch the results of the SETJMP test and present them continuously on the JMPMET line. Control Logic Equations: Next_State_A = ~REQ * (State_C + State_D * DEVEND_FF * (Read_Order + Write_Order)) Next_State_B = ~REQ * State_A * ~Set_Bank_Order_Next Next_State_C = REQ + State_B * ~(Read_Order + Write_Order + End_Order) + State_D * (Set_Bank_Order + EOT * ~DEVEND) Next_State_D = ~REQ * (State_A * Set_Bank_Order_Next + (State_B + State_D * ~EOT) * (Read_Order + Write_Order)) EOT = Last_Word_FF + DEVEND_FF; TOGGLEINXFER = (State_B * ~In_Block + State_D * EOT * ~Chained_Order) * Read_Order TOGGLEOUTXFER = (State_B * ~In_Block + State_D * EOT * ~Chained_Order) * Write_Order Note: The intent is to set the device controller IN/OUTXFER FFs for the first Read or Write order and clear them after the last Read or Write order but not to toggle them on intermediate chained orders. The IOCW is loaded in State A, so toggling the FFs depends on whether or not the channel is transferring within the same block. In_Block is cleared by REQ, set at the end of State B for a Read or Write order, and cleared at the end of State D if EOT is set and the current order is not chained. The effect is to enable TOGGLEnXFER in State B for the first Read/Write order, regardless of the DC bit in that order, and inhibit TOGGLEnXFER in State B for additional Read/Write orders if the DC bit was set in the prior order. TOGGLESIOOK = State_B * End_Order PSTATSTB = State_B * (Sense_Order + End_Order) PREADSTB = State_D * Read_Order * ~DEVEND * Load_Complete PWRITESTB = State_D * Write_Order * ~DEVEND_FF * Load_Complete READNEXTWD = (State_B + State_D * ~EOT) * Read_Order * Load_Complete PCMD1 = State_A * Control_Order_Next PCONTSTB = State_B * Control_Order SETINT = State_B * (Interrupt_Order + End_Order * Interrupt_Bit) SETJMP = State_B * Jump_Order * Conditional_Bit SIOENABLE = 1 ACKSR = Address_Transfer * ((State_A + State_C) * (Read_Order + Write_Order) * ~Chained_Order + (State_B + State_C) * Control_Order + State_D * (Read_Order + Write_Order)) Note: The intent is to clear externally generated SRs by clearing the controller's Device SR FFs. Note: The "Read_Order", "Write_Order", and "Chained_Order" in State A are the PREVIOUS orders, not the NEW order loaded in State A. The load of the RAM registers precedes the IOCW read and RAM store. The intent is to clear controller's Device SR FFs, unless a chained order is executing, in which case the SR from the last transfer of the chained order enables the first transfer of the next transfer before being cleared. DEVNODB = State_C * CHANACK Note: CHANACK denies when DATAPOLL denies, releasing IODn for Store DRT if needed (Jump order). TOGGLESR = State_A * Control_Order_Next + State_B * (Read_Order + Write_Order + End_Order) + State_C * ~Chained_Order * (Read_Order + Write_Order + Control_Order) + State_D * ~Chained_Order * (Read_Order + Write_Order) * DEVEND_FF + State_D * Chained_Order * EOT Note: The orders tested in State C are the prior orders, as the new order isn't written to the state RAM until the end of State A. The order tested in State A is the order that will be written to the RAM at the end of the state. Auxiliary RAM: - holds 4-bit memory bank number for read/write data transfers only. - holds 1-bit Transfer Complete (TC) flag for diagnostics only (RIO STATE). - holds 1-bit In Block (DC) flag for TOGGLE*XFER strobe generation. - all bits cleared by REQ or IORESET. - all bits clocked into registers at start of cycle. - all bits written back to RAM at end of cycle (SO trailing edge). - AUX.TC RAM is: - set by carry out of IOCW up-counter (sets AUX.TC register as well), - cleared by State B * Read/Write order. Carry is inactive unless clock is active, so a DEVEND with one word remaining in the counter will NOT set AUX.TC RAM. - AUX.DC RAM is: - set by State B * Read/Write order, - cleared by State D * EOT * ORDER.0 register (Chained Order) = 0. Transfer Aborts: - Device controller asserts DEVEND if it detects a retryable error. - Mux asserts XFERERROR to device controller if it detects a fatal error. - Fatal errors are: - invalid state in STATE RAM (STATE PRTY, "state parity error") - IODn bus received data parity error (BUS PE) - IOP transfer error (XERR, IODPE, "parity error"); is true for I/O timeout, memory address PE, system PE, and illegal address (> LWAM). IOP Interaction: - Performs memory reads/writes on behalf of the device controller or itself. - Does address (inbound) and data (inbound or outbound) transfers. - Every state starts with an address transfer immediately after poll acknowledged. IOP Address Transfer: - IOP asserts DATAPOLL IN to mux. - Mux asserts CHANACK and then CHANSO to device controller, loads addressed RAM contents into registers. - Mux puts IOP order onto IOCMDn, address onto IODn, and asserts SI to IOP. - IOP stores IODn into IOD Data In and onto MCU-bus as address. - IOP denies DATAPOLL IN to mux. - Mux denies SI to IOP, CHANACK to device controller. - If order = Read or Write, mux increments address and word-count RAMs. IOP Outbound Data Transfer: - IOP stores MCU-bus into IOP Data Out and onto IODn, and asserts SO to mux. - Mux stores IODn into RAM or asserts a write strobe to the device controller. - Mux asserts SI to IOP. - IOP denies SO to mux. - Mux denies SI to IOP. IOP Inbound Data Transfer: - IOP asserts SO to mux. - Mux puts RAM onto IODn or asserts a read strobe to the device controller. - Mux asserts SI to IOP. - IOP stores IODn into IOP Data In and sends to MCU-bus as data. - IOP denies SO to mux. - Mux denies SI to IOP. SIO Initialize Operation: - CPU microcode executes IOA in the store field. - IOP gates U-Bus to IOCMDn and DEVNOn, asserts SO. - SIO command * card not selected -> card SR inhibited for duration of SIO; this ensures only initializing card SR asserted to produce RAM address. - SIO command * card selected -> controller sets SIO OK, SR, enable SR, and SR buffer FFs, and asserts REQ to mux (REQ is SIO command pulse). - REQ sets next state [SRn] = Fetch DRT (C), clears other RAMs, asserts SI to IOP. - IOP denies SO, CPU resumes with next instruction. - Mux denies SI. SIO Fetch DRT (State C; prior order not Jump and not Conditional Jump or condition not met): - SR FF * enable SR FF asserts SRn to mux. - Mux responds to SRn from device controller by asserting HSREQ to IOP. - IOP asserts DATAPOLL IN to mux. - Inactive mux asserts DATAPOLL OUT to next mux in chain; highest priority active mux inhibits DATAPOLL OUT, sets its SR Latch. - SR Latch set force-denies device controller SRn, asserts CHANACK and then CHANSO to device controller to enable mux strobes, and loads addressed RAM contents into registers. - CHANSO enables JMPMET, which is denied by the device controller. - If last order was Read/Write/Control and not chained, mux asserts TOGGLESR to device controller. - Mux asserts ACKSR and DEVNODB to device controller. - Controller places device number * 4 (DRT address) onto IODn. - Mux sets DRTF ("DRT fetch") onto IOCMDn, 0 onto IOXn, and asserts SI to IOP. - IOP stores IODn into IOD Data In and onto MCU-bus as address, MOP = read. - IOP denies DATAPOLL IN to mux. - Mux denies SI to IOP, CHANACK and DEVNODB to device controller. - Memory read (I/O program address) stores MCU-bus into IOP Data Out and onto IODn, asserts SO to mux. - IOP copies IOP Data Out to IOP Data In, increments by 2, and writes to memory using IOD Data In as address (writes back to DRT to anticipate the next Fetch DRT). - Mux stores IODn into address RAM. - Mux asserts SI to IOP. - IOP denies SO to mux. - Mux denies SI to IOP, CHANSO to device controller to disable strobes, clears SR Latch, and sets next state = Fetch IOCW (A). SIO Store DRT (State C; prior order is Jump or Conditional Jump and condition met): - SR FF * enable SR FF asserts SRn to mux. - Mux responds to SRn from device controller by asserting HSREQ to IOP. - IOP asserts DATAPOLL IN to mux. - Inactive mux asserts DATAPOLL OUT to next mux in chain; highest priority active mux inhibits DATAPOLL OUT, sets its SR Latch. - SR Latch set force-denies device controller SRn, asserts CHANACK and then CHANSO to device controller to enable mux strobes, and loads addressed RAM contents into registers. - CHANSO enables JMPMET, which is asserted by the device controller. - If last order was Read/Write/Control and not chained, mux asserts TOGGLESR to device controller. - Mux asserts ACKSR and DEVNODB to device controller. - Controller places device number * 4 (DRT address) onto IODn. - Mux sets JUMP ("Jump") onto IOCMDn, 0 onto IOXn, and asserts SI to IOP. - IOP stores IODn into IOD Data In and onto MCU-bus as address, MOP = write. - IOP denies DATAPOLL IN to mux. - Mux denies SI to IOP, CHANACK and DEVNODB to device controller. - IOP asserts SO to mux. - Mux puts address RAM value onto IODn. - Mux asserts SI to IOP. - IOP stores IODn into IOP Data In and onto MCU-bus as data, MOP = nop. - IOP increments IOP Data In by 2 and writes to memory using IOD Data In as address (writes back to DRT to anticipate the next Fetch DRT). - IOP denies SO to mux. - Mux denies SI to IOP, CHANSO to device controller to disable strobes, clears SR Latch, and sets next state = Fetch IOCW (A). SIO Fetch IOCW (State A): - SR FF and enable SR FF remain set to assert SRn to mux. - Mux responds to SRn from device controller by asserting HSREQ to IOP. - IOP asserts DATAPOLL IN to mux. - Inactive mux asserts DATAPOLL OUT to next mux in chain; highest priority active mux inhibits DATAPOLL OUT, sets its SR Latch. - SR Latch set force-denies device controller SRn, asserts CHANACK and then CHANSO to device controller to enable mux strobes, and loads addressed RAM contents into registers. - Mux puts address RAM value (IOCW address) onto IODn. - Mux sets OUTBND ("read from memory") onto IOCMDn, 0 onto IOXn, and asserts SI to IOP. - IOP stores IODn into IOD Data In and onto MCU-bus as address, MOP = read. - IOP denies DATAPOLL IN to mux. - Mux denies SI to IOP, CHANACK to device controller. - Mux increments address RAM value. - Memory read (IOCW data) stores MCU-bus into IOP Data Out and onto IODn, asserts SO to mux. - Mux stores stores IOD0-3 to order RAM. - If order /= Return Residue, mux stores IOD4-15 to word-count RAM. - If order = Control, mux asserts PCMD1 and TOGGLESR to device controller to latch control word. - Mux asserts SI to IOP. - IOP denies SO to mux. - Mux denies SI to IOP, CHANSO to device controller to disable strobes, clears SR Latch, and sets next state = Transfer Data (D) if order = Set Bank or next state = Fetch IOAW (B) otherwise. SIO Fetch IOAW (State B; Read, Write, Jump, Control, and Interrupt orders): - if order = Control, SRn is asserted when the device controller is ready for the second control word; otherwise, SR FF and enable SR FF remain set to assert SRn to mux. - Mux responds to SRn from device controller by asserting HSREQ to IOP. - IOP asserts DATAPOLL IN to mux. - Inactive mux asserts DATAPOLL OUT to next mux in chain; highest priority active mux inhibits DATAPOLL OUT, sets its SR Latch. - SR Latch set force-denies device controller SRn, asserts CHANACK and then CHANSO to device controller to enable mux strobes, and loads addressed RAM contents into registers. - Mux puts address RAM value (IOAW address) onto IODn. - Mux sets OUTBND ("read from memory") onto IOCMDn, 0 onto IOXn, and asserts SI to IOP. - IOP stores IODn into IOD Data In and onto MCU-bus as address, MOP = read. - IOP denies DATAPOLL IN to mux. - Mux denies SI to IOP, CHANACK to device controller. - Mux increments address RAM value. - Memory read (IOAW data) stores MCU-bus into IOP Data Out and onto IODn, asserts SO to mux. - If order = Control, mux asserts ACKSR to device controller; otherwise, mux stores IODn to address RAM. - If auxiliary RAM In Block bit = 0, mux asserts TOGGLEINXFER if order = Read or TOGGLEOUTXFER if order = Write to device controller. - If order = Read/Write, mux asserts TOGGLESR to device controller, sets In Block, and clears Transfer Complete auxiliary RAM bits. - If order = Read, mux asserts READNEXTWD; if order = Conditional Jump, mux asserts SETJMP; if order = Control, mux asserts PCONTSTB; if order = Interrupt, mux asserts SETINT to device controller. - Mux asserts SI to IOP. - IOP denies SO to mux. - Mux denies SI to IOP, CHANSO to device controller to disable strobes, clears SR Latch, and sets next state = Transfer Data (D) if order = Read/Write or next state = Fetch DRT (C) otherwise. SIO Store IOAW (State B; Sense, End, and Return Residue orders): - SR FF and enable SR FF remain set to assert SRn to mux. - Mux responds to SRn from device controller by asserting HSREQ to IOP. - IOP asserts DATAPOLL IN to mux. - Inactive mux asserts DATAPOLL OUT to next mux in chain; highest priority active mux inhibits DATAPOLL OUT, sets its SR Latch. - SR Latch set force-denies device controller SRn, asserts CHANACK and then CHANSO to device controller to enable mux strobes, and loads addressed RAM contents into registers. - Mux puts address RAM value (IOAW address) onto IODn. - Mux sets INBND ("write to memory") onto IOCMDn, 0 onto IOXn, and asserts SI to IOP. - IOP stores IODn into IOD Data In and onto MCU-bus as address, MOP = write. - IOP denies DATAPOLL IN to mux. - Mux denies SI to IOP, CHANACK to device controller. - Mux increments address RAM value. - IOP asserts SO to mux. - If order = Sense, mux asserts PSTATSTB; if order = End, mux asserts TOGGLESIOOK, TOGGLESR, PSTATSTB and SETINT (if bit 0 = 1). - If order = Return Residue, mux puts word-count RAM value onto IODn; otherwise, device controller puts status on IODn. - Mux asserts SI to IOP. - IOP stores IODn into IOP Data In and onto MCU-bus as data, MOP = nop. - Memory write (IOAW data) stores MCU-bus into memory. - IOP denies SO to mux. - Mux denies SI to IOP, CHANSO to device controller to disable strobes, clears SR Latch, and sets next state = 0 if order = End or next state = Fetch DRT (C) otherwise. SIO Transfer Data (State D; Set Bank order): - SR FF and enable SR FF remain set to assert SRn to mux. - Mux responds to SRn from device controller by asserting HSREQ to IOP. - IOP asserts DATAPOLL IN to mux. - Inactive mux asserts DATAPOLL OUT to next mux in chain; highest priority active mux inhibits DATAPOLL OUT, sets its SR Latch. - SR Latch set force-denies device controller SRn, asserts CHANACK and then CHANSO to device controller to enable mux strobes, and loads addressed RAM contents into registers. - Mux puts address RAM value (IOAW address) onto IODn. - Mux sets OUTBND ("read from memory") onto IOCMDn, 0 onto IOXn, and asserts SI to IOP. - IOP stores IODn into IOD Data In and onto MCU-bus as address, MOP = read. - IOP denies DATAPOLL IN to mux. - Mux denies SI to IOP, CHANACK to device controller. - Mux increments address RAM value. - Memory read (IOAW data) stores MCU-bus into IOP Data Out and onto IODn, asserts SO to mux. - Mux stores IODn to auxiliary RAM bank number and address RAM. - Mux asserts SI to IOP. - IOP denies SO to mux. - Mux denies SI to IOP, CHANSO to device controller to disable strobes, clears SR Latch, and sets next state = Fetch DRT (C). SIO Transfer Data (State D; Read or Write orders, DEVEND not asserted): - The device controller asserts SRn to the mux when it has a word ready to read or is ready to accept a word to write. - Mux responds to SRn from device controller by asserting HSREQ to IOP. - IOP asserts DATAPOLL IN to mux. - Inactive mux asserts DATAPOLL OUT to next mux in chain; highest priority active mux inhibits DATAPOLL OUT, sets its SR Latch. - SR Latch set force-denies device controller SRn, asserts CHANACK and then CHANSO to device controller to enable mux strobes, and loads addressed RAM contents into registers. - CHANSO enables DEVEND, which is denied by the device controller. - Mux asserts ACKSR to device controller. - Mux puts address RAM value (transfer address) onto IODn and auxiliary RAM value (bank number) onto IOXn. - Mux sets INBND ("write to memory") if order = Read, or OUTBND ("read from memory") if order = Write onto IOCMDn, asserts SI to IOP. - IOP stores IODn into IOD Data In and onto MCU-bus as address, MOP = write (if INBND) or read (if OUTBND). - IOP denies DATAPOLL IN to mux. - Mux denies SI to IOP, CHANACK to device controller. - Mux increments address and word-count RAM values. - If INBND, IOP asserts SO to mux; if OUTBND, memory read (device data) stores MCU-bus into IOP Data Out and onto IODn, asserts SO to mux. - If word count = 0, mux asserts EOT to device controller and sets auxiliary RAM Transfer Complete bit. - If word count = 0, mux asserts TOGGLESR to the device controller if the order is chained, or clears auxiliary RAM In Block bit and asserts TOGGLEINXFER (if order = Read) or TOGGLEOUTXFER (if order = Write) to the device controller if the order is not chained. - If order = Write, mux asserts PWRITESTB and the device controller stores the value onto IODn in its output buffer and initiates a write operation; if order = Read, mux asserts PREADSTB and READNEXTWD (if EOT is not asserted) and the device controller puts the value in its input buffer onto IODn and initiates a read operation (if READNEXTWD is asserted). - Mux asserts SI to IOP. - If INBND, IOP stores IODn into IOP Data In and onto MCU-bus as data, MOP = nop; memory write (device data) stores MCU-bus into memory. - IOP denies SO to mux. - Mux denies SI to IOP, CHANSO to device controller to disable strobes, clears SR Latch, and sets next state = Fetch DRT (C) if EOT asserted or Transfer Data (D) otherwise. SIO Transfer Data (State D; Read or Write orders, DEVEND asserted): - The device controller sets its internal Device End FF and asserts SRn to the mux when it detects a condition that requires aborting the transfer. - Mux responds to SRn from device controller by asserting HSREQ to IOP. - IOP asserts DATAPOLL IN to mux. - Inactive mux asserts DATAPOLL OUT to next mux in chain; highest priority active mux inhibits DATAPOLL OUT, sets its SR Latch. - SR Latch set force-denies device controller SRn, asserts CHANACK and then CHANSO to device controller to enable mux strobes, and loads addressed RAM contents into registers. - CHANSO asserted and Device End FF set asserts DEVEND to mux and sets controller Device End Buffer latch. - Mux asserts EOT and TOGGLESR to device controller. - If the order not is chained, mux clears auxiliary RAM In Block bit and asserts TOGGLEINXFER (if order = Read) or TOGGLEOUTXFER (if order = Write) to the device controller. - CHANACK asserted and Device End Buffer latch set enables device number * 4 (DRT address) onto IODn. - Mux asserts ACKSR to device controller. - Device controller clears Device End FF, which denies DEVEND. - Mux sets DRTF ("DRT fetch") onto IOCMDn, 0 onto IOXn, and asserts SI to IOP. - IOP stores IODn into IOD Data In and onto MCU-bus as address, MOP = read. - IOP denies DATAPOLL IN to mux. - Mux denies SI to IOP, CHANACK to device controller. - CHANACK denied disables device number * 4 onto IODn. - Memory read (I/O program address) stores MCU-bus into IOP Data Out and onto IODn, asserts SO to mux. - IOP copies IOP Data Out to IOP Data In, increments by 2, and writes to memory using IOD Data In as address (writes back to DRT to anticipate the next Fetch DRT). - Mux stores IODn into address RAM. - Mux asserts SI to IOP. - IOP denies SO to mux. - Mux denies SI to IOP, CHANSO to device controller to disable strobes, clear SR Latch and Device End Buffer latch, and set next state = Fetch IOCW (A). State D signals (for Read order; Write is similar): DEVEND denied: - not last word: ACKSR | PREADSTB | READNEXTWD - last word and not chained: ACKSR | PREADSTB | EOT | TOGGLEINXFER - last word and chained: ACKSR | PREADSTB | EOT | TOGGLESR DEVEND asserted: - not chained: ACKSR | EOT | TOGGLESR | TOGGLEINXFER - chained: ACKSR | EOT | TOGGLESR =========================== Series III Selector Channel =========================== General: - Consists of Control (30030-60003), Sequencer (30030-60011), Register (30030-60021), Port Controller (30030-60020), and Bus Terminator (30030-60015) PCAs. - DEVNO address register (8) (= DEVNO * 4) - memory bank register (4) - residue register (12) - I/O program counter (16) - I/O control word register (4 + 12), active and buffer - I/O address word register (16), active and buffer - input buffer (16), A and B - output buffer (16), A and B - executes I/O programs from memory - decodes I/O orders to individual strobe lines - transfers between memory and the device controller via the SEL bus (DMA) - connects to one of eight device controllers for the duration of a transfer - channel initializes and locks to controller when it receives REQ if REQ is asserted by controller while channel is active, it aborts the I/O program (init or abort depends on state of channel Active FF) and generates an internal "clear logic" signal. - SRn is 16-bit bidirectional data bus instead of service request lines - asserts SIOENABLE when idle, so SIO OK only if no other device currently SIO - CHANSR asserted by device controller moves SEL to next I/O order or data word in a multiword transfer - Note: unlike the multiplexer channel, the selector channel asserts SETJMP and tests JMPMET in the same cycle. - Continuous CHANSR transfer rate is 950KW (1.053 usec) outbound and 1140KW (0.877 usec) inbound, per the Series III CE Handbook (page 4-17). - CHANSO-to-CHANACK timeout of 10 usec - CHANSR timeout of 1 second - timeouts result in XFERERR - XFERERROR is asserted for: + SO TIMEOUT + SR TIMEOUT + WT CHAINING (order other than write follows write-chained) + RD CHAINING (order other than read follows read-chained) + PARITY ERROR + ILLEGAL ORDER (order other than read or write has chain bit on) + PORT ERROR + ILLEGAL ADDRESS An XFERERROR causes an internal "clear logic" signal to be generated that resets virtually all of the internal sequencer flip-flops but NOT the registers (e.g., program counter or word counter). SIO Initialization: - SIO instruction sends TIO to device controller via IOP - device controller returns status to IOP. status bit 0 (SIO OK) is 1 if SEL is idle, 0 if busy (SIO ENABLE from SEL is a term in every device controller's SIO OK state) - SIO instruction sends SIO to device controller via IOP - device controller sets SIO BUSY FF, enables device number onto SRn bus, asserts REQ; BUSY FF set enables Priority Latch set on next CHANSO - REQ sets Channel Active FF in SEL, latches SRn into DEVNO register, returns SI to IOP - SEL reads DEVNO register and requests memory read from address DEVNO * 4 - read value stored in I/O Program Counter register - next state is fetch NOTE: Both the HP 3000 Series II/III System Reference Manual and the HP 3000 Series III Reference/Training manuals say that the selector channel asserts a DEVNODB signal as part of the REQ processing. This is incorrect; the DEVNODB line is tied inactive by the channel, per the Control PCA schematic. Instead, the channel expects that the device number (multiplied by four) will be present on the SR0-15 lines during REQ signal assertion, when it is loaded into the device number register. Selector channel devices gate their device numbers onto SR0-15 when an SIO instruction is decoded. SIO Fetch: - SEL reads IOPC register as addr and requests memory read, increments IOPC - read value stored in IOCW Active register - SEL reads IOPC register as addr and requests memory read, increments IOPC - read value stored in IOAW Active register - next state is execute SIO Prefetch: - if order is Read or Write with Data Chain, prefetch next IOCW and IOAW as in SIO Fetch sequence (to maintain transfer speed); at end of current transfer, copy IOCW/IOAW buffer registers to active registers and do another prefetch if Data Chain is set in the copied words SIO Execute: Sense: - SEL asserts PSTATSTB * CHANSO - device controller puts status register on SRn, asserts CHANACK - SEL latches SRn into input buffer - mem [IOPC - 1] = input buffer (mem write) - next state is fetch (CHANSR not needed) Interrupt: - SEL asserts PSETINT * CHANSO - device controller sets Int Req FF, asserts CHANACK - next state is fetch (CHANSR not needed) - if Int Mask FF set, device controller asserts INTREQ to IOP - IOP asserts INTPOLL IN - device controller puts device number on IOD, asserts INTACK - IOP asserts EXTINT to CPU Jump: - if conditional, SEL asserts PSETJMP * CHANSO - if conditional, device controller asserts CHANACK and JMPMET if condition is true - if true condition or unconditional, SEL copies IOAW to IOPC - next state is fetch (CHANSR not needed) Control: - SEL puts IOCW on SRn, asserts PCMD1 * CHANSO - device controller latches first control word, asserts CHANACK - when device controller is ready for second word, it asserts CHANSR - SEL puts IOAW on SRn, asserts PCONTSTB * CHANSO - device controller latches second control word, asserts CHANACK - when control processing is complete, device controller asserts CHANSR - next state is fetch Set Bank: - SEL copies four LSBs from IOAW to Bank Register - next state is fetch (CHANSR not needed) Read: - SEL asserts TOGGLEINXFER * READNEXTWD * CHANSO - device controller sets In Xfer FF and asserts CHANACK - (loop) when word is ready, device controller asserts CHANSR - SEL asserts PREADSTB * CHANSO * (READNEXTWD if not last or EOT * TOGGLEINXFER if last) - device controller puts input buffer on SRn, asserts CHANACK - SEL latches SRn into input buffer - mem [IOAW] = SEL input buffer (mem write) - SEL sets IOAW = IOAW + 1, IOCW = IOCW + 1 - loops until IOCW = 0 or DEVEND asserted by device controller - RR = IOCW - when read processing is complete, device controller asserts CHANSR - next state is fetch Return Residue: - mem [IOPC - 1] = RR (mem write) - next state is fetch (CHANSR not needed) Write: - SEL asserts TOGGLEOUTXFER * CHANSO - device controller sets Out Xfer FF and asserts CHANACK - (loop) SEL output buffer = mem [IOAW] (mem read), IOAW = IOAW + 1 - when device controller is ready for word, it asserts CHANSR - SEL puts output buffer on SRn, asserts PWRITESTB * CHANSO (* EOT * TOGGLEOUTXFER if last) - device controller stores SRn in output buffer, asserts CHANACK - SEL sets IOCW = IOCW + 1 - loops until IOCW = 0 or DEVEND asserted by device controller - RR = IOCW - when write processing is complete, device controller asserts CHANSR - next state is fetch End: - SEL asserts TOGGLESIOOK * PSTATSTB * CHANSO (* PSETINT if IOCW bit 4) - device controller puts status register on SRn, asserts CHANACK - SEL latches SRn into input buffer - mem [IOPC - 1] = SEL input buffer (mem write) - mem [DEVNO * 4] = IOPC (mem write) - SEL clears Active FF - next state is idle LED indicators are provided on the Control PCA for: - IOCW 0-4 (order code) - ACTIVE (an order is currently executing) - WCRO (Word count roll over) - DEVEND (Device end from device controller) - XERR (An error occurred) - RR (State of the return residue FF) - END (State of the END FF) - JUMP (State of the JUMP FF) - CTRL (State of the CTRLR FF) - CHAN SR (Service request from device controller) - CHAN SO (Service out from channel) - CHAN ACK (Channel acknowledge from device controller) - FREEZE (Clock is frozen by a selected condition) ================================== Selector Channel Maintenance Board ================================== General: - Used when servicing the selector and multiplexer channels. - Exercises all I/O program orders, device-dependent signals (conditional jump, device end, etc.), and timeout conditions. - Permits display of bus data and control signals on the maintenance panel. - Jumper XW1 selects between operation on selector or multiplexer channel. - A second SCMB is needed by some diagnostics. Architecture: - Consists of a control register, a data register, a counter/buffer register, a comparator, and control logic. - The counter/buffer register (four 9316s) can hold a value for comparison to values sent via a programmed write, or it can be set to count occurrences of several channel signals (e.g., PREADSTB, PWRITESTB, etc.). Flip-flops: - channel SR (TOGGLESR) - device SR (set: INXFF + OUTXFF + PCMD1 + PCONTSTB; clr: IORST + PIORST + CLRIL) - SIOOK (TOGGLESIOOK) - OUTX (TOGGLEOUTXFER) - INX (TOGGLEINXFER) - INTREQ / INTACT - JMPMET - TC (terminal count) - NC (no compare) - XE (transfer error) - EOT - new transfer Operation: - A master reset or IORESET clears the control logic, control register, and counter/buffer register. - Either miscompare or terminal count can be enabled to generate either DEVEND or REQ (i.e., clear interface). ================== Device Controllers ================== Device controllers have three backplane connectors: - P1 : IOP/Power Bus (20 pin ribbon for IOP part) - P2 : Multiplexer or Selector Channel Bus (50 pin ribbon) - P3 : IOP Bus (50 pin ribbon) Controllers are installed with connections either to: - the IOP bus alone (e.g., ATC) - the IOP and MUX buses (e.g., 7970 mag tape) - the IOP and SEL buses (e.g., 7905 MAC disc) In the above configurations, I/O transfers occur: - direct via IOP bus; programmed not supported - direct via IOP bus; programmed via IOP with MUX controlling - direct via IOP bus; programmed via SEL with SEL controlling Device controllers have these common configuration jumpers: - Multiplexer service request priority (0-15) - Group interrupt mask (0-15, enabled always, disabled always) "This jumper must be set to the ENABLE position in all Series III systems." - Device number (0-127) - Interrupt poll order (daisy-chained twisted-pair) General: - Registers: data in buffer, data out buffer, status, control. - All controllers have SIO OK in status bit 0, RIO/WIO OK in status bit 1. Devices that cannot do SIO (e.g., ATC) have bit 0 permanently set to 0. - All controllers execute master clear for control bit 0, interrupt reset for control bit 1. - Controller needs extra hardware to do SIO vs. DIO. If hardware missing, then controller cannot be connected to MUX/SEL (e.g., ATC). - Controller needs extra hardware to do both MUX and SEL. If dual hardware is missing, then controller is dedicated to MUX (e.g., tape, printer) or SEL (e.g., disc). IOP Commands: - IOP places command on IOCMDn, device number on DEVNOn. - IOP asserts SO. - Concurrence of device number with SO causes execution of command. Exceptions are SMSK (all controllers respond) and SIO (controllers not addressed inhibit their device SRs for the duration of the command). - IOCMD0-2 decoded into one-of-eight strobes for action. - Controller stores IODn into register or enables register to IODn and asserts SI to IOP. - SI causes IOP to store IODn into IOD Data In Register. Channel Commands: - SIO to device controller sets SIO Busy FF, asserts REQ to SEL - SIO Busy FF * CHANSO from channel sets Priority Latch Priority Latch also set by SIO Busy FF * DEV SR * (INXFER + OUTXFER). Priority Latch is reset by next SO * DEVNO = device number. - Pri Latch set enables device data in/out to SRn bus instead of IODn bus, gates CHANSO to return as CHANACK, gates CHANSO to clock In Xfer, Out Xfer, SIO Busy, and Xfer Error FFs Service Request: - controller requests service by asserting SRn on MUX Bus (n is set by a jumper on the controller) - request generated by: - SR FF (mux only); sets on SIO, clears on TOGGLESR - DEVEND asserted - device SR asserted: - after control word 1 or 2 accepted - ready to send read data to memory - ready to accept write data from memory - read/write mode terminated and ready for next command - need separate SR and Device SR FFs, as a chained read/write operation toggles SR FF on while fetching next chained order at the same time that Device SR is on because the device is ready. - typically four device SR flip-flops: - Command SR FF sets on PCMD1, PCONTSTB - Xfer SR FF clocks 1 on leading edge of OUTXFER - Data SR FF clocks ? on ? - EOT SR FF clocks EOT on leading edge of PREADSTB - ACKSR clears DEVEND and device SRs but not SR FF. Device End: - Device controller sets External Device End FF if it detects a retryable error. - External Device End FF sets Device End FF and asserts SRn. - When mux asserts CHANACK and then CHANSO, device controller asserts DEVEND, sets Device End Buffer latch. - CHANACK * Device End Buffer latch enables DRT address onto IODn. - When mux asserts ACKSR, device controller clears Device End FF, which denies DEVEND. - When mux denies CHANSO, device controller clears Device End Buffer latch. - When INXFER and OUTXFER FFs clear, External Device End FF clears. This ensures that DEVEND is asserted for each Read/Write order in a chain. Transfer Error: - channel asserts XFERERROR with CHANSO for illegal address or parity error - device controller responds by clearing INXFER, OUTXFER, SIO BUSY, SR, SR Buffer FFs (stops SIO program; same action as PIORESET and IORESET), requests interrupt Jump Met: - Very few controllers use JMPMET; most tie it active. - JMPMET is available continuously during CHANSO. - Multiplexer channel asserts SETJMP during IOAW Fetch and tests JMPMET during DRT Fetch, so a Jump Met FF is needed to preserve the state. - Selector channel asserts SETJMP and latches JMPMET on the trailing edge of the same cycle. Interrupt Mask FF: - set by I/O RESET or P I/O RESET - clocked by SMSK instruction - data value is set by jumper to +5, ground, or IODn, corresponding to always enabled, always disabled, or mask group 0-15 - must be asserted for interrupt request to be made Interrupt Request FF: - set by SETINT or SIN instruction or device request - cleared by I/O RESET or P I/O RESET or RESETINT or Interrupt Active FF Interrupt Latch: - latched while INTPOLL IN is asserted - transparent while INTPOLL IN is denied - input value is Mask FF * Interrupt Request FF * Active FF clear - purpose is to provide a stable set of interrupt requests while the poll is active (prevents case where higher priority request usurps the poll just after a lower priority controller has set its Active FF) Interrupt Active FF: - set by INTPOLL IN * Interrupt Latch - cleared by I/O RESET or P I/O RESET or RESET INT - not clocked - purpose is to hold off lower priority controllers (inhibits INTPOLL OUT and Latch set, which disables device number to DEVNO bus, so IOP ignores interrupt request) Interrupt Request Process: - initial state is Interrupt Mask FF set, Latch clear, Active FF clear - interrupt request is developed by device or SIN/PSETINT from IOP/channel - true Mask FF * interrupt request asserts INTREQ to IOP - IOP polls controllers by asserting INTPOLL IN to first controller in chain - a non-interrupting controller passes INTPOLL IN to INTPOLL OUT - an interrupting controller inhibits INTPOLL OUT - INTPOLL IN sets Interrupt Latch = Active FF clear * Mask FF * request All device controller latches are thus frozen, giving a stable polling set - Interrupt Latch set inhibits INTPOLL OUT, sets Active FF, enables device number on DEVNO0-7 (INTPOLL IN asserts INTPOLL OUT if Latch is clear) - Active FF * INTPOLL IN asserts INTACK to IOP - IOP stores DEVNO0-7 into IOA register and asserts EXTINT to CPU (IOA is read by the CPU to identify the interrupting controller) - IOP denies INTPOLL IN and prohibits INTACK from starting another poll until the CPU clears the external interrupt via CCPX in the microcode interrupt handler (EXTINT remains asserted; IOA remains valid) - INTPOLL IN clear * Active FF set clears the Interrupt Latch - Active FF remains set until interrupt is serviced and RESETINT is sent - Active FF set inhibits INTPOLL OUT, so a lower priority device that requests an interrupt will cause an INTPOLL sequence that will be stopped by the device controller with an active interrupt. Because the Latch is not set, the device number will not be enabled onto DEVNO0-7, so the IOP will read the interrupting device number as 0. This causes the IOP to ignore the interrupt request. The effect is that lower priority device interrupt requests are held off while a higher priority interrupt service request handler is executing. I/O Reset: - sets Interrupt Mask FF - clears Jump Met, INXFER, OUTXFER, SIO BUSY, SR, SR Buffer, Interrupt Active FFs - invokes any controller-specific master reset function Signal Responses: - DEVNODB : places device number on IODn+2 (i.e., multiplies by four). - PCMD1 : saves control word 1, sets Command SR FF. - PCONTSTB : saves control word 2, sets Command SR FF. - TOGGLEINXFER : complements INXFER FF. - TOGGLEOUTXFER : complements OUTXFER FF. - SETINT : sets interrupt request FF. - SETJMP : sets jump met FF. - PSTATSTB : places status register contents on IODn. - TOGGLESIOOK : complements SIO OK FF. - TOGGLESR : complements SR FF. - PWRITESTB : stores IODn into output buffer, initiate transfer to device. - PREADSTB : places input buffer on IODn. - READNEXTWD: initiate transfer from device. ================================ Series III Interconnection Buses ================================ The Central Data Bus interconnects the CPU/IOP, main memory, and the Selector Channel(s). The Selector Channel interfaces to the Central Data Bus via the 30030-60020 Port Controller. The CPU and IOP interface via the 30003-60007 Module Control Unit. Main memory interfaces via the 30007-60005 Memory Control and Logging PCA. The CPU and IOP share one MCU. One MCL is used for each memory module. The first (lower) memory module supplies memory from addresses 0-128K (Series II banks 0-1) or 0-512K (Series III banks 0-7). The second (upper) memory module supplies memory from addresses 128K-256K (banks 2-3) or 512K-1024K (8-15). Each MCU, MCL, or Port Controller is identified by a Module Control Priority Number, as follows: 0 - Memory, lower bank 1 - " 2 - Memory, higher bank 3 - " 4 - Selector Channel Port Controller 5 - CPU/IOP 6 - (unused) 7 - (unused) The two memory modules respond to module numbers 0 and 1 or 2 and 3. The CDB defines: - sixteen data lines - one data parity line - three FROM module number lines - three TO module number lines - two MOP (module operation) lines - status and handshake lines The incoming parity of the FROM, TO, and MOP lines are checked, and the -SYSPE line is asserted if an error occurs. For main memory, the Module Operation (MOP) encoding is: 00 - no operation 01 - write 10 - read 11 - read/write ones (Series II only) When main memory is returning read data, the MCL sets MOP = 00 (NOP). When the CPU sends write data to the MCL, it also sets MOP = 00. Neither the CPU nor the Port Controller responds to the MOP lines. Also, the Port Controller TO address is hardware limited to 0-3, so it cannot send to the CPU. If a module addresses the CPU with the TO lines, and the CPU is not expecting the action (i.e., it is not in response to a CPU-initiated exchange), then a Module Interrupt occurs. The S-bus micro-order "MOD" will place the FROM address on bits 5-7 of the S bus, and S-bus bit 13 is asserted for the Series III and for CPU #1 of the Series II or bit 12 is asserted for CPU #2 of the Series II. In addition, although the microcode documentation doesn't mention it, the MOP is placed on bits 2-3. The "CRL" MCU micro-order stores the U-bus value into the CPU's CRL register. CRL bits 0-1 receive U-bus bits 10-11, representing the MOP. CRL bits 2-4 receive U-bus bits 13-15, representing the TO address. The "CMD" MCU micro-order stores the U-bus value into the CPU's ACOR register and initiates a low request using the MOP and TO address specified by the CRL register. Each 3000 device controller PCA typically has three backplane connectors (P1-P3) and three front-plane connectors (J1-J3), numbered from left to right. The backplane connectors are: - P1: IOP/Power Bus - P2: Multiplexer/Selector Channel Bus - P3: IOP Bus Connector P2 is connected to the Multiplexer or Selector Channel, depending on which backplane ribbon connector is used. The front-plane connectors are used to connect to devices or to interconnect between multi-board interfaces. ------------------ IOP/Power Bus (P1) ------------------ 1 -- 2 -- 3 -- 4 -- 5 -PFWARN 6 ENTIMER 7 Spare 8 Spare 9 PWR ON 10 -- 11 IORESET 12 -- 13 -MCUCLKS 14 -- 15 -- 16 -- 17 -- 18 -- 19 -- 20 -- 21 -- 22 -- 23 -- 24 -- 25 -- 26 -- 27 -- 28 -- 29 -- 30 -- 31 -- 32 -- 33 -- 34 -- 35 -- 36 -- 37 -- 38 -- 39 -- 40 -- 41 -HSREQ 42 -- 43 -- 44 INTPOLL OUT 45 -IODPE 46 -- 47 -- 48 INTPOLL IN 49 -SI 50 -- 51 -- 52 DATAPOLL OUT 53 -SO 54 -- 55 -- 56 DATAPOLL IN ---------------------------- ------------------------- Multiplexer Channel Bus (P2) Selector Channel Bus (P2) ---------------------------- ------------------------- 1 CHANSO 1 CHANSO 2 -- 2 -- 3 SRCLOCK 3 SRCLOCK 4 -- 4 -- 5 DEVEND 5 DEVEND 6 -- 6 -- 7 ACKSR 7 ACKSR 8 -- 8 -- 9 CHANACK 9 CHANACK 10 -- 10 -- 11 DEVNODB 11 DEVNODB 12 SIOENABLE 12 SIOENABLE 13 EOT 13 EOT 14 JMPMET 14 JMPMET 15 -- 15 -- 16 TOGGLEINXFER 16 TOGGLEINXFER 17 TOGGLESR 17 CHANSR 18 TOGGLEOUTXFER 18 TOGGLEOUTXFER 19 TOGGLESIOOK 19 TOGGLESIOOK 20 -- 20 -- 21 XFERERROR 21 XFERERROR 22 REQ 22 REQ 23 -- 23 -- 24 SR8 24 SR15 25 SR9 25 SR14 26 SR10 26 SR13 27 SR11 27 SR12 28 SR12 28 SR11 29 SR13 29 SR10 30 -- 30 -- 31 SR14 31 SR9 32 SR15 32 SR8 33 SR0 33 SR7 34 SR1 34 SR6 35 SR2 35 SR5 36 -- 36 -- 37 SR3 37 SR4 38 SR4 38 SR3 39 SR5 39 SR2 40 SR6 40 SR1 41 SR7 41 SR0 42 -- 42 -- 43 PCMD1 43 PCMD1 44 SETJMP 44 SETJMP 45 PSTATSTB 45 PSTATSTB 46 PCONTSTB 46 PCONTSTB 47 READNEXTWD 47 READNEXTWD 48 PWRITESTB 48 PWRITESTB 49 SETINT 49 SETINT 50 PREADSTB 50 PREADSTB --------------------------- IOP Bus (P3) (All GND true) --------------------------- 1 IODPRTY 2 IOX13 3 -- 4 IOCMD0 5 IOCMD1 6 IOCMD2 7 -- 8 DEVNO0 9 DEVN01 10 -- 11 DEVN02 12 DEVN03 13 -- 14 DEVN04 15 DEVN05 16 -- 17 DEVN06 18 DEVN07 19 -- 20 IOD0 21 IOD1 22 -- 23 IOD2 24 IOD3 25 -- 26 IOD4 27 IOD5 28 -- 29 IOD6 30 IOD7 31 -- 32 IOD8 33 IOD9 34 -- 35 IOD10 36 IOD11 37 -- 38 IOD12 39 IOD13 40 -- 41 IOD14 42 IOD15 43 -- 44 INTREQ 45 IOX12 46 -- 47 IOX14 48 IOX15 49 -- 50 INTACK ------------------- Signal Descriptions ------------------- IOP Bus ------- DEVNO0-7 -- Device number. Bidirectional. Asserted by the IOP to address a device controller for direct I/o. The device controller qualifies IOCMD by comparing the value on the bus to the device number jumper setting. Asserted by the device controller when answering an interrupt poll and placing its device number on the bus. IOCMD0-2 -- I/O command. Asserted by the IOP. Three-bit encoded direct I/O command to the device controller. Decoding is enabled by the concurrence of SO and the device number matching the DEVNO. IOD0-15 -- I/O data. Bidirectional. Asserted by the device controller or multiplexer channel with SI to transfer inbound (to memory). Asserted by the IOP with SO to transfer outbound (to device or multiplexer channel). Not used by the selector channel. IODPRTY -- I/O data parity. Bidirectional. Asserted by the IOP with outbound data on IOD, or asserted by the device controller or multiplexer channel with inbound data on IOD. Not used by the selector channel. IOX12-15 -- I/O extension. Asserted by the multiplexer channel. Provides the upper four bits of memory addresses to the IOP when sending an address in preparation for reading or writing. Not used by the selector channel, which has its own port controller to interface to memory. INTREQ -- Interrupt request. Asserted by the device controller to request an external interrupt. The IOP responds by asserting INTPOLL IN. INTACK -- Interrupt acknowledgement. Asserted by the device controller that asserted INTREQ and received INTPOLL IN. The controller responds by placing its device number on DEVNO0-7 and asserting INTACK. The IOP responds by latching DEVNO into the IOA register, where it will be available to the CPU, and asserting EXTINT to the CPU. IOP/Power Bus ------------- PFWARN -- Power failure warning. Asserted by the power supply when input power has dropped below sustainable levels no less than 500 microseconds before loss of DC power. May be used by device controllers to stop in-process operations. IORESET -- I/O reset. Asserted when the LOAD or DUMP button is pressed on the CPU front panel. Used to initialize I/O hardware. INTPOLL IN -- Interrupt poll in. Asserted by the IOP in response to an INTREQ from a device controller. The signal is propagated to INTPOLL OUT if the device controller is not requesting an interrupt. If it is, propagation is blocked, and the interrupt is acknowledged. INTPOLL OUT -- Interrupt poll out. Asserted by the device controller when it is polled but is not requesting an interrupt. SO -- Service out. Asserted by the IOP to indicate that the IOCMD, DEVNO, and IOD bus values are valid. SI -- Service in. Asserted by device controllers to acknowledge all direct I/O commands except SIO. Asserted by the multiplexer or selector channels to acknowledge SIO on behalf of the device controller. Completes an IOP handshake started with SO. ENTIMER -- Enable timer. Passively asserted. Controlled by the maintenance panel interface PCA to reflect the setting of the TIMERS ENABLE/DISABLE switch on the panel. If enabled, the CPU, memory, IOP, and selector channel will impose timeouts on critical operations. Used by the selector channel to enable acknowledgement timeouts on the CHANSO and CHANSR signals. PWR ON -- Power on. Asserted by the power supply when the DC voltages are stable. MCUCLK -- Module control unit clock. 175 nanosecond square wave driven by the CPU to provide master timing to all PCAs. HSREQ -- High-speed request. Asserted by the multiplexer channel to request service from the IOP. The IOP initiates a data poll in response. DATAPOLL IN -- Data poll in. Asserted by the IOP to poll for the highest priority multiplexer channel that is requesting service. The signal is propagated to DATAPOLL OUT if the multiplexer channel is not requesting service. If it is, propagation is blocked, and the channel's transfer logic is enabled. DATAPOLL OUT -- Data poll out. Asserted by the multiplexer channel when it is polled but is not requesting service from the IOP. Multiplexer/Selector Channel Bus -------------------------------- CHANSO -- Channel service out. Asserted by the channel to qualify the programmed strobe signals during execution. Also asserted by the multiplexer channel to request the device number during initialization. SRCLOCK -- Service request clock. MCUCLK is buffered and driven by the channel on this line. DEVEND -- Device end. Asserted by the device controller when CHANSO is asserted in response to CHANSR or SRn to terminate a read or write operation that it considers to be retryable. ACKSR -- Acknowledge service request. Asserted by the multiplexer channel to clear all of the service request FFs on the serviced device controller. Tied inactive by the selector channel, as the device controller issuing the SR is always the one serviced. CHANACK -- Channel acknowledge. Asserted by the multiplexer channel in response to SRn for the duration of the DATAPOLL; indicates that the multiplexer channel has control of the IOP. Asserted by the device controller in response to CHANSO from the selector channel. DEVNODB -- Device number data base. Asserted by the multiplexer channel to enable the device controller to place its device number on the DEVNO bus. Tied inactive by the selector channel. SIOENABLE -- Start I/O enable. Asserted by the selector channel to qualify the SIO OK status returned to the CPU by the device controller. If SIOENABLE is denied, the CPU will not start another SIO program, as this indicates that the selector channel is already in use. Tied active by the multiplexer channel, as it supports multiple concurrent SIO programs. EOT -- End of transfer. Asserted by the channel to indicate that the word count of the current transfer has expired. JMPMET -- Jump met. Asserted by the device controller to indicate that the jump condition is true. If the current order is a conditional jump, the controller will execute it if JMPMET is asserted and ignore it if JMPMET is denied. TOGGLEINXFER -- Toggle input transfer. Asserted by the channel to prepare the device controller for inbound (read) data transfer, or to terminate the transfer at the end of a chained operation or single transfer sequence. CHANSR -- Channel service request. Asserted by the device controller to request selector channel continuation of the SIO program. The channel responds with CHANSO and the appropriate strobe(s) to service the request. Not used by the multiplexer channel (pin is used for TOGGLESR). TOGGLEOUTXFER -- Toggle output transfer. Asserted by the channel to prepare the device controller for outbound (write) data transfer, or to terminate the transfer at the end of a chained operation or single transfer sequence. TOGGLESIOOK -- Toggle SIO OK. Asserted by the channel to end SIO operations in the device controller. Returns to the controller to an idle state. TOGGLESR -- Toggle service request. Asserted by the multiplexer channel after initialization and before the first SIO command execution to clear the Service Request FF on the device controller. Not used by the selector channel (pin is used for CHANSR). XFERERROR -- Transfer error. Asserted by the channel to terminate the SIO program due to an invalid channel state, a memory or system parity error, an illegal address (beyond the memory capacity), or an I/O timeout (controller not responding). REQ -- Request. Asserted by the device controller in response to an SIO command. Starts the initialization sequence in the selector channel or combines with a service request to request an initialization sequence in the multiplexer channel. If this signal is asserted while the selector channel is busy, it will abort the SIO program. SR0-15 -- Selector channel data bus. Bidirectional. Once a device controller is connected to the selector channel for SIO operation, all data transfers occur on this bus. SR0-15 -- Multiplexer channel service request 0-15. Bidirectional. Asserted by the device controller to request service from the multiplexer channel. Force-denied by the multiplexer channel to inform the device controller that it is being serviced (i.e., the controller will have its SR Buffer FF set but its assigned SR line clear when the channel is acknowledging). PCMD1 -- Program command 1. Asserted by the channel to strobe the first control word into the device controller and to set the controller command logic to generate a service request for the second command word. Generated by a Control order. SETJMP -- Set jump. Asserted by the channel to allow the device controller to specify the jump condition via JMPMET. Generated by a Jump order. PSTATSTB -- Program status strobe. Asserted by the channel to strobe status data from the device controller onto the data bus. Generated by a Sense or End order. PCONTSTB -- Program control strobe. Asserted by the channel to strobe the second control word into the device controller and to clear the controller command logic. This signal always follows a PCMD1 assertion. Generated by a Control order. READNEXTWD -- Read next word. Asserted by the channel to initiate a transfer of a data word from the device to the device controller. PWRITESTB -- Program write strobe. Asserted by the channel to strobe write data on the data bus into the device controller. This signal also sets the controller logic. SETINT -- Set interrupt. Asserted by the channel to set the interrupt request logic in the device controller. Generated by an Interrupt or End/Interrupt order. PREADSTB -- Program read strobe. Asserted by the channel to strobe read data from the device controller onto the data bus. This signal also sets the controller logic. ============== HP-IB Machines ============== ----------- Main Memory ----------- [from the Series 44 R/T manual] Main memory is implemented by a Memory Control and Logging (MCL) board and one to eight Semiconductor Memory Arrays (SMAs). Memory is arranged as 39-bit words consisting of 32 data bits and 7 check bits. The MCL can control from one to eight SMAs, with each SMA providing 128K words using 16K RAMs or 512K words using 64K RAMs. Two MCLs are supported, though only one is needed if using 64K SMAs, as the maximum supported memory is 4096K words, due apparently to power supply limitations. The MCL sits on the IMB and is controlled by IMB memory commands. Four operations are supported: Read, Write, Read/Write Ones, and Command and Status. Memory Read retrieves the 32-bit word and places either the upper or lower 16 bits on the IMB; the lower address line (A15) on the IMB determines which half is used. Memory Write consists of a read, upper or lower half replacement, and a write back. The Read/Write Ones command reads a 16-bit location and then writes an all-ones word back to that location in an atomic operation. The Memory Command and Status (MCS) operation controls the MCL and obtains status from it. The MCL contains an Error Logging Array (ELA) that stores information on all correctable (single-bit) and uncorrectable (double-bit) errors in the SMAs. A read with a correctable error causes the word to be rewritten with the corrected value; no IMB error is indicated. An uncorrectable error asserts the PER (parity error) signal on the IMB. As Write is actually a read-modify-write cycle internally, both it and the Read/Write Ones commands abort the write part if the read has an uncorrectable error. Read/Write Ones asserts PER. The signal is not asserted for a Write, but the error is logged, and PER will be asserted on the next Read or Read/Write Ones as an indication that an error occurred. The ELA is readable via the MCS operation. The ECC check bits are normally generated by the MCL. However, they may also be supplied by an Alternate Check Register that is loaded by an MCS operation. If non-existent memory is read, an all-ones word is returned with no error. If a memory location on a partially populated SMA is read that is not populated by RAM chips, an all-zeros word is returned with no error. ------------------------- Memory Command and Status ------------------------- The MCS operation involves two extra registers on the MCL: the Alternate Check register (ACR) and the Alternate Status Register (ASR). These registers are loaded on the execution of each MCS operation. Only the ASR is cleared by assertion of the IMB PON (Power On) or SRST (System Reset) signals, or by the RESET switch located on the MCL. The MCS operation behaves as a read operation, in that the CPU establishes a value on the IMB address bus and receives data on the data bus. The address, however, is decoded into fields, as follows: ADRE 8 7 | 6 5 4 | 3 2 1 +---+---+---+---+---+---+---+---+ | - | - | - | ELA Address | +---+---+---+---+---+---+---+---+ ADR 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | ELA Address | - | - | Alternate Status Reg | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Alternate Check Reg | - | - | - | - | - | - | - | - | - | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ The ELA Address and the Alternate Check Register contents are loaded simultaneously from the same address bus value. The content of the ELA specified by the address is read out and returned in Status Regieter bit 8. The Alternate Status Register bits are defined as follows: 10 = Disable PER 11 = Disable all error logging 12 = Disable read error correction 13 = Use the ACR on susbsequent writes 14 = Write bit 15 into the specified ELA Address 15 = Data bit to be written to the ELA Disabling PER logs single-bit errors but does not log double-bit errors; the latter are reported in bit 9 of the status word. Disabling all error logging reports single-bit errors in bit 10 and double-bit errors in bit 9 of the status word. The Alternate Check Regster value is substituted for the normal ECC generation if ASR bit 13 is set. Setting both bits 10 and 12 causes subsequent writes to initialize both upper and lower memory values to the value supplied by the data bus and to generate correct ECC bits; error logging is inhibited, i.e., no read precedes the write. If bit 13 is also set, then the ACR is used instead of the generated ECC check bits. Writing into the ELA also returns the previous bit value in bit 8 of the status word. The MCS operation returns the value of the Status Register on the data bus. The register assignments are as follows: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | ECC Check Bits | R | E | U | C | 0 1 0 0 N | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: R = RAM type (0/1 = 16K/64K) E = Data bit from the specified address in the ELA U = Uncorrectable error occurred since last MCS C = Correctable error occurred since last MCS N = Controller number (0/1 = first/second controller) The controller number is 0 for the first (16K RAM SMAs) or only (64K RAM SMAs) controller and 1 for the second 16K RAM SMA controller. ------------ System Clock ------------ The HP-IB machines do not have a dedicated hardware counter for the process clock, nor is there a dedicated hardware timer with a programmable interrupt interval for the time-of-day clock. Instead, there is a simple 1 msec. CPU counter that provides periodic interrupts that the firmware intercepts and uses to provide a software process clock and a software programmable timer. PDF page 13 of the HP 3000 Series 3x/4x Computer Systems Engineering Diagrams Set (30090-90034) shows a 256 KHz oscillator that drives a divide-by-256 counter (two 74LS393 4-bit counters in sequence). The MSB of the counter clocks a 74S74 flip-flop whose D-input is pulled up to +5V and presented on connector J2 pin 34. This is connected to the output of a register on the CMP board, which presumably can pull the line low to disable the timer for diagnostics. On each rising edge of the counter output, i.e., every millisecond, the flip-flop sets, driving its ~Q output low. The output drives one input of a 74S30 8-input NAND gate whose (interrupt) output eventually is presented as a test condition to the microcode, as well as bit 1 of the Status and Interrupt Register. The flip-flop remains set until bit 1 of the SIR is written with a zero value. It appears that the counter interrupts the firmware continuously every millisecond, but the firmware generates a system clock interrupt (STT %14) every 100 counter interrupts during MPE operation. ----------------------------- Status and Interrupt Register ----------------------------- The Status and Interrupt Register (SIR) replaces the CPX1 and CPX2 registers on the Series 4x machines. The format is: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | O | K | - | - | - | I | C | E | - | - | - | - | D | S | L | H | write +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | O | K | C | I | R | F | V | M | T | G | A | N | D | S | L | H | read +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where (for writing, action occurs when bits are set to zero): O = Clear Reset and set Run flip-flops K = Clear CPU timer flip-flop I = Set the interrupt-disable flip-flop C = Clear the interrupt-disable flip-flop E = Clear the parity error flip-flop D = Set dispatch flag S = Set ICS flag L = Set SS flag H = Set Run/Halt indicator to CMP Where (for reading): O = CPU is released from reset K = CPU timer tick C = IMB CSRQ I = IMB IRQ R = CPU is up and running F = IMB power fail warning V = Integer overflow trap (T * O) M = Memory parity error T = IMB timeout G = Toggle RUN/HALT from control panel A = Disable Attention FF N = IMB DNV D = Dispatcher flag (0) S = ICS flag (0) L = Split-Stack flag (0) H = Run/Halt indication to CMP (0/1) Note that bits 12-15 are negative logic, i.e., 0 = the active condition. The "SS Flag" is set for split-stack operation. The Series III determines this if DBANK <> SBANK or DB > Z or DB < DL, and this test is made everywhere split-stack operation is possible. For the Series 64, the microcode sets a split-stack flag (as "FSS") when SBANK is set differently from DBANK (such as SBANK = 0 during an ICS interrupt, or DBANK = 0 for an external interrupt, or duing IXIT or SETR). So this is likely for the 4x/5x as well, as the checks would be faster (although it looks as though the SS flag only records the bank difference; the other two checks are still made explicitly). ------------------------- Interrupt Classifications ------------------------- The segment transfer table (STT) for segment 1 (internal interrupts) changes for the HP-IB machines, as follows: Maintained: Label STT Param Stack Source Type ------ --- ------ ----- ------ ---------------------- (DRT) - devnum ICS SIR.3 External Interrupt 100401 1 label user abort Bounds Violation 101001 2 label user SIR.11 Illegal Memory Address 101401 3 label user SIR.8 Non-Responding Module 103001 6 label ICS SIR.7 Data Parity Error 104401 11 label ICS SIR.5 Power Fail No longer used: Label STT Param Stack Source Entry ROM Type ------ --- ------ ----- ------ ----- ---- -------------------- 102001 4 label ICS CPX1.4 IR 3001 System Parity Error 102401 5 label ICS CPX1.5 IR 3001 Address Parity Error 103401 7 module ICS CPX1.7 IR 3001 Module Interrupt Added: Label STT Param Stack Source Type ------ --- ------ ----- ------ ------------------------------- 104001 10 -- - -- Call Procedure Help 105001 12 -- - -- Temperature Warning (Series 64) 105401 13 -- - -- Unknown External Interrupt 106001 14 -- ICS SIR.1 System Clock 106401 15 -- - -- Breakpoint 107001 16 -- - -- Power Fail (Series 37) 107401 17 -- - -- DCU Logging (Series 64) ======== Starfish ======== References: - 30090-90001 HP 3000 Series 40/44 Reference/Training Manual IMB and GIC, pages 36-41 and 118-147. - 30090-90034 HP 3000 Series 3x/4x Computer Systems Engineering Diagrams Set IMBA and GIC, pages 66-70 and 71-76. - 30000-90141 HP 3000 Series III Engineering Diagrams Set Port Controller, pages 119-121. - 30070-90009 HP 3000 Series 33 Engineering Diagrams Set Processor, BIC, and GIC, pages 95-97, 106-108, and 116-120. - 32002-90004 Console Operator's Guide Series II, III, 30, 33, and 44 pages 32-35 and 184-199. - 30000-90014 MPE IV System Manager/System Supervisor Reference Manual pages 138, 199, 286, 293, 298. - HP 3000 Series III CE Handbook (30000-90172, July 1981) [pp. 111 and 237-244]. - 30341-60001 HP 30341A HP-IB Interface Module Diagnostic Manual Set - 30341-90003 Preface To The HP 30341A HP-IB Interface Module Diagnostic Manual Set - 30341-90005 Diagnostic Utility System III Reference Manual - 30341-90006 AID Diagnostic Language Reference Manual - 30341-90007 Sleuth Simulator Diagnostic Language Reference Manual - 30341-90008 IOMAP Diagnostic Reference Manual - 30341-90009 General I/O Channel (GIC) Diagnostic Manual - 30341-90010 HP 7976A Magnetic Tape Unit Diagnostic Loader - 30341-90013 HP 2680A Page Printer Verifier Diagnostic Manual (Need) - 30000-90136 3000 Series III Computer System Microprogram Listing (cold load) - 30070-90006 3000 Series 33 Microcode Manual (CPP) - 30090-90004 3000 Series 40/44 Computer System Microcode Manual (CPP) - 30341-90002 HP 30341A HP-IB Interface Module Reference/Training Manual - HP 300 I/O ERS (channel program descriptions) The HP 30341A HP-IB Interface Module ("Starfish") connects HP-IB devices to the Series III. Supported devices are the HP 7933 CS/80 disc drive, the HP 7976 1/2-inch magnetic tape drive, and the HP 2680 laser page printer. A small, rack-mounted chassis houses the module and contains these PCAs: - 30340-60002 Intermodule Bus Adapter (IMBA) - 30070-60012 Processor - 31000-60053 Bus Interface Controller (BIC) - 31262-60001 General I/O Channel (GIC) - 30340-60001 Backplane (6 position) The IMBA connects via flat ribbon cables to the Series III IOP bus, the IOP/Power bus, and to an additional 30030-60020 Port Controller installed in the Series III chassis. The Processor is a Series 33 processor card containing modified firmware that implements the Channel Program Processor and Series 33 I/O instruction set. The BIC and GIC are standard Series 33 cards. Graphically, the module appears as follows: Intermodule Bus +---------------+ +------------+-----------+----------------+ | | | | | | | | | | | | +-----------------+ +-------------+ +-----------+ +-----+ +-----+ | | | | | | | | | | | Port Controller | | IMB Adapter | | CPP / BIC | | GIC | | GIC | | | | | | | | | | | +-----------------+ +-------------+ +-----------+ +-----+ +-----+ | | | | | | | | +-------------+ ----+---- +-------------+ +-------------+ | | IOP Bus | | | | | Main Memory | IOP/Power Bus | HP-IB Discs | | HP-IB Tapes | | | | | | | +-------------+ +-------------+ +-------------+ The IMBA is permanently assigned device number 125 (octal 175). The module is designed to run HP-IB channel programs to control the devices attached to the GIC. Communication between the Series III and the GICs is controlled by executing SIO instructions directed at the IMBA and specifying an SIO channel program address of -1 (177777 octal). This causes the CPP firmware running on the Processor card to examine a "mailbox" consisting of the Device Reference Table entries for devices 126 and 127, which are dedicated to the Series III multiplexer channels but are otherwise unused. The eight-word mailbox resides at memory addresses 770-777 octal. Mailbox word 0 contains a code that designates the Series 33 I/O instruction to execute. For the SIOP instruction, mailbox word 3 contains the address of the HP-IB channel program that directs operation of the designated GIC device. Interrupt requests from the channel program are reflected back through the IMBA to the Series III. The following devices are mentioned in HP manuals as supported: Model Description Count Manual ----- ------------------ ----- -------------------- 7933 CS/80 disc drive 1 30000-90014 Dec 1982 7935 CS/80 disc drive 1 5953-7428 Feb-1982 7976 1/2" tape drive 1 30000-90014 May 1981 2680 Page printer 2 30000-90014 May 1981 The following devices would appear to work, based on the construction of the associated MPE drivers (i.e., they execute SIOP, etc. through the IMBA rather than as hardware instructions): Model Description Driver ----- ------------------ -------- 7911 CS/80 disc drive HIOMDSC2 7912 CS/80 disc drive HIOMDSC2 7905 MAC disc drive HIOMDSC1 7906 MAC disc drive HIOMDSC1 7920 MAC disc drive HIOMDSC1 7925 MAC disc drive HIOMDSC1 2608 Line printer HIOLPRT0 2619 Line printer HIOLPRT2 7970E 1/2" tape drive HIOTAPE0 --------------- Intermodule Bus --------------- References: - HP 3000 Series 40/44 Computer Systems Reference/Training Manual (30090-90001 July 1981) [pp. 36-41] - HP Series II III 30 33 44 MPE III-IV Binder [p. 58] The Intermodule Bus (IMB) consists of 78 lines, categorized as follows: - 3 operation - 24 address - 17 data - 7 handshake - 9 control - 12 priority - 6 power The lines are as follows: Operation ~~~~~~~~~ [T] OP0-2 -- Bus opcode. Asserted by the bus master to indicate the requested operation by the bus slave. Slave is either memory or a channel. When a channel opcode is asserted, DATA0-15 provide the channel command. Address ~~~~~~~ [T] ADR0-15 -- Address Bus, MSB is ADR0. [T] ADRE1-E8 -- Address Extension Bus, MSB is ADRE8. Data ~~~~ [T] DATA0-15 -- Data Bus, MSB is DATA0. ? [.] PARITY -- ? Handshake ~~~~~~~~~ [I] BRQ -- Bus Request. Asserted by any channel to request access to the bus from the CPU. A true PRI and BRQ are required to request the bus. [O] BACK -- Bus Acknowledge. Asserted by the CPU to acknowledge release of the bus to the channel asserting BRQ. Simultaneous bus requests are resolved by delaying the response to BRQ to allow time for priority chain propagation to disable lower-priority channels. [B] ADO -- Address Do. [B] ADN -- Address Done. [B] DDO -- Data Do. [B] DDN -- Data Done. [.] DNV -- Data Not Valid. Asserted to indicate that a read cannot be satisfied. Examples are attempting to read the GIC FIFO when it is empty, or attempting to read PHI registers while DMA is active. Control ~~~~~~~ [I] WAIT -- Wait. [I] IRQ -- Interrupt Request. [I] CSRQ1 -- Channel Service Request 1. [I] CSRQ2 -- Channel Service Request 2. [O] PER -- Parity Error. [.] SRST -- System Reset. [I] PON -- Power On. [I] PFW -- Power Fail Warning. Priority ~~~~~~~~ [.] PRI0-9 -- Priority In. There are 10 PRI signals, and all must be true to be granted bus access. On the channel card, each PRI is pulled up. A tree structure is build into the backplane to establish priority as a function of the location of the card on the bus. [.] PRO -- Priority Out. Asserted when idle; denied when a channel wants the bus. This prevents access to the bus by lower-priority channels. [.] PCRY -- Priority Carry. Asserted if the module's PRO is asserted and all 10 PRI signals are asserted. --------------- IMB Assignments --------------- Controllers installed on the IMB are configured to respond to the following channel addresses (HP 3000 HP-IB Version Computer Systems CE Handbook, 30070-90010 May 1987): Channel Address Description ------- ------------------------------------ 1 ADCC 1 (console, terminals 1-3, 4-7) 2 ADCC 2 (terminals 8-11, 12-15) 3 ADCC 3 (terminals 16-19, 20-23) 4 ADCC 4 (terminals 24-27, 28-31) 9 GIC 2 (backup device, e.g. 7970E) 11 GIC 1 (system disc, e.g., 7925M) 12 GIC 3 (cartridge tape, line printer) 13 GIC 4 (2680 laser printer) The 30340-60002 Intermodule Bus Adapter (IMBA) is hard-wired to respond to channel address 1. The general assignments are: Channels Device Types -------- --------------------------- 1-8 Terminals 9 Tape Drive 10 Tape Drive 11 System and Peripheral Discs 12 Line Printer 13 Laser Printer Low-speed devices, such as the 7970E tape drives, cannot be on the same channel as high-speed devices, such as the system disc. ------------ IMB Commands ------------ IMB commands are defined by an operation code asserted on OP0-OP2. For memory reads and writes, ADRE8-E1 and ADR0-15 give the 24-bit address, and DATA0-15 supply or accept the 16-bit data, respectively. For I/O commands, ADR0-15 give the command code, register number, and channel number, and DATA0-15 supply or accept the 16-bit data, respectively. The command format is: IMB Command Code Format: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Command | Register | - | Channel | - - - | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ The IMB command set is: Mnemonic Opcode Command Operation -------- ------ ------- -------------------------------- -- 000 -- Memory Read -- 001 -- Memory Read/Write Ones -- 010 -- Memory Write -- 011 -- (reserved) -- 100 -- I/O Read RIOC 100 0000 Read I/O Data OBII 100 0010 Obtain Interrupt Information OBSI 100 0100 Obtain Service Information -- 100 0110 (reserved) IPOLL 100 1000 Interrupt Poll ROCL 100 1010 Roll Call SPOL1 100 1100 Service Poll 1 SPOL2 100 1110 Service Poll 2 -- 101 -- Memory Write Control/Read Status -- 110 -- I/O Write WIOC 110 0000 Write I/O Data INIT 110 0010 Initialize Channel SIOP 110 0100 Start I/O Program HIOP 110 0110 Halt I/O Program SMSK 110 1000 Set Interrupt Mask IOCL 110 1010 I/O Clear -- 110 1100 (reserved) -- 110 1110 (reserved) -- 111 -- (reserved) Note that although the command code is four bits wide, the LSB is always 0 and is usually not decoded in hardware. Global commands have bit ADR bit 0 = 1 and omit the channel number. All channels respond to these commands. Local commands have ADR bit 0 = 0 and only the channel addressed by ADR9-12 will respond. The value present on DATA0-15 depends on the I/O command. Data is channel-dependent for the Read I/O Data and Write I/O Data commands, and is not used for the I/O Clear command. The command and data formats are as follows: RIOC -- Read I/O Channel 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 0 0 0 | Register | - | Channel | - - - | ADR +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Register Value | DATA +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ The value of the addressed register is returned on the DATA lines. OBII -- Obtain Interrupt Information: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 0 1 0 | - - - - | - | Channel | - - - | ADR +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 0 0 0 0 0 0 0 | N | Channel | Device | DATA +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: N = Channel and device numbers are not valid Obtain Interrupt Information is issued to the highest-priority channel that is asserting IRQ, as determined by the Interrupt Poll command. The channel returns the number of the highest-priority device that has an interrupt pending. The returned word is used to determine the DRT entry for the external interrupt. If the Not Valid bit is set, the Channel and Device numbers are invalid, as no interrupt is pending. [ ucode p 28 ] OBSI -- Obtain Service Information: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 1 0 0 | - - - - | - | Channel | - - - | ADR +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 0 0 | T | A | S | D | C | N | Channel | Device | DATA +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: T = Timeout A = DMA Abort S = SRQ Request D = Device Request C = Channel Request (including DMA completion) N = Not Valid The response indicates the channel and device requesting service from the controller and the reason for the request. IPOLL -- Interrupt Poll: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 0 0 0 | - - - - | - | - - - - | - - - | ADR +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | I | I | I | I | I | I | I | I | I | I | I | I | I | I | I | I | DATA +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Interrupt Poll is issued in response to IRQ assertion. Each channel that is asserting IRQ asserts the DATA line corresponding to its channel number. ROCL -- Roll Call: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 0 1 0 | - - - - | - | - - - - | - - - | ADR +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | P | P | P | P | P | P | P | P | P | P | P | P | P | P | P | P | DATA +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Each channel that is present on the IMB asserts the DATA line corresponding to its channel number. SPOL1 -- Service Poll 1: SPOL2 -- Service Poll 2: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 1 x 0 | - - - - | - | - - - - | - - - | ADR +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | R | R | R | R | R | R | R | R | R | R | R | R | R | R | R | R | DATA +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Each channel that is asserting CSRQ asserts the DATA line corresponding to its channel number. WIOC -- Write I/O Channel 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 0 0 0 | Register | - | Channel | - - - | ADR +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Register Value | DATA +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ The value present on the DATA lines is written to the addressed register. INIT -- Initialize Channel 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 0 1 0 | - - - - | - | Channel | - - - | ADR +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - - - - - - - - - - - - - - - - | DATA +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Initialize Channel causes the specified channel to reset its state. The value on the DATA lines is ignored. SIOP -- Start I/O Program HIOP -- Halt I/O Program 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 1 x 0 | - - - - | - | Channel | - - - | ADR +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - - - - - - - - - - - - | S | Device | DATA +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: S = New status (0 = set CSRQ/1 = clear CSRQ) An SIOP or HIOP with S = 0 causes the channel to assert CSRQ and set bit 6 (device request) in the OBSI response. SMSK -- Set Interrupt Mask 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 0 0 0 | - - - - | - | - - - - | - - - | ADR +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | M | M | M | M | M | M | M | M | M | M | M | M | M | M | M | M | DATA +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ The DATA bit corresponding to the channel's assigned address disables (0) or enables (1) channel interrupts by inhibiting or allowing IRQ assertion. IOCL -- I/O Clear 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 0 1 0 | - - - - | - | - - - - | - - - | ADR +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - - - - - - - - - - - - - - - - | DATA +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ I/O Clear causes all channels to reset their state. The value on the DATA lines is ignored. ----------- IMB Adapter ----------- References: - HP 3000 Series III Engineering Diagrams Set (30000-90141, April 1980) [pp. 119-121] - HP 3000 Series 40/44 Computer Systems Reference/Training Manual (30090-90001 July 1981) [pp. 36-41] - HP 3000 Series 39/40/42/44/48 Computer Systems Engineering Diagrams Set (30090-90034, October 1984) [pp. 66-70] The IMBA responds to four of the eight I/O commands presented on the IOP bus: IOCMD Internal Inst 0 1 2 Signal Action ---- - - - ---------- --------------- CIO 0 0 1 DCONTSTB Control I/O SIO 0 1 0 (STARTIO) Start I/O IXIT 1 0 0 RESETINT Reset Interrupt TIO 1 0 1 DSTATSTB Test I/O Commands are enabled on the IMBA when the DEVNO lines present either 175 octal (the device number of the IMBA) or 200 octal + the contents of the DEVNO response register. The register value is set in response to an IMB WIOC command, as described below. The CIO and TIO words are structured as follows: IMBA Control Word Format (CIO): 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | M | - - - - - - - - - - - - - - - | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: M = master reset Master reset performs these actions: - clears the CSRQ flip-flop - clears the INTREQ flip-flop (via DIPOLL) - clears the IMB handshake flip-flops - clears the IMB parity error flip-flop Master reset is also initiated by asserting PON or IORESET on the IOP bus, and by an IMB IOCL command. IMBA Status Word Format (TIO): 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | S | D | V | - - - - - - - - - - - - - | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: S = SIO OK (CSRQ flip-flop is clear) D = direct read/write I/O OK (always 1) V = +5 volts is present on the Intermodule Bus RESETINT clears the INTACK flip-flop. SIO sets the CSRQ flip-flop, which asserts CSRQ1 on the IMB. The IMBA decodes five IMB commands: Opcode Command Mnemonic Operation ------ ------- -------- -------------- 000 -- -- Memory Read 010 -- -- Memory Write 100 110x SPOL1 Service Poll 1 110 000x WIOC I/O Write Data 110 101x IOCL I/O Clear SPOL1 gates the CSRQ flip-flop onto IMB DATA1 line. Assertion indicates that channel 1 (the IMBA) is asserting CSRQ1. It also clears the CSRQ flip-flop at the end of the command. WIOC is additionally qualified by channel 1, i.e., the IMBA address. Assertion writes IMB DATA9-15 into the DEVNO response register and sets the interrupt request flip-flop. The response register is gated onto the DEVNO lines when INTPOLLIN is asserted, so that the interrupt handler is selected from the DRT of the appropriate GIC device, rather than from the IMBA DRT. The MSB (DATA8) of the IMB WIOC data word is not stored in the register. During INTPOLLIN, DEVNO0 is set to 0. During IOP command decoding, DEVNO0 is compared to 1, effectively adding 200 octal to the register value for the comparison. This is odd, as device numbers are restricted to 000-177 octal, even though the bus is eight bits wide. Otherwise, the interrupt flip-flops are standard. IOCL asserts Master Reset to the IMBA. Note that the IMBA does not respond to ROCL. ------------------ Interrupt Requests ------------------ An interrupt request is generated when the IMB IRQ line is asserted. An HP-IB CPU responds with this sequence after saving the user's environment on his stack and setting up the ICS: 1. Issue an IPOLL command to determine the channel that asserted IRQ. A system halt %16 occurs if no channel responds (i.e., the IRQ is spurious). 2. Issue an OBII command to highest-priority channel that responded to the IPOLL command to determine the device that requested the interrupt. 3. Set DB Bank to zero, and set DB from word 1 of the corresponding Device Reference Table entry. 4. Set the Status register to privileged mode and reenable interrupts. 5. Push the Channel/Device number on top of the ICS. 6. Clear the IRQ by writing the device number to channel register C and save CIR in the X register. 7. Get the external program label from word 2 of the DRT. 8. Set up code segment 1 for the external interrupt. For the Starfish, an IMB interrupt request is handled by the CPP microcode and results in a WIOC issued to the IMBA to assert IRQ to the Series III CPU. The sequence is modified from the above as follows: 1. Issue an IPOLL command to determine the channel that asserted IRQ. If no channel responds (i.e., the IRQ is spurious), the request is ignored. [???] 2. Issue an OBII command to highest-priority channel that responded to the IPOLL command to determine the device that requested the interrupt. 3. Clear the IRQ by writing the device number to channel register C. 4. Issue a WIOC command to the IMBA, passing the Channel/Device number as the data value. This causes the IMBA to assert IRQ on the IOP bus. From there, the normal Series III external interrupt actions occur. ------------------- General I/O Channel ------------------- References: - HP 3000 Series 40/44 Computer Systems Reference/Training Manual (30090-90001, July 1981) [pp. 129-147] - HP 3000 Series 39/40/42/44/48 Computer Systems Engineering Diagrams Set (30090-90034, October 1984) [pp. 71-75] - HP 3000 Series 64/68 Computer Systems Engineering Diagrams Set (30140-90046, April 1984) [pp. 135-139] - "A Computer Input/Output System Based on the HP Interface Bus" (HP Journal, July 1979) [pp. 9-13] - HP 13255 HP-IB Interface Module (13255-91128, April 1979) [pp. 19-37] - "PHI, the HP-IB Interface Chip" (HP Journal, July 1978) [pp. 16-17] The GIC consists of a PHI (Processor to HP-IB) chip, a DMA sequencer, and bus request and handshake circuitry. It connects to the IMB on one end and the HP-IB on the other. It can drive up to eight HP-IB devices. Switch Positions ~~~~~~~~~~~~~~~~ The switch positions are described in the CE Handbook (30070-90010) on page 9-23: Switch Choices Setting Action Alternate Action ------ --------- ------- -------------------- ------------------- S1 CPU/CPP CPU Asserts CSRQ1 Asserts CSRQ2 S2 A/B A Denies HYBRID Asserts HYBRID S3 OFF/ON ON Asserts SCTRL to PHI Denies SCTRL to PHI S4 0-15 11 Sets channel number (not applicable) S5 OPER/TEST OPER Denies DIAGSW Asserts DIAGSW SW1 position A corresponds to the CPU position, and position B corresponds to the CPP position. The description of SW2 includes, "In the normal (A) position, the system performs unit identification during power up (PON)." The signal is reflected in bit 1 of Register E and is presented on pin J1-44 but otherwise has no effect on the GIC. SW3 determines whether or not the PHI is the system controller. SW4 sets the channel number to which the GIC responds. Channel 0 is illegal, channel 1 is reserved for the ADCC, and channel 15 is reserved for the IMBA (as devices 5-7 of that channel correspond to the DRT mailbox locations). The description of SW5 includes, "When set to TEST, the GIC diagnostic can be run. Also, this mode allows the DMA state machine to be single-stepped by clocking the slave flip-flop, prevents a CSRQ command from being issued, and disables the one-second timeout." New Status Register ~~~~~~~~~~~~~~~~~~~ Setting a bit in the New Status register will assert CSRQ for a Device Request only if the NSEN (New Status Enable) signal is asserted. This occurs under the following conditions: NSEN = CIC * ~CSRQDIS * DMAINACT * ATNB * EOIB * ~OBSIDOF * ~DMARQPLA + ~CIC * ~CSRQDIS * DMAINACT That is, NSEN is asserted when: - The PHI is the controller-in-charge and CSRQ is not disabled and DMA is inactive and a parallel poll is in progress (ATN and EOI are asserted) and the PHI is not interrupting for a PPR when an OBSI is received and the inbound FIFO is empty, or - The PHI is not the controller-in-charge and CSRQ is not disabled and DMA is inactive. With NSEN asserted, decoding of the New Status register is enabled to assert a channel request (CSRQ) on behalf of the device (DEVRQ). Timeout ~~~~~~~ The GIC has a one-second watchdog timer, consisting of an astable 555 timer running at 15 Hz and a 4-bit binary down counter that sets a flip-flop to assert the TIMEOUT signal when the counter underflows. This signal causes a DMA abort (identical to writing to Register E), forces a PHI interrupt and thus a channel request, and presents on bit 3 of Register F. The timer is inhibited by DIAG signal assertion, which occurs when SW5 is in the TEST position and bit 12 of Register B or F is zero. The counter preset signal is controlled by a 3-3-2-2 AOI gate. The counter is held in a preset state if the AOI gate is low, which occurs if the output of any of the four AND gates is high. The equation is: PRESET = DMAINACT * ~CSRQDIS + DMAENF * DMARQPLA + MYCSRQ * ~TIMEOUT + CLRERR ...where CLRERR is PONINCL + DMAINACT * WREG11. That is, PRESET is asserted when: - DMA is inactive and CSRQ is enabled for parallel poll response (i.e., Register B/F bit 8 is 0), or - DMA is enabled and the PHI is requesting a DMA cycle, or - Channel service is requested and timeout has not occurred, or - Power-on or INIT or IOCL or a write to Register B with DMA inactive occurs. The latter three signals are pulses; the first is asserted continuously. In the idle state, the timer is frozen if CSRQDIS is clear and released to run if CSRQDIS is set. If DMA is active, then each DMA cycle will reset the counter to its initial state. Should a DMA cycle hang, the timer will eventually expire. The timer is also cleared each time channel service is requested, unless it was for a timeout. Finally, an I/O clear will reset the timer. The IOMAP program sets bit 8 is Register 15 to assert CSRQDIS before initiating the HP-IB Identify sequences. This ensures that sending Identify sequences to absent device addresses will not hang. IMB Commands ~~~~~~~~~~~~ The GIC decodes 13 IMB commands: Mnemonic Opcode Command Operation -------- ------ ------- ---------------------------- RIOC 100 0000 Read I/O Data OBII 100 0010 Obtain Interrupt Information OBSI 100 0100 Obtain Service Information IPOLL 100 1000 Interrupt Poll ROCL 100 1010 Roll Call SPOL1 100 1100 Service Poll 1 SPOL2 100 1110 Service Poll 2 WIOC 110 0000 Write I/O Data INIT 110 0010 Initialize Channel SIOP 110 0100 Start I/O Program HIOP 110 0110 Halt I/O Program SMSK 110 1000 Set Interrupt Mask IOCL 110 1010 I/O Clear INIT, IOCL, and the IMB SRST signal all cause the GIC to reset its internal state. SMSK clocks the data bus bit (3000 numbering) corresponding to the channel address into the Mask flip-flop. The output of the flip-flop gates the IRQ line, so that IRQ assertion is allowed only when the corresponding mask bit is set. Data Not Valid ~~~~~~~~~~~~~~ The GIC asserts DNV in response to a register read or write under either of these conditions: - Reading or writing Registers 0-7 while DMA is active. - Reading Register 0 while the inbound FIFO is empty if not conducting a parallel poll and the DMA direction is inbound or the outbound FIFO is full. For the latter case, the PHI will set the Handshake Abort bit in Register 2 and return an arbitrary value. However, DNV is inhibited if the DMA direction is outbound and the outbound FIFO is not full (DMARQPLA signal is asserted). An RIOC instruction that receives DNV from the interface will set CCL [per S20S231A.SPL -- ADCC diagnostic source]. The 6x microcode IMB I/O routine [IOR p.216] recovers from a DNV received while reading the FIFO by waiting for inbound data availability [SUSB p.224]. Receipt of any other I/O error (e.g., parity error, timeout) results in a system halt %23, "I/O Error" [IOEE p.29]. Registers ~~~~~~~~~ The GIC has sixteen addressable registers -- eight provided by the PHI, and eight provided by the DMA sequencer. The sequencer is a state machine with 27 states. The five-bit state number is presented as bits 3-7 of Register 8. The GIC inverts register address bit 1 (bit 6 of the Command / Register / Channel IMB command word), so that this mapping occurs: IMB Register PHI Register IMB Register Description ------------ ------------ ------------------------------- 0 2 FIFO 1 3 Status 2 0 Interrupt Conditions 3 1 Interrupt Mask 4 6 Parallel Poll Mask 5 7 Parallel Poll Sense 6 4 Control 7 5 Address 8 - DMA Extended Address 9 - DMA Address A - DMA Byte Count B - DMA Status/Control C - Interrupt Register D - Interrupt Information E - Channel Configuration/DMA Abort F - Channel Service Information The 264x manual and the GIC schematic both show the PHI part number as 1AA6-6004. However, the descriptions of the registers does not always agree. Comments in the 264x manual suggest that the description in the Series 4x manual describes an earlier revision of the PHI chip, although why they should have the same part number is unclear. Differences between the manuals are noted in the respective register descriptions. The PHI registers (0-7) are each 10 bits wide. The PHI bus is connected to present these as a 16-bit value on bits 0-1 and 8-15, respectively. A soft reset (SRST) signal assertion on pin 15 clears all PHI registers except Register 1 (status). Register 0 - FIFO: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 0 | - - - - - - | parallel poll responses | read +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 1 | - - - - - - | 0 0 | T | secondary | read +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 0 | - - - - - - | data byte | read +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 0 | - - - - - - | final data byte | read +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 1 | - - - - - - | tagged data byte | read +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | E | 0 | - - - - - - | data byte | write +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 1 | - - - - - - | 0 | bus interface command | write +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | L | 0 | - - - - - - | receive count | write +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 1 | - - - - - - | 0 0 0 0 0 0 0 0 | write +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 1 | - - - - - - | 0 | receive count | write +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 1 | - - - - - - | 1 | send count | write +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: T = Talk secondary E = Tag byte with EOI L = Inhibit LF detection The PHI has an eight-byte outbound FIFO and an eight-byte inbound FIFO. If the inbound FIFO is empty and a read is performed, then if the PHI is the controller and has been conducting a parallel poll for at least two microseconds, then the poll responses will be read, masked and normalized by Registers 4 and 5. Otherwise, an indeterminate value is returned, and bit 9 (handshake abort) of Register 2 is set. Data bytes are received into the FIFO only when the PHI is addressed to listen. Secondaries are received only when the preceding bus command is is a Talk or Listen that addresses the PHI. If the inbound FIFO is full, the PHI holds off the handshake (NDAC asserted) until a byte has been read by the host. Bits 0 and 1 of the FIFO word indicate a the type of byte received -- a secondary, a data byte that is not the last byte of a transfer, a data byte that is the final byte of a counted transfer, or a data byte that is tagged with EOI or is a LF (if enabled). If the outbound FIFO is full and a write is performed, the FIFO contents are not altered, and and bit 9 (handshake abort) of Register 2 is set. If the outbound FIFO is empty while PHI is not the controller and is addressed to talk, the bus remains idle until a byte is written to the FIFO. If either the Outbound data freeze bit in Register 1 or the Device Clear bit in Register 2 is set, the FIFO will not be unloaded to the bus until both bits are cleared. Neither bit can set if the PHI is the controller. However, if either is set when the PHI becomes the controller, FIFO unloads are held off as before. When the outbound FIFO is empty, the PHI conducts a continuous parallel poll. Bit 10 (parallel poll response) of Register 2 is set if any device responds affirmatively during the poll. The poll terminates when a byte is written to the FIFO. The outbound FIFO is cleared when bit 15 (clear outbound FIFO) of Register 6 is set or the Soft Reset pin (pin 15, PON) is low. When the FIFO is cleared, a parallel poll begins immediately, asserting ATN and EOI. Caution must be exercised if a data byte is on the bus at that time, as it may be misinterpreted as a command. Bytes written to the FIFO are interpreted by the PHI in one of six modes, with bits 0 and 1 of each word partially indicating the mode. If the PHI is not the controller and is addressed to talk (mode 1), then data bytes are sent over the bus, optionally tagged with EOI. If the PHI is also addressed to listen, the bytes are loaded back into the inbound FIFO. However, bits 0 and 1 will be undefined, i.e., will not contain the last byte indicators. If the PHI is the controller and is addressed to talk (mode 2), then a bus interface command may be sent over the bus. The PHI will assert ATN with the command and will assert odd parity on DIO8 automatically. If the PHI is the controller and has addressed another device to talk, reception may be configured to end on a byte count or LF reception or a byte tagged with EOI (mode 3), or only when a byte tagged with EOI is received (mode 4); they represent counted and uncounted transfer enables, respectively. The words remove the ATN assertion after the Talk command when they are unloaded from the FIFO and inhibit the automatic parallel poll. The PHI will terminate either transfer when a byte tagged with EOI is received. Counted transfers additionally terminate when a LF character is received (if the inhibit bit is clear) or the number of bytes in the count field is received (a zero count specifies a 256-byte transfer). Counted transfers larger then 256 bytes may be specified by including additional transfer enable commands in the outbound FIFO buffer. Modes 5 and 6 are deprecated in the terminal interface manual but appear in the Series 4x manual. They are implemented by the PHI for backward compatibility. Register 1 - Status: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 0 0 0 0 0 0 0 | - - | R | C | S | T | L | F | read +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - - - - - - - - - - - - - - - | F | write +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: R = PHI is in remote mode C = PHI is the controller S = PHI is the system controller T = PHI is addressed to talk L = PHI is addressed to listen F = Outbound data freeze The data freeze bit is set whenever a byte enters the inbound FIFO. While it is set, it prevents data being sent from the outbound FIFO. Writing a 1 to this bit while the inbound FIFO is empty clears the freeze. NOTE: Bits 0 and 1 are stated as reading as zeros in the terminal interface manual but as ones in the Series 4x manual. Register 2 - Interrupt Conditions: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | I | P | 0 0 0 0 0 0 | C | H | R | S | F | D | E | L | read +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - | P | - - - - - - | C | H | - - - - - | L | write +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: I = Interrupt pending (OR of the other bits after masking) P = Parity error detected on received command C = Status has changed H = Processor handshake aborted due to FIFO overflow/underflow R = Parallel poll response is present S = Service Request (SRQ) is asserted on the bus F = Outbound FIFO is not full D = Data available in the inbound FIFO E = Outbound FIFO is empty L = Device Clear (DCL) universal command has been received Each bit in the register is associated with a particular interrupting condition but can be unconditionally masked off by setting the corresponding bit in Register 3. Bit 0 is the OR of the other bits after masking; when set, the PHI asserts IRQ continuously until the interrupt is reset, either by writing a 1 to the indicated bits, or by clearing or masking off the resulting condition. The processor handshake abort is set if the data transfer cannot be executed. In lieu of waiting, a FIFO operation completes without a real data transfer and is followed by an interrupt. Incorrect (even) parity on a received HP-IB command sets the parity error bit. If the parity freeze bit of register 6 is set, the command is not executed, and the HP-IB handshake is held off until the controller denies DAV; the July 1978 HP Journal article on the PHI states additionally that the DIO lines may be read during the freeze, but the 264x PHI description of the inbound FIFO register does not mention this. If the freeze bit is clear, the command is allowed to execute in spite of the bad parity. Register 3 - Interrupt Mask: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | I | P | 0 0 0 0 0 0 | C | H | R | S | F | D | E | L | read +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | I | P | - - - - - - | C | H | R | S | F | D | E | L | write +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: I = Enable all interrupts P = Enable parity errors C = Enable status changes H = Enable FIFO overflows/underflows R = Enable parallel poll responses S = Enable Service Requests (SRQ) F = Enable outbound FIFO space available D = Enable data available E = Enable outbound FIFO empty L = Enable Device Clears (DCL) Writing a 0 to a given bit masks that interrupt source. The corresponding bit in Register 2 will read 0 while it is masked. Writing a 0 to bit 0 masks all interrupts. Register 3 is cleared when the PHI SRST (soft reset) line is asserted. Register 4 - Parallel Poll Mask: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 0 0 0 0 0 0 0 | parallel poll response mask | read +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - - - - - - - - | parallel poll response mask | write +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Each mask bit is ANDed with the corresponding parallel poll response received over the bus. A mask bit of 0 prevents recognition of the poll response. Note that bits 8-15 correspond to HP-IB signal lines DIO8-DIO1, which correspond to poll responses from bus addresses 0-7, respectively. NOTE: Bits 0 and 1 are stated as reading as zeros in the terminal interface manual but as ones in the Series 4x manual. Register 5 - Parallel Poll Sense: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 0 0 0 0 0 0 0 | parallel poll response sense | read +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - - - - - - - - | parallel poll response sense | write +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Each sense bit is XORed with the corresponding parallel poll response received over the bus. A mask bit of 1 reverses the poll response sense (i.e., a 0 bit on the bus represents a request for service). Note that bits 8-15 correspond to HP-IB signal lines DIO8-DIO1, which correspond to poll responses from bus addresses 0-7, respectively. NOTE: Bits 0 and 1 are stated as reading as zeros in the terminal interface manual but as ones in the Series 4x manual. Register 6 - Control: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 0 0 0 0 0 0 0 | B | F | R | I | P | S | D | C | read +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 0 | - - - - - - | B | F | R | I | P | S | D | C | write +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: B = 8-bit processor F = Parity freeze R = Remote Enable (REN) bus line I = Interface Clear (IFC) bus line P = Set Parallel Poll response S = Service Request (SRQ) bus line D = DMA direction (0/1 = inbound/outbound) C = Clear outbound FIFO The DMA direction bit determines the action of the DMARQ (DMA Request) line. When set to 0 (inbound), DMARQ is asserted whenever the inbound FIFO has data available. When set to 1 (outbound), DMARQ is asserted when the outbound FIFO is not full. NOTE: Bits 0 and 1 are stated as reading as zeros in the terminal interface manual but as ones in the Series 4x manual. NOTE: Bits 8 and 9 are shown as "must be written as 0" in the terminal manual. This corresponds to "16-bit processor" and "accept incorrect parity" functions. Register 7 - HP-IB Address: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 0 0 0 0 0 0 0 | O | T | L | bus address | read +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 0 | - - - - - - | O | T | L | bus address | write +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: O = PHI is online T = PHI is talk always L = PHI is listen always NOTE: Bits 0 and 1 are stated as reading as zeros in the terminal interface manual but as ones in the Series 4x manual. Register 8 - DMA Extended Address: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | E | 0 0 | DMA state | upper address bits | read +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 0 0 0 0 0 0 0 | upper address bits | write +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: E = DMA is enabled Specifies the upper 8 bits (bank number) of the 24 bit transfer word address. Bit 0 indicates the state of the DMA Enable flip-flop. The DMA State value is the address supplied to the DMA ROM state machine. Register 9 - DMA Address: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | lower address bits | read/write +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Specifies the lower 16 bits of the 24 bit transfer word address. The register is incremented once for each two data bytes transferred. When the transfer ends, the register will contain the address of the byte following the final byte transferred. The register is updated and may be read during transfers. Register A - DMA Byte Count: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | byte count | read/write +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Specifies the number of bytes to transfer (a value of 0 means 64KB). The register is decremented for each byte transferred. If a transfer completes, the value will be zero. Otherwise, it will be the number of bytes not transferred when the abort occurred. Register B - DMA Status/Control: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | I | P | V | T | 0 | stat | B | C | R | E | D | S | Device | read +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 0 0 0 0 0 0 | A | C | R | E | D | G | Device | write +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: I = PHI interrupt P = Parity error V = Address overflow T = Memory timeout B = DMA busy C = Inhibit CSRQ on parallel poll R = Right-hand byte E = Inhibit EOI on the last byte D = DMA direction (0/1 = inbound/outbound) S = Diagnostic switch position (0/1 = OPERATE/TEST) A = Disable address increment / assert SRQ (only when S5 = TEST) G = Diagnostic disabled (only when S5 = TEST) Status: 00 = ~DMASTATA * ~DMASTATB 01 = ~DMASTATA * DMASTATB 10 = DMASTATA * ~DMASTATB 11 = DMASTATA * DMASTATB Writing sets DMA control parameters and starts DMA. Bit 7 (A) must be 0 to allow the DMA address register to increment; if SW5 is in the TEST position, this bit controls the HP-IB SRQ line directly. Bit 8 (C) disables CSRQ assertion when a parallel poll response is detected (see page 7-32 of the Series 44 RTM). It is copied from the Record/Burst Mode bit in the DMA instruction configuration, so it is set for Burst Mode (is this so that a higher-priority poll response does not interrupt a set of burst transfers, which if allowed would lead to overruns/underruns?). Bit 10 (E) = 1 inhibits DMA from asserting EOI when the byte count reaches zero. Bit 12 (G) is significant only when switch SW5 is in the TEST position. If it is, then when this bit is zero: - CSRQ generation is inhibited - the one-second timeout counter is inhibited - the free-running DMA clock is inhibited - DMA clock cycles occur when IMB read or write occurs - bit 7 (A) controls the HP-IB SRQ line directly When this bit is set to one, then the above conditions are reversed, i.e., the GIC behaves as though the switch were in the OPERATE position. The device number written to the register is available to be read back and is presented in the OBSI response when a DMA completion interrupt occurs. It has no other purpose. Register C - Interrupt Register: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 0 0 0 0 0 0 0 | device interrupt requests | read +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - - - - - - - - - - - - | S | device | write +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: S = Set interrupt request for specified device number Setting a device IRQ bit will cause the GIC to assert the IMB IRQ signal if the interrupt mask bit is set. The device bits are stored in "parallel poll response" order, i.e., device 0 corresponds to bit 8. Register D - Interrupt Information: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 0 0 0 0 0 0 0 | N | channel | device | read +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: N = Channel and device numbers are not valid This register is read in response to an Obtain Interrupt Information (OBII) IMB command. The N bit is set if no device has an interrupt request pending. A write to register D is ignored. Register E - Channel Configuration/DMA Abort: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | H | C | 0 0 0 0 0 0 0 0 0 | channel type | read +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | write +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: H = Hybrid (switch S2 position 0/1 = A/B) C = CPU/CPP (switch S1 position 0/1 = CPU/CPP) Bits 12-15 supply the channel type identifier; the GIC type is 0. Writing to this register aborts the current DMA operation. Reading this register reports the position of the configuration switches S1 and S2. Register F - Channel Service Information: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 0 0 | T | B | S | V | H | N | Channel | Device | read +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 0 0 0 0 0 0 | A | C | R | E | D | G | Device | write +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: T = Operation timeout B = DMA abort S = SRQ request (always 0 for GIC Revision D) V = Device request H = Channel request (including DMA completion) N = Channel and device numbers are not valid A = Disable address increment / assert SRQ (only when S5 = TEST) C = Disable CSRQ for parallel polls R = Right-hand byte E = EOI disabled D = DMA direction (0/1 = inbound/outbound) G = Diagnostic disabled (only when S5 = TEST) Writing to this register is the same as writing to Register B, except that DMA is not started. Bit 7 (A) must be 0 to allow the DMA address register to increment; if SW5 is in the TEST position, this bit controls the HP-IB SRQ line directly. This register is read in response to an Obtain Service Information (OBSI) IMB command. The N bit is set if no device has a channel service request pending. A Timeout is asserted if the GIC has waited more than one second for some action to occur. A Device Request is asserted when the New Status register has a bit set, or when the PHI is asserting a bit on its data lines for a parallel poll and OBSIDN is asserted. A Channel Request is asserted for a PHI interrupt (e.g., outbound FIFO empty, inbound FIFO has data) or for a DMA completion interrupt. The device number presented when register F is read directly is different from the number presented when it is read for an OBSI response. For the former, the number is that stored in the register (or register B), i.e., the DMA device number. During an OBSI, the device number is: - the highest-priority bit in the New Status register - the highest-priority bit of a parallel poll response - the register B device number for a DMA interrupt - device 7 (hardware default) for a PHI interrupt Byte Transfer Enable ~~~~~~~~~~~~~~~~~~~~ The PHI provides two methods of indicating the end of a read (inbound) transfer. The first method is the Counted Transfer Enable. This command, written to the outbound FIFO after the device has been addressed to talk, indicates that the transfer ends on reception of the specified number of bytes, by reception of a byte tagged with EOI, or optionally by reception of a line-feed (LF) byte. A count of zero is interpreted as a transfer of 256 bytes. The second method is the Uncounted Transfer Enable. This command indicates that bytes are accepted until a byte tagged with EOI is received. It is used when the size of the incoming record is unknown. There is no interrupt associated with end-of-transfer recognition. Instead, bits 0 and 1 indicate whether the byte is a normal byte (bits = 00), the final byte of a counted transfer (bits = 10), or a byte tagged with EOI or LF (bits = 11). As a consequence, counted transfers are simply a convenience, as the same result would be achieved if the receiving circuit counted bytes itself. In the CPP, inbound counted transfers are used for these operations: Operation Count ------------------- ----- Read (burst mode) burst Read (single byte) 1 DSJ 1 Identify 2 Single-byte reads, DSJs, and Identifies do not use DMA. Instead, after sending the appropriate Counted Transfer Enable, they enable the inbound FIFO data available interrupt. The interrupt asserts when the first byte arrives. This is the only byte for reads and DSJs but only the first of two bytes for Identifies. Apparently, the CPP simply assumes that the second byte will be available when the FIFO is read. Burst-mode reads use DMA and set up the DMA byte count to the burst size. So the transfer is ended by the DMA count rather than the PHI count. DMA does monitor bits 0 and 1 during each byte transferred from the inbound FIFO and will end the transfer if the bits are 11, indicating EOI reception. No other bit state is examined -- in particular, the count termination state, bits = 10, is not checked. So there appears to be no reason to use Counted Transfer Enables at all, as all transfers are ended either by EOI, by DMA byte count, or by receiving the expected number of bytes (one or two). [NO!] (Actually, there is a fallback mechanism: if the inbound FIFO is empty, DNV will assert, and this apparently causes a microcode trap [??? p.???]. The routine sets up another wait-for-data indicator and exits. When the second byte arrives Parallel Poll ~~~~~~~~~~~~~ Per 13255-91128 page 25, "When the outbound FIFO within an HP-IB controller is empty, the PHI chip automatically conducts a continuous parallel poll on the HP-IB. The poll terminates as soon as the next word is placed into the outbound FIFO by the host processor." This description is not complete. Page 27 goes on to say, "After addressing another device to talk, the host processor should place a BYTE TRANSFER ENABLE [command] into its own outbound FIFO to remove the ATN signal from the HP-IB and allow bytes to be sent to all addressed listeners." So if this command stops the automatic poll, what reenables it? Looking at logic state analyzer traces from the Series 37, it appears that automatic polling is reenabled: - at the end of a counted (burst) transfer - at the end of an uncounted transfer after receiving EOI (or LF, presumably) Traces show a poll inserted between the end of a 7970E read burst and the Untalk and Unlisten that end the transaction. So the PHI is not waiting for the command. Traces of a 7970E burst write also show anomalous behavior. Consider: -140 DF REN ATN Untalk 2.04 usec -139 BF REN ATN Unlisten 5.08 usec -138 00 REN ATN EOI Parallel poll 14.32 usec -137 5E REN ATN Talk 30 2.04 usec -136 23 REN ATN Listen 3 3.80 usec -135 E0 REN ATN Write data 3.96 usec -134 FE REN FEH data write 165.4 usec -133 FE REN FEH data write 95.00 usec The first poll is conducted 14 microseconds after the outbound FIFO empties. However, after the Write Data command, the first data byte enters the outbound FIFO after 165 microseconds. Yet, a poll is not conducted when the secondary is accepted and the FIFO is temporarily empty for a much longer time than that between the Unlisten and the Talk 30. Somthing seems to be holding the automatic poll off here. But then, at the end of the burst: -072 FE REN FEH data write 19.56 usec -071 FE REN FEH data write 19.72 usec -070 00 REN ATN EOI Parallel poll 73.28 usec -069 BF REN ATN Unlisten 2.08 usec -068 00 REN ATN EOI Parallel poll 14.92 usec -067 3E REN ATN Listen 30 2.08 usec -066 43 REN ATN Talk 3 3.84 usec -065 61 REN ATN Send status 3.92 usec Here, the poll picks up automatically at the end of the burst. But outbound transfers are not counted by the PHI (supposedly). So how does it know to reenable polling? The outbound FIFO is cleared when bit 15 (clear outbound FIFO) of Register 6 is set or the Soft Reset pin (pin 15, PON) is low. When the FIFO is cleared, a parallel poll begins immediately, asserting ATN and EOI. Caution must be exercised if a data byte is on the bus at that time, as it may be misinterpreted as a command. Parallel Poll Response ~~~~~~~~~~~~~~~~~~~~~~ Per 13255-91128 page 27, "If the inbound FIFO is empty during any attempt to read from it...if the device containing the PHI chip is the HP-IB controller and has been conducting a parallel poll for at least two microseconds (the outbound FIFO has been empty for at least two microseconds), the a read from register [0] will obtain the DIO line responses of the eight pollimng devices...." Per page 23, bit 10 of register 2 is set when a parallel poll response is detected, specifically when: - the outbound FIFO is empty, implying that a poll is being conducted, - the poll has been conducted for at least two microseconds, - the inbound FIFO is empty, so the host won't read data as responses, and - a device is asserting its poll response. Inhibit CSRQ on Parallel Poll ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Bit 8 of Register B is described as the "no poll" bit. Setting the register bit asserts the CSRQDIS signal. This signal is reflected back when reading Register B. When asserted, it also controls the following aspects of GIC operation: - It prevents the DMAINACT signal from disabling the watchdog timer, i.e., it releases the timer if DMA is inactive. - It disables New Status register encoding, so it cannot assert CSRQ. - It disables parallel poll response recognition. The channel program processor sets this bit when a program suspends to wait for the PHI outbound FIFO to empty. Once emptied, the PHI will conduct a parallel poll automatically; this bit prevents a potential poll response from being recognized. The bit is also set when a WAIT instruction has the "Wait for selected conditions" option selected. Without this option, the program waits for a parallel poll. With the option, poll response is inhibited, and the wait concludes when the PHI interrupts. It is also set for a READ, DSJ, or IDENTIFY instruction while waiting for the device to return data to prevent a possible poll response from being interpreted as incoming data. Reset ~~~~~ Four signals are involved in resetting the GIC. They are: - PON (Power On) - SRST (System Reset) - IOCL (I/O Clear) - INIT (Initialize Channel) The first two are IMB signals and are combined to generate the PONB signal. The latter two are IMB Commands that are combined with the PONB signal to generate the PONINCL and PONDLAY signals. Asserting the PONB signal: - resets the DMA Clock flip-flop Asserting the PONDLAY signa:: - clears the DMA state machine to state 0 - resets the PHI via its PON (Soft Reset) pin A soft reset signal assertion clears all PHI registers except Register 1 (status). Clearing Register 2 drops the IRQ line, clearing bit 0 of Register B. Asserting the PONINCL signal: - releases the IMB if the GIC has obtained it - releases the master handshake - clears bits 7-8 and 12-15 of Registers B and F - clears DMASTATA and DMASTATB flip-flops (bits 5-6 of Register B) - clears the DMAENF flip-flop - clears the New Status register - clears Register C - clears the Interrupt Mask flip-flop - generates the CLRERR signal - clear bits 1-3 of Register B (via CLRERR) - clears the timeout flip-flop and presets the timeout counter (via CLRERR) For the GIC registers, a reset clears: - Register B bits 0-8 and 12-15 - Register C bits 8-15 - Register F bits 7-8 and 12-15 Registers 8, 9, and A are unaffected, Register D is read-only, and Register E reflects switch settings and has no programmable bits. CSRQ Generation ~~~~~~~~~~~~~~~ The GIC requests service from the CPP by asserting CSRQ on the IMB. When the CPP responds with an OBSI command, the GIC returns the contents of Register F, more or less (see below). The return value contains a Device Request bit, a Channel Request bit, a No-Request bit, and an encoded device number from 0-7. It also contains status bits that indicate the source of an unexpected request (Operation timeout, DMA abort, or SRQ request); "expected" requests are reflected in DRT word 3, the channel program status word. From the OBSI return and DRT 3, the CPP decides what action is needed. To determine the Register F value, the CSRQ logic generates DEVRQ, CHANRQ, and a multiplexer selector signal. The selector determines whther the device number is from the priority encoders of the New Status and Parallel Poll Response registers, or from the device number field of Register B. It also determines whether CHANRQ is denied unilaterally, or is derived from a PHI interrupt or DMA completion. The logic is quite convoluted, and one of its quirks is that the Register F value that is returned depends on whether it is read via an OBSI command or via an RIOC command. The GIC diagnostic tests both types of return values, so they must be generated accurately. //CHECK! Another quirk is that a particular condition may return a value with both the Device Request and the Channel Request bits set. //CHECK END Working backward from the IMB, the -CSRQ1 and -CSRQ2 signals are generated from a pair of NAND gates that are qualified by the setting of the SW1 switch (CPU/CPP). These gates derive from a common MYCSRQ signal that is ANDed with the -DIAG signal that is asserted when bit 12 of Register B or F is clear and SW5 (OPER/TEST) is in the TEST position. Assertion inhibits MYCSRQ, which prevents CSRQ assertion on the IMB, although the device and channel request bits in Register F are still valid. -DIAG is denied if bit 12 is set or SW5 is in the OPER position. In the normal case, i.e., SW1 is in the CPU position and SW5 is in the OPER position, then MYCSRQ assertion will assert CSRQ1 on the IMB. The overall logic equations are as follows: MYCSRQ = -PFW * OBSCRW OBSCRW = CHANRQ + DEVRQ DEVRQ = NS.GS + (PPR.GS * OBSIDN) NS.GS = NSEN * one or more inputs asserted NSEN = CIC * DMAINACT * ~CSRQDIS * ATNB * EOIB * ~DMARQPLA * ~OBSIDOF + ~CIC * DMAINACT * ~CSRQDIS DMAINACT = ~DMAENF * DMOFF DMAENF = DMA Enable flip-flop is set DMOFF = DMA sequencer is in state 0 CSRQDIS = Inhibit CSRQ on parallel poll (REGB.8) DMARQPLA = PHI DMA request (inbound FIFO has data or outbound FIFO not full) PPR.GS = OBSIDOF * one or more inputs asserted OBSIDN = OBSIDOF * IOEND OBSIDOF.D = PHIINT * CIC * DMAINACT * ~CSRQDIS * ATN * EOI OBSIDOF.C = OBSI OBSIDOF.R = ~DDOB PHIINT = Interrupt signal from PHI (REG2.0) or timeout counter expired IOEND = Signal from the PHI to indicate the end of the handshake CHANRQ = -MUX.S * DMRQEN DMRQEN = (PHIINT + DMIN) * ~DMOBSIF DMIN = DMA direction is inbound (-REGB.11) DMOBSIF.R = DMOFF DMOBSIF.D = DMINT DMOBSIF.C = ~OBSI (inhibits CSRQ after OBSI executed) MUX.S = (OBSIDOF + -PHIINTBF) * (PPR.GS + -PHIINTBF) * -DMINT -MUX.S = PHIINTBF * (-OBSIDOF + -PPR.GS) + DMINT PHIINTBF.S = PHIINT * DMINACT * -OBSI PHIINTBF.R = -PHIINT + -DMINACT DMINT = signal from DMA sequencer asserted in states 5 and 4 OBSIDEV = -MUX.S * DMDEV + MUX.S * (NS.AN + PPR.AN) DMDEV = device number from Register B bits 13-15 Looking at these actions in detail: MYCSRQ = -PFW * OBSCRW OBSCRW = CHANRQ + DEVRQ MYCSRQ is generated as an OR of DEVRQ, CHANRQ, and HPSRQ, although the latter is grounded in Revision D of the GIC, so it is permanently disabled. The OR of the device and channel requests is then is qualified with -PFW (Power Fail Warning) from the IMB, which serves to inhibit service requests while power is failing. DEVRQ, CHANRQ, and a NOR of these two, OBSCRQ (i.e., No Rquest), are presented as Register F bits 6, 7, and 8. DEVRQ = NS.GS + (PPR.GS * OBSIDN) NS.GS = NSEN * one or more inputs asserted DEVRQ is the OR of the GS (Group Select) output of the New Status register priority encoder and an AND of the GS output of the Parallel Poll Response priority encoder and the OBSIDN ("OBSI done") signal. The GS outputs assert when one or more of the eight encoder inputs are asserted. NSEN = CIC * DMAINACT * ~CSRQDIS * ATNB * EOIB * ~OBSIDOF * ~DMARQPLA + ~CIC * DMAINACT * ~CSRQDIS DMAINACT = ~DMAENF * DMOFF DMAENF = DMA Enable flip-flop is set DMOFF = DMA sequencer is in state 0 CSRQDIS = Inhibit CSRQ on parallel poll (REGB.8) OBSIDOF.D = PHIINT * CIC * DMAINACT * ~CSRQDIS * ATN * EOI OBSIDOF.C = OBSI OBSIDOF.R = ~DDOB DMARQPLA = DMA request from the PHI (FIFO data present or FIFO not full) When a New Status register bit sets, and NSEN ("New Status enable") is asserted, then NS.GS asserts, resulting in a device request. If the PHI is the CIC, then NSEN asserts when DMA is inactive, the Inhibit CSRQ bit is not set in Register B, a parallel poll is in progress, an OBSI command is not being executed for a PPR, and the PHI DMA request is inactive (inbound FIFO is empty). Note in passing that this logic ensures that an HIOP command, which sets a New Status register bit, will NOT generate a CSRQ until a parallel poll is active. The OBSIDO ("OBSI do") flip-flop output asserts at the start of an OBSI cycle for a parallel poll response interrupt from the PHI. As the New Status and Poll Response priority encoder outputs are ORed, this signal determines which encoded value appears in the device field of Register F. If the PHI is not the CIC, then NSEN asserts when DMA is inactive and the Inhibit CSRQ bit is not set in Register B. /// PPR.GS = OBSIDOF * one or more inputs asserted OBSIDN = OBSIDOF * IOEND OBSIDOF.D = PHIINT * CIC * DMAINACT * ~CSRQDIS * ATN * EOI OBSIDOF.C = OBSI OBSIDOF.R = ~DDOB OBSIDN is asserted when the OBSIDO ("OBSI do") flip-flop output asserts during an OBSI cycle in response to a parallel poll response ==== ADCC ==== Series 44 ADCC UART is 1820-3215 (AMI S1602P, second source for WD TR1602) (same as TR1863 used in HP 1000 BACI) Series 33 ADCC UART is 1820-2060 (NEC uPD369D) The ADCC driver is HIOTERM0, S26S033C.SPL The ADCC diagnostic is ADCCDIAG, S20S231A.SPL ------------ IMB Commands ------------ The ADCC decodes 13 IMB commands: Mnemonic Opcode Command Operation -------- ------ ------- ---------------------------- RIOC 100 0000 Read I/O Data OBII 100 0010 Obtain Interrupt Information OBSI 100 0100 Obtain Service Information IPOLL 100 1000 Interrupt Poll ROCL 100 1010 Roll Call SPOL1 100 1100 Service Poll 1 SPOL2 100 1110 Service Poll 2 WIOC 110 0000 Write I/O Data INIT 110 0010 Initialize Channel SIOP 110 0100 Start I/O Program HIOP 110 0110 Halt I/O Program SMSK 110 1000 Set Interrupt Mask IOCL 110 1010 I/O Clear INIT, IOCL, and the IMB SRST, PFW, and ~PON signals all cause the ADCC to reset its internal state. SMSK clocks the data bus bit (3000 numbering) corresponding to the channel address into the Mask flip-flop. The output of the flip-flop gates the IRQ line, so that IRQ assertion is allowed only when the corresponding mask bit is set. Only these register numbers are decoded: 0 : FIFO (Command and Data registers, read/write) 2 : Interrupt Conditions (read only) 12 : Interrupt Register (write only) 14 : Channel Configuration (read only) The diagnostic tests that Registers 1, 3-13, and 15 return zero values when read and that writing into registers 1-11 and 13-15 is ignored. OBSI and OBII are decoded from their commands and are not accessible via a register read. OBII -- Obtain Interrupt Information: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 0 0 0 0 0 0 0 | 0 | Channel | Device | DATA +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Obtain Interrupt Information is issued to the highest-priority channel that is asserting IRQ, as determined by the Interrupt Poll command. The channel returns the number of the highest-priority device that has an interrupt pending. The returned word is used to determine the DRT entry for the external interrupt. For the ADCC, the Not Valid bit (bit 8) is always clear. OBSI -- Obtain Service Information: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 0 0 0 0 0 | D | 0 0 | Channel | Device | DATA +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: D = Device Request The response indicates the device requesting service from the CPP and the reason for the request. For the ADCC, the Device Request bit reflects the state of the CSRQ signal, and the Not Valid bit (bit 8) is always clear. Register 0 - Command and Data: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 0 | - - - - - - | regular data byte | read +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 1 | - - - - - - | special data byte | read +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - | 0 | - - - - - - | data byte | write +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 1 | - - - - - - | 0 | bus interface command | write +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ While the CPP writes the full HP-IB protocol to Register 0, the ADCC responds only to the above formats. The bus commands to which the ADCC responds are: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 1 | - - - - - - | 0 | 0 | 1 | D | 0 | address | Listen +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 1 | - - - - - - | 0 | 1 | 0 | D | 0 | address | Talk +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 1 | - - - - - - | 0 | 1 | 1 | D | 0 | modifier | Secondary +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 1 | - - - - - - | 0 | 1 | 1 | 1 0 0 0 0 | DSJ +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: D = Disable CSRQ if address is even and secondary is odd J = Device Specified Jump To be recognized as a Talk or Listen, either bit 12 must be zero or bit 15 must be 1. The address and the D bit are stored in a latch and are used to select the multiplexer port. The modifier and the D bit are stored in a latch and are used to determine the action to be taken. Interpretation of the data byte depends on the received modifier. The D bit is used to inhibit CSRQ for the diagnostic. For Section 12 of the diagnostic, the manual says: The ADCC logic is capable of suppressing the assertion of CSRQ on the IMB. This is done by sending an address to talk or listen for any of the following device numbers: 16, 18, 20, or 22, followed by any one of the following secondary addresses: 17, 19, 21, 23, 25, 27, 29, or 31. Any reset (PON, SRST, etc.) of the ADCC will re-enable CSRQ assertion. Also, CSRQ assertion can be re-enabled by sending an address to talk or listen for any of the following device numbers: 0, 1, 2, 3, 4, 5, 6, 7, or 31, followed by any of the following secondary addresses: 0, 1, 2, 3, 4, 5, 6, 7, or 16. Register 2 - Interrupt Conditions: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 0 0 0 0 0 0 0 0 0 | R | 0 1 0 1 0 | read +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: R = Parallel poll response is present (ADCC is asserting CSRQ) Bits 11-15 have no meaning on an ADCC, but are defined for use by the channel program microcode. They indicate "Outbound FIFO is not full" and "Outbound FIFO is empty." Bit 0, the OR of the other bits, is always 1 to indicate "An interrupt is pending." Register C - Interrupt Register: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - - - - - - - - - - - - | S | device | write +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: S = Set interrupt request for specified device number Setting a device IRQ bit will cause the ADCC to assert the IMB IRQ signal if the interrupt mask bit is set. Device 0 has the highest priority, with priority decreasing as device address increases. Register E - Channel Configuration: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 | C | 0 0 0 0 0 0 0 0 | E | channel ID | read +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: C = CPU/CPP (switch S1 position 0/1 = CPU/CPP) E = Extender is present Bits 12-15 supply the channel identifier; the ADCC identifier is 1. -------------------------------- Register 0 Data Reads and Writes -------------------------------- The Channel Program Processor controls the ADCC by writing HP-IB protocol commands and data to Register 0. Because the ADCC does not have DMA, CPP Read and Write commands specify Burst Mode transfers with a burst size of 1. Therefore, the reads and writes are performed by the CPP. Each sequence starts with a Talk or Listen for the controller address (30), followed by a Listen or Talk for the ADCC addresses (0-7), followed by a Secondary of 00-07 or 10H, followed by data read(s) or write(s). The primary and secondary addresses are stored by ADCC registers and used to indicate the port number and operation, respectively. The allowed operations are as follows: Secondary 00 - UART Data: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 0 | - - - - - - | regular data byte | read +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 1 | - - - - - - | special data byte | read +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - | 0 | - - - - - - | data byte | write +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ A read asserts the DRR signal to the UART to reset the Data Received condition and permit reception of the next data byte. If the character read is a special character, bit 1 is set to indicate a tagged data byte. Otherwise, is is clear to indicate a final data byte. A write asserts the THRL signal to the UART, entering the data byte into the transmitter holding register. Bit 0 (EOI) is ignored on writes. Secondary 01 - UART Control/Status: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 B | 0 0 0 0 0 0 0 0 0 0 | B | O | P | F | read +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - | 0 | - - - - - - | R | - - | len | S | E | I | write +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: B = Break detected O = Overrun error (OE * DR) P = Parity error (PE * DR) F = Transmit buffer empty R = Master reset S = Stop bits (0/1 = one bit/two bits) E = Even parity I = Inhibit parity generation and checking Word Length: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits The Transmit Buffer Empty status value is masked according to the Service Condition Mask settings. If the status read includes the Break Detected bit, then bit 1 is set to represent a tagged data byte. Otherwise, is is clear to represent a final data byte. F = THRx * TREx * Bx (service condition 1) Secondary 02 - Interface Control/Modem Status: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 1 | 0 0 0 0 0 0 0 0 0 | B | C | E | F | S | read +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - | 0 | - - - - - - - - - | R | A | D | H | X | write +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: (actually) B = CB (CTS) state RI C = CC (DSR) state DTR E = CE (RI) state (undefined; european?) F = CF (DCD) state RTS S = SCF (SDCD) state (undefined) R = Enable received character echo A = CA (RTS) state (0/1 = off/on) DCD D = CD (DTR) state (0/1 = off/on) DSR H = CH (DRS) state (0/1 = off/on) DRS X = SCA (SRTS) state (0/1 = off/on) SDCD Reading returns with bits 0 and 1 set to indicate a tagged data byte. The RI (Ring Indicator) and DRS (Data Rate Selector) bits are only valid when the ADCC extender is installed, as all eight receivers for the CE signals and transmitters for the CH signals are located on the extender PCA. If the extender is absent, the E bit is always zero, and the H bit is ignored. Reset clears the interface control register. Secondary 03 - Service Condition Masks: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - | 0 | - - - - - - - - - - - | M | cond | write +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: M = Mask bit (0/1 = disable/enable) Condition: 00 = Transmit buffer not full (THRE) 01 = Transmit buffer is empty (THRE * TRE) 10 = Receive buffer is not empty (DR) 11 = not used Reset clears this register. -- mask 2 enables read of reg 0 to pulse DRR (UART data received reset), which clears RHR occupancy! Secondary 04 - Clear Special Character RAM: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - | 0 | - - - - - - | character | write +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ The specified character is no longer a special character. Secondary 05 - Set Special Character RAM: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - | 0 | - - - - - - | character | write +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ The specified character becomes a special character. Secondary 06 - Set Baud Rates: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - | 0 | - - - - - - - - - | S | baud rate | write +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: S = Rate selector (0/1 = transmitter/receiver) Baud Rate: 0 = external 1 = external 2 = 50 3 = 75 4 = 134.5 5 = 200 6 = 600 7 = 2400 8 = 9600 9 = 4800 10 = 1800 11 = 1200 12 = 2400 13 = 300 14 = 150 15 = 110 Secondary 07 - Status Reference/Mask: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - | 0 | - - - - - - - - | M | B | C | E | F | S | write +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: M = Status selector (0/1 = reference/mask) B = Set CB (CTS) value C = Set CC (DSR) value E = Set CE (RI) value F = Set CF (DCD) value S = Set SCF (SDCD) value Setting a given status mask bit enables a channel request when the selected status line asserts if the corresponding mask bit is clear or denies if the mask bit is set. Setting the reference and mask states for the RI (Ring Indicator) status is available only when the ADCC extender is installed. Otherwise, the E bit is ignored. Secondary 10 - DSJ: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - - - - - - - - | 0 0 0 0 0 0 | jump | read +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Jump: 0 = UART receive buffer contains a character 1 = UART transmit buffer is empty 2 = UART status has changed (overrun error, parity error, break, or modem line) 3 = device is not requesting service If multiple conditions are present simultaneously, the presentation priority is 2, 0, 1, 3. Note that while PE and OE cause DSJ = 2, they do not assert CSRQ. DSJ.1 = STATn + PEn + OEn + ~(BNFn + BEMn) DSJ.0 = ~(RCVn + STATn + PEn + OEn) STATn = BRKn + STCHn + MDMn BRK = UART framing error (FE) * UART receiver input (RI) * UART receiver register clock (RRC) STCH = CB, CC, CF, SCF xor status-reference * status-mask MDM = RI xor status-reference * status-mask PEn = UART parity error (PE) OEn = UART overrun error (OE) BNFn = THRn (empty) * An (service condition mask 0 enabled) BEMn = THRn (empty) * TRn (empty) * Bn (service condition mask 1 enabled) RCVn = UART data received (DR) * ~UART framing error (FE) SRQ = THRE * M0 + THRE * TRE * M1 + DR * M2 + BRK + MDMST + CEMASK * (CEREF ^ CE) MDMST = RUN * (CBMASK * (CBREF ^ CB) + CCMASK * (CCREF ^ CC) + CFMASK * (CFREF ^ CF) + SCFMASK * (SCFREF ^ SCF)) DSJ derives from mask and ref/signal checks before RUN qualification. SRQP = SRQ + NEWST (priority is SRQ0, NEWST0, SRQ1, NEWST1, etc.) CSRQ = SRQP * SRQEN SRQEN = priaddr < 16 + priaddr is odd + secaddr < 16 + secaddr is even SRQDIS = priaddr > 15 * priaddr is even * secaddr > 15 * secaddr is odd Identify: 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 1 | - - - - - - | 0 | 1 | 0 | 1 1 1 1 1 | Untalk +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 1 | - - - - - - | 0 | 1 | 1 | D | 0 | address | Secondary +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ An Untalk followed by a secondary address 0-7 will return the Amigo ID of the ADCC, which is 4080H. If the address is 4-7 and the extender is not present, the ADCC will assert DNV (Data Not Valid). ------------------ RS-232 Connections ------------------ 30090-90034 October 1984 [PDF p.45] 30070-90009 January 1979 [PDF p.137] Terminal and modem connections are made to a four-place RS-232 connector panel that is populated by female DB-25 connectors wired as DCE. Each ADCC main or extender PCA has an interconnection cable between card-edge connector J2 on the PCA and the RS-232 panel. Using port 0 as the pin number reference, the cable is wired as follows: ADCC DBF ADCC DTE Pin Pin Ckt DCE Description Dir Ckt DTE Description ----- --- ---- ----------------------------- --- --- ----------------------------- J2-FF 2 BB Received Data <-- BA Transmitted Data J2-DD 3 BA Transmitted Data --> BB Received Data J2-25 4 \ CF Data Carrier Detect <-- CA Request to Send --- 5 / -- --> CB Clear to Send J2-28 6 CD Data Terminal Ready --> CC Data Set Ready J2-21 7 AB Signal Ground <-> AB Signal Ground J2-27 8 CA Request to Send --> CF Data Carrier Detect J2-26 11 \ SCF Secondary Data Carrier Detect -- (undefined) J2-EE 12 | SCA Secondary Request to Send --> SCF Secondary Data Carrier Detect --- 19 / -- <-- SCA Secondary Request to Send J2-24 20 CC Data Set Ready <-- CD Data Terminal Ready J2-23 22 * CB Clear to Send --> CE Ring Indicator J2-20 23 ** CH Data Rate Selector --> CH Data Rate Selector J2-X 25 ** CE Ring Indicator - -- (undefined) ------ 30021A ADCC-to-Junction Panel Cable 13232N Direct-Connect Terminal Cable, DB-25M to 264x card edge 30062B Direct-Connect Terminal Cable, DB-25M to DB-25F 30062B Modem Cable, DB-25M to DB-25M ADCC DBF ADCC Pin Pin Ckt Dir DCE Description ----- --- ---- --- -------------------------------- J2-FF 2 BB <-- Received Data J2-DD 3 BA --> Transmitted Data J2-25 4 CF <-- Data Carrier Detect --- 5 -- --- (connected to pin 4 internally) J2-28 6 CD --> Data Terminal Ready J2-21 7 AB <-> Signal Ground J2-27 8 CA --> Request to Send J2-26 11 SCF <-- Secondary Data Carrier Detect J2-EE 12 SCA --> Secondary Request to Send --- 19 -- --- (connected to pin 11 internally) J2-24 20 CC <-- Data Set Ready J2-23 22 * CB <-- Clear to Send J2-20 23 ** CH --> Data Rate Selector J2-X 25 ** CE <-- Ring Indicator [*] DB-25 pin 22, assigned as received signal CE Ring Indicator for DTE, is connected to the ADCC and assigned as received signal CB Clear to Send. So there is no transmitter on this line. [**] The CH (Data Rate Selector) and CE (Ring Indicator) signals are available for ports 0-3 only when the extender is present. This is because the extender contains the circuitry for all eight ports. Direct cable: DBF ADCC DBM DTE Pin Ckt Dir DCE Description Pin Dir Ckt DTE Description --- ---- --- -------------------------------- --- --- --- ----------------------------- 2 BB <-- Received Data 2 <-- BA Transmitted Data 3 BA --> Transmitted Data 3 --> BB Received Data 4 CF <-- Data Carrier Detect 4 <-- CA Request to Send 5 -- --- (connected to pin 4 internally) 5 --> CB Clear to Send 6 CD --> Data Terminal Ready 6 --> CC Data Set Ready 7 AB <-> Signal Ground 7 <-> AB Signal Ground 8 CA --> Request to Send 8 --> CF Data Carrier Detect 11 SCF <-- Secondary Data Carrier Detect 11 --- -- (undefined) 12 SCA --> Secondary Request to Send 12 --> SCF Secondary Data Carrier Detect 19 -- --- (connected to pin 11 internally) 19 <-- SCA Secondary Request to Send 20 CC <-- Data Set Ready 20 <-- CD Data Terminal Ready 22 * CB <-- Clear to Send 22 --- -- (unised) 23 ** CH --> Data Rate Selector 23 --> CH Data Rate Selector 25 ** CE <-- Ring Indicator 25 --- -- (undefined) Modem cable: DBF ADCC DBF DCE Pin Ckt Dir DCE Description Pin Dir Ckt DCE Description --- ---- --- -------------------------------- --- --- --- ----------------------------- 2 BB <-- Received Data 3 <-- BB Received Data 3 BA --> Transmitted Data 2 --> BA Transmitted Data 4 CF <-- Data Carrier Detect 8 <-- CF Data Carrier Detect 5 -- --- (connected to pin 4 internally) -- --- -- (unused) 6 CD --> Data Terminal Ready 20 --> CD Data Terminal Ready 7 AB <-> Signal Ground 7 <-> AB Signal Ground 8 CA --> Request to Send 4 --> CA Request to Send 11 SCF <-- Secondary Data Carrier Detect 12 <-- SCF Secondary Data Carrier Detect 12 SCA --> Secondary Request to Send 19 --> SCA Secondary Request to Send 19 -- --- (connected to pin 11 internally) -- --- -- (unused) 20 CC <-- Data Set Ready 6 <-- CC Data Set Ready 22 * CB <-- Clear to Send 5 <-- CB Clear to Send 23 ** CH --> Data Rate Selector 23 <-- CH Data Rate Selector 25 ** CE <-- Ring Indicator 25 --- -- (undefined) ------ The DB connectors also internally jumper pin 4 (RTS) to 5 (CTS) and pin 11 (unused) to 19 (SRTS). [*] DB-25 pin 22, assigned as received signal CE Ring Indicator for DTE, is connected to the ADCC and assigned as received signal CB Clear to Send. So there is no transmitter on this line. [**] The CH (Data Rate Selector) and CE (Ring Indicator) signals are available for ports 0-3 only when the extender is present. This is because the extender contains the circuitry for all eight ports. The ADCC Test Hood (5060-5563) makes the following internal connections at J2: Signals Description ------------- ---------------------------------------------------------- BA -> BB Transmitted Data -> Received Data CA -> CB, CF Request to Send -> Clear to Send, Data Carrier Detect CD -> CC Data Terminal Ready -> Data Set Ready SCA -> SCF Secondary Request to Send -> Secondary Data Carrier Detect CH -> CE Data Rate Selector -> Ring Indicator The "D" Loop Connector (0960-0475) makes the following internal D-shell connections: Signals Description ------------- ---------------------------------------------------------- BA -> BB Transmitted Data -> Received Data ----- Reset ----- The ADCC "-RST" signal is generated from the following sources: Origin Source Description ----------- ---------- ------------------ IMB command INIT Initialize Channel IMB command IOCL I/O Clear IMB signal SRST System Reset IMB signal PFW Power Fail Warning IMB signal -PON Not Power On The following actions occur when RST is asserted (sheet/location indicated): 1/4H - Clears the Interrupt Mask flip-flop 3/3A - Clears the Service Condition Mask (mod 3) register - Clears Register C (Interrupt Register) - Clears the modifier latch (but not the address latch) 4/1C - Clears the Interface Control (mod 2) register 5/5G - Clears the New Status register - Clears the Program Run State register Two additional indirect actions are performed as a result of a reset: 2/2A - CSRQ assertion is enabled when the modifier latch is cleared, because an even modifier value enables the signal 4/2E - The occupancy flag (DR) for the UART Receiver Holding Register is cleared when the Service Condition Mask register is cleared, because Condition 2 (receiver buffer is occupied) qualifies the active-low Data Register Reset signal. Setting bit 8 in the UART Control register asserts Master Reset to the UARTs. This causes the following actions: - Clears the THR, RHR, and TR registers - Clears the Framing Error, Overrun Error, Parity Error, and Data Received status indicators - Sets the Transmitter Holding Register Empty and Transmitter Register Empty status indicators - Sets the Transmitter Register Output (serial data) to the marking (high) level ===================== 7970E HP-IB Interface ===================== The HP-IB interface for the HP 7970E 1/2" tape drive permits the connection of the drive to the HP Interface Bus. This is the required connection method when using the drive with IMB-based HP 3000 computer systems. The interface replaces the HP 30215 tape controller and parallel interface that is used with SIO-based 3000s, such as the Series II and III. ------------ Device Clear ------------ The manual states that a Universal Device Clear and a Selected Device Clear initialize the interface to its power-up state. The two commands are equivalent and reset the hardware and firmware. Notably, they do not affect the bus addressing state. Although not documented, device clear must set the "tape-unit-placed-online" bit in the status word for each drive that is online at the time the command is executed. The diagnostic relies on this in its CLEARDEV function. The function does: 6900 CHP !94 .Clear Device 6904 WAIT 6908 DSJ 6912,6912;X 6912 RR 1,SS(0),3 .Read STATUS 6916 IN H 6920 RSIO 6924 DELAY 1200 .Delay 120 msec 6928 BSIO QQ 6932 WR 7,TT(21),1 .END (clear DSJ, clear PPR, auto-select) 6936 WAIT 6940 DSJ 6944;X 6944 RR 1,SS(0),3 .Read STATUS 6948 IN H 6952 RSIO 6956 IF SS(1) AND !F00<>0 THEN 6928 The first routine issues a Universal Device Clear. The second routine issues an End with the enable auto-select bit set. Each device that is online will auto-select, enable PPR, clear its "placed online" status bit, and set DSJ = 1. The Read DSJ and Read Status command sequence clears the End command. The last line checks if any "placed-online" bits remain and, if so, repeats the End with auto-select command until all units are acknowledged. A note for Step 218 says, "Cleardev changes unit," and the previously selected unit is explicitly selected after the call. This indicates that an auto-select will occur, meaning that the "placed-online" bits must be restored by the clear. ------------------------- Old versus New Controller ------------------------- Step 10 of the diagnostic determines whether the HP-IB controller is "old" or "new" by calling the WRITEREC function to write a record of 200 bytes using bursts of 63 bytes. It expects an old controller to succeed with DSJ = 0 and a new controller to fail with DSJ = 1 and a Data Timing Error. WRITEREC does this: 1856 WR 1,TT(5),1 110663 Write secondary 01H count 1 burst 1 address 00110305 chain 0 | record mode | left byte 1860 WAIT 110670 Wait | response 0455 1864 DSJ 1868,1928;X 110672 Device Specified Jump 110676, 110727 1868 WB 0,NAME1,VALUE2,VALUE3 110676 Write secondary 00H count 200 burst 63 address 00100007 chain 0 | burst mode | left byte | no EOI 1884 JUMP 1912 110703 Relative Jump 110715 1888 WAIT 110705 Wait | response 7017 1904 DSJ 1908,1928;Y 110707 Device Specified Jump 110713, 110727 1908 JUMP 1868 110713 Relative Jump 110676 1912 WR 7,TT(17),1 110715 Write secondary 07H count 1 burst 1 address 00110321 chain 0 | record mode | left byte 1916 WAIT 110722 Wait | response 0001 1920 DSJ 1928;Y 110724 Device Specified Jump 110727 1928 RR 1,SS(0),3 110727 Read secondary 01H count 3 burst 1 address 00110454 chain 0 termination 110734 | record mode | left byte 1932 IN H,2,5 110734 Interrupt/Halt 0005 | CPVA 2 Before returning, the BEREADY function is called. This checks the Rewinding, Tape Unit Busy, and Interface Busy status bits in SS(0). If all are clear, the function returns. Otherwise, it does a Read DSJ and a Read Status in a loop until the two Busy bits are clear or 1000 attempts have been made. In either case, it prints "After interrupt, dev/controller wasn't ready" before returning. After the WRITEREC call, the diagnostic checks the Data Timing Error bit. A new controller sets this bit; an old controller does not. How exactly this works is not documented. However, some inferences are possible. The interface has a 128-byte FIFO buffer. Once the tape preamble is written by the Write Record command, the interface asserts PPR with DSJ = 0 (or DSJ = 1 if the write ring is missing, e.g.). There is an 8 millisecond window during which data must be supplied to the buffer. If data doesn't arrive in time, or if the data does not arrive fast enough (no more than 13.9 microseconds per byte), a data underrun occurs, which sets the DTE bit. The documented behavior for a Write Record in burst mode is to send 64 bytes without EOI and wait for a PPR. The drive sets PPE to indicate that the buffer can accept another 64 bytes, and a second burst is then sent. As the tape drive consumes bytes, PPR is asserted when the buffer occupancy declines to 64 bytes. The channel program then sends the next burst, and the process is repeated until the final burst is sent with EOI tagging the last byte. For the controller test, after the first 63-byte burst is sent, the program returns to P + 2 with a normal completion of the burst. It then waits for PPR to assert, indicating that the buffer has space for the next burst. At this point, three behaviors are possible. The first is that PPR asserts because there are at least 64 bytes available in the buffer (actually, there are 65). For this response, the next 63-byte burst will almost fill the buffer. As the drive consumes bytes, PPR will assert when occupancy declines below 65, and the normal burst loop will repeat until all 200 bytes are sent. The record is written normally, and no DTE occurs. The second behavior is that PPR asserts only when there are exactly 64 bytes in the buffer. In this case, the first 63-byte burst does not assert PPR, so the program waits. As the drive consumes bytes, occupancy declines to zero, and then an underrun occurs. At this point, there are then two more possibilities. The first is that PPR never occurs. This will lead to a GIC timeout, which will abort the channel program. In this case, the Read Status command that sets SS(0) is never executed, so the test in BEREADY is invalid. This doesn't seem to be expected, so the other possibility is that the underrun causes the Write Record command to terminate, and the wait completes when the final PPR occurs to complete the command. But this seems to contradict the statement in the manual describing the DTE that says, "The DSJ is set to 1 for the final poll response issued for the read/write completion." This says that the DTE isn't reported until the command completes, which suggests that it doesn't abort the command. So neither conclusion of the second behavior seems to be likely. A third behavior is for the interface to assert PPR as in the first behavior but also log a DTE error if a burst does not end with EOI and is shorter than 64 bytes, as determined by the Unlisten that follows the data transmission. In this case, an underrun didn't actually occur. But maybe the diagnostic is taking advantage of a peculiarity of the interface firmware. Behavior 1 would produce the "old controller" indication. Behavior 3 would produce the "new controller" behavior. Behavior 2 seems to be unlikely for the reasons stated. ------------------------- Data Overrun and Underrun ------------------------- The hardware interface contains a 128-byte FIFO that buffers the data transfer between the GIC at 1.2 microseconds per byte and the tape drive at 13.9 microseconds per byte. The interface asserts a poll response when the FIFO is less than half full when writing or more than half full when reading. Put another way, PPR asserts when the FIFO has at least 64 bytes of space available when writing or has at least 64 bytes of data available when reading. That is, PPR assertion means that the FIFO can accept a write or read burst of 64 bytes. In REALTIME mode, this action would leave the bus free about 90% of the time when using burst-mode transfers. Record-mode transfers would initially transfer at the faster rate until the FIFO was full or empty, and then transfer at the slower rate for the remainder of the tape record. In FASTTIME mode, the GIC and tape rates would be about equal. If the FIFO empties during a write or becomes full during a read, a Data Timing Error is set to indicate a buffer underrun or overrun. In simulation, does the FIFO have to be implemented? One aspect is that when reading, the end-of-record poll response occurs on time, regardless of whether or not the data is accepted by the GIC. Step 212 of the diagnostic relies on this. It reads 60 bytes of a 16,640-byte record, then does End / Clear DSJ / Clear poll, then does Read Byte Count, and then waits for the Read Record completion poll. So while only 60 bytes are accepted in the data phase (and an overrun occurs), the PPR after 16K byte times must still be generated. ----- Ideas to avoid implementing FIFO explicitly: 1. Schedule unit completion on tape unit (start -> traverse -> stop) with time to stop figured as data-time * record-length. Schedule data xfer concurrently on tape controller, so that not completing data xfer will still cause end-of-record PPR. 2. Schedule data on tape unit but keep "slack" value, i.e., difference in xfer rates between GIC and tape drive, as indicator of FIFO content level. Detect overrun, underrun, and PPR assertion level (RQSRV return). 3. Keep track of "FIFO level" by scheduling controller at GIC rate and unit at tape rate. For writes, controller stores data and increments FIFO level, while unit decrements level. Unit transitions to stop phase only when EOD and level = 0. For Item 2, buffer half full is represented by slack = 812.8 uS, and buffer full is represented by slack = 1625.6 uS. Item 2 operation (write): - start phase sets slack = 0.0 uS, asserts PPR to initiate Write Data transfer - data byte accepted from bus, assert NRFD; set DTRDY - end of start phase schedules unit at FIFO rate (1.2 uS) - service entry - if DTRDY: - send data to tape controller - add 12.7 uS to slack (13.9 - 1.2) - clear DTRDY - else not DTRDY: - if slack > 1.2 uS then subtract 1.2 from slack else slack = 12.7 uS, set underrun, send dummy byte to tape controller - if slack < 812.8 uS (half full) then set RQSRV for PPR - if slack < 1611.7 uS (1625.6 - 13.9, i.e., space for one more byte) then deny NRFD - continues until EOD set by EOI Item 2 operation (read): - start phase sets slack = 812.8 uS, asserts PPR to initiate Read Data transfer - end of start phase schedules unit at FIFO rate (1.2 uS) - service entry - if not DTRDY and not NRFD and not ATN: - get data from tape controller - subtract 12.7 uS from slack - source data byte to bus - clear DTRDY - else if DTRDY or NRFD or ATN: - if slack < 1625.6 uS then add 1.2 uS to slack else slack = 1625.6 uS, set overrun, get dummy byte from tape controller - if slack > 812.8 uS (half full) then set RQSRV for PPR - continues until DVEND set by tape controller to signify end of record For item 3, FIFO level = 0 on write without EOD indicates underrun. For read, FIFO = 128 indicates overrun. Item 3 operation (write): - call controller with Write Record => set controller = Wait_Phase, RQSRV to initiate Write Data transfer - Write Data calls controller => schedule unit = Start_Phase, set level = 0, set controller = Data_Phase @ 1.2 uS - unit service entry for Start_Phase: schedule unit = Data_Phase @ 13.9 uS - data byte accepted from bus, assert NRFD, set DTRDY, schedule tape controller unit - controller service entry for Data_Phase: call tape controller - controller unit Data_Phase: save byte, increment level, if level < 128 then IFOUT to acknowledge - tape controller return: if IFOUT asserted, then deny NRFD; else NRFD remains asserted to hold off next data transfer - unit service entry for Data_Phase: if level = 0 then underrun, save dummy byte, RQSRV, return; else decrement level, if level = 127 then IFOUT (to deny NRFD holdoff) else if level = 0 and EOD then schedule unit = Stop_Phase else if level <= 64 then RQSRV else return with no action Item 3 operation (read): - call controller with Read Record => set controller = Wait_Phase, RQSRV to initiate Read Data transfer - Read Data calls controller => schedule unit = Start_Phase - unit service entry for Start_Phase: read record to buffer, set level = 64, schedule unit = Data_Phase @ 13.9 uS, schedule controller = Data_Phase @ 1.2 uS - controller service entry for Data_Phase: if not ATN and not NRFD then call tape controller else return - controller unit Data_Phase: get next byte, decrement level, if end of record then DVEND, schedule unit = Stop_Phase; else if level > 0 then IFIN to acknowledge - tape controller return: if IFIN asserted then reschedule controller unit else return with no action - hpib_accept signal change: if ATN or NRFD denies, schedule controller unit - unit service entry for Data_Phase: if level < 128 then increment level else overrun, toss next byte, if end of record then DVEND, schedule unit = Stop_Phase; else if level >= 64 then RQSRV; else return with no action ---- SIO controller: Read Record cntl = wait TOGGLE...XFER cntl = idle unit = start service start unit = data service data ... HPIB controller: Read Record cntl = wait unit = start service start RQSRV, unit = data Read Data cntl = data schedule cntl service when ATN drops service data ... ------------- for read: - index = 0, fifo = 0, length = record-length - tapeunit loads fifo if fifo < 128 then fifo + 1 else index + 1, overrun if index + fifo < length then reschedule - tapecntl unloads fifo out = buffer [index], index + 1, fifo - 1 if fifo > 0 then reschedule else if index = length then move to stop state, DVEND for EOI Does the tape read end with a PPR when the fifo is loaded or only after it unloads? If it did the former, wouldn't there be a race condition, with the PPR possibly beating the end of the transfer? What if there were only one or two bytes in the final burst? Then the prior burst would see the EOR PPR, and the expected end PPR would never occur. ====================================== 26069A HPIB-to-Differential Translator ====================================== Reference: - 26069A HPIB-to-Differential Translator Kit Installation and Service Manual (26069-90901 March 1980) The 26069A HPIB-to-Differential Translator allows the HP 2611, 2613, 2617, 2618, and 2619 line printers with differential interfaces to be connected to the HP 3000 General I/O Channel (GIC). This interface translates the HP-IB signals supplied by the GIC to the parallel differential signals required by the printers. It uses MPE driver "HIOLPRT2" (module 21). Each translator supports a single line printer. Up to four translators are supported on the Series 44. The translator consists of a single Printed Circuit Assembly (PCA) containing a Z-80 microprocoessor, four 2K x 8 MOS ROMs, one 1K x 8 bipolar ROM, four 1K x 4 MOS static RAMs, and a Computer to HP-IB Interface (CHI) chip. User-configurable settings include the HP-IB bus address and 132 or 136 column print line length. A momentary switch that initiaites an on-board self-test is provided, as are eight LEDs for self-test results. Self-test can also be initiated programmatically. The following signals are exchanged between the interface and the printer: Src Signal Description --- ------ ------------------------------------------------ P BUFRDY Printer is online and not printing or slewing P ONLINE Printer is READY and online P READY Power is on, no alarm condition, VFU initialized P CH9 VFU channel 9 is punched P CH12 VFU channel 12 is punched P DEMAND Print online and ready for a character I MASCLR Master clear I STROBE Data is valid on D7-D1 lines I PINST Paper instruction I D1 Data bit 1 I D2 Data bit 2 I D3 Data bit 3 I D4 Data bit 4 I D5 Data bit 5 I D6 Data bit 6 I D7 Data bit 7 The commands that are implemented are: Pri Sec Operation --- --- ------------------------------- UNT MSA Identify 14 - Universal Device Clear 04 - Selected Device Clear MLA 00 Print data MLA 02 Enable/Disable Escape Sequences MLA 10 Amigo Clear MLA 1E Write Loopback MLA 1F Initiate Self-Test MTA 0E Read Status MTA 10 Device-Specified Jump MTA 1E Read Loopback MTA 1F Read Self-Test Result The HP-IB bus transaction sequence for each of the implemented commands is listed below: Identify -------- ATN UNT Untalk ATN MSA My secondary address DAB ID data byte #1 EOI DAB ID data byte #2 ATN OTA Talk 30 Universal Device Clear ---------------------- ATN PCG Primary command 14H ppe Parallel poll enabled when clear completes Selected Device Clear --------------------- ATN MLA My listen address ATN PCG Primary command 04H ppe Parallel poll enabled when clear completes Amigo Clear ----------- ATN MLA My listen address ATN SCG Secondary command 10H ppd Parallel poll disabled EOI DAB Command parity checking enabled/disabled ATN SDC Selected device clear ppe Parallel poll enabled when clear completes ATN UNL Unlisten Device-Specified Jump --------------------- ATN MTA My talk address ATN SCG Secondary command 10H ppd Parallel poll disabled EOI DAB Reporting byte ATN UNT Untalk Print Data ---------- ATN MLA My listen address ATN SCG Secondary command 00H DAB Write data byte #1 ... (more data bytes) EOI DAB Write data byte #n ppe Parallel poll enabled ATN UNL Unlisten Enable/Disable Escape Sequences ------------------------------- ATN MLA My listen address ATN SCG Secondary command 02H ppd Parallel poll disabled EOI DAB Escape recognition action ATN UNL Unlisten ppe Parallel poll enabled Read Status ----------- ATN MTA My talk address ATN SCG Secondary command 0EH ppd Parallel poll disabled EOI DAB Status byte ATN UNT Untalk Write Loopback and Read Loopback -------------------------------- ATN MLA My listen address ATN SCG Secondary command 1EH ppd Parallel poll disabled DAB Loopback data byte #1 ... EOI DAB Loopback data byte #n ppe Parallel poll enabled ATN UNL Unlisten ATN MTA My talk address ATN SCG Secondary command 1EH ppd Parallel poll disabled DAB Loopback data byte #1 ... EOI DAB Loopback data byte #n ppe Parallel poll enabled ATN UNT Untalk Initiate Self-Test and Read Self-Test Result -------------------------------------------- ATN MLA My listen address ATN SCG Secondary command 1FH ppd Parallel poll disabled DAB Execute test #n ppe Parallel poll enabled when test completes ATN UNL Unlisten ATN MTA My talk address ATN SCG Secondary command 1FH ppd Parallel poll disabled EOI DAB Self-test result byte ppe Parallel poll enabled ATN UNT Untalk Unlike other Amigo devices, parallel poll is asserted after a command only when a data buffer is available, rather than to indicate completion of the command. A Universal Clear, Selected Device Clear, or Amigo Clear asserts the MASTER CLEAR signal to the printer. This causes any in-process print motion operation to complete and the bus and printer buffers to clear. The printer responds to data seven data bits plus a "paper instruction" bit. Data is printed when the paper instruction bit is clear. When the bit is set, the printer prints the character buffer and then slews as determined by bit 6: P 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+ | 0 | ASCII character | print data +---+---+---+---+---+---+---+---+ | 1 | 0 | - | line count | slew by count +---+---+---+---+---+---+---+---+ | 1 | 1 | - | VFU channel | slew by VFU +---+---+---+---+---+---+---+---+ The printer responds to a single control bit: master clear. The printer provides n status bits: ready, online, VFU channel 9, and VFU channel 12. The READY and ONLINE signals indicate the current state of the printer. READY asserts when printer power is on, no alarm condition (paper out, tape format error) exits, and the VFU has been initialized. ONLINE asserts when READY is asserted and the Online button is pressed. Therefore: ~ONLINE * ~READY = paper out or VFU error ~ONLINE * READY = paper loaded and offline ONLINE * ~READY = (prohibited) ONLINE * READY = paper loaded and online Operation of HIOLPRT2: The translator provides this status to the driver: 0 | 1 2 3 | 4 5 6 | 7 +---+---+---+---+---+---+---+---+ | L | B | - | E | P | - | O | F | +---+---+---+---+---+---+---+---+ Where: L = Online B = I/O buffer ready E = Protocol error P = Bus parity error O = Paper out F = Power fail PARALLEL POLL CONSIDERATIONS ---------------------------- On Power On (PON) Condition, the controller (driver) will get an Affirmative Response to Parallel Poll (ARPP) the first time due to the PON condition. Afterwards, the controller (driver) will not get an ARPP unless there is a buffer available to accept data, the printer is online and no problems exists. For PON with Offline Condition: The first ARPP cause status to be read, afterward the idle channel program is run until the second ARPP is received. For PON with Online Conditon: The first ARPP cause status to be read, afterward the idle channel program is ran through one pass to assure synchronization between the firmware and the driver. For Power Off When IOQ is Issued: The driver will time out and the idle channel program is run. When power finally gets turned on, the condition specified above will occur in respect to PON being online or offline. For Regular Offline Condition: The driver will not get an ARPP unless there is a buffer available to accept data, the printer is online, and no error conditions exist (ie. paper out, paper jam, platen open, etc). ABORT/POWERFAIL CONSIDERATIONS ------------------------------ On an abort caused either by a powerfail or an operator abort, a Device Clear must be sent to the line printer to clear out the last request and reset the firmware to a known state. This is necessary, since an abort has high priority and can interrupt the channel program prior to it completing. EXTRA HANDSHAKE REQUIREMENT --------------------------- At any point in the driver when a "2" is returned from a DSJ denoting I/O status should be interrogated, an extra wait [WAIT, DSJ] for an ARPP (denoting that a buffer is available to receive the next secondary) is required. This assures that the firmware will not get out of synchronization with the driver. Omission of this extra handshake can result in the protocol error bit being set in the status word. Under the driver completion section, this extra handshake is done under the following conditions: - PON condition (flagged with DSJ 2) - Alarm condition which cleared up showing a clean status but retained the DSJ 2 condition (ie. user opens and closes the yoke between jobs) - Buffer ready bit not set in the status word possibly due to noise on the bus --------------------------- HP-IB Data Reads and Writes --------------------------- The Channel Program Processor controls the translator by sending HP-IB protocol commands and data. Each sequence starts with a Talk or Listen for the controller address (30), followed by a Listen or Talk for the translator address (0-7), followed by a Secondary of 00-?? or 10H, followed by data read(s) or write(s). The secondary addresses are used to indicate the operation to perform. The allowed operations are as follows: Secondary 00 - Printer Data: 8 7 | 6 5 4 | 3 2 1 +---+---+---+---+---+---+---+---+ | 0 | ASCII character | write +---+---+---+---+---+---+---+---+ A write ... DIO 8 is ignored. Data transfer is accomplished with burst writes of 128 bytes. This is the size of the data buffers provided by the translator [?]. If enabled, the translator responds to escape sequences by performing paper motion. The following sequences are recognized: ESC & l nn U -- slew by line count nn. ESC & l nn V -- slew by VFU channel nn. These escapes are sent with one or two spaces before the number and one after the number. The translator ignores these. If escapes are disabled, then the characters are sent to the printer as data. Escapes are always sent as eight-byte strings. Secondary 02 - Enable/Disable Escape Sequences: 8 7 | 6 5 4 | 3 2 1 +---+---+---+---+---+---+---+---+ | 1 0 0 0 0 0 | E | 0 | write +---+---+---+---+---+---+---+---+ Where: E = Enable/disable (0/1) escape sequences Secondary 0E - Read Status: 8 7 | 6 5 4 | 3 2 1 +---+---+---+---+---+---+---+---+ | L | B | - | E | P | - | O | F | read +---+---+---+---+---+---+---+---+ Where: L = Online B = I/O buffer ready E = Protocol error P = Bus parity error O = Paper out F = Power fail Secondary 10 - DSJ: 8 7 | 6 5 4 | 3 2 1 +---+---+---+---+---+---+---+---+ | 0 0 0 0 0 0 | jump | read +---+---+---+---+---+---+---+---+ Jump: 0 = Printer is ready to accept data 1 = Invalid byte, read status 2 = Read Status is required 3 = Invalid byte, read status NOT CLEAR HOW 1, 2, and 3 DIFFER! Driver lumps them all together to trigger a read status command. Is there a printer diag that would reveal this? If multiple conditions are present simultaneously, the presentation priority is .... Secondary 1E - Write/Read Loopback: 8 7 | 6 5 4 | 3 2 1 +---+---+---+---+---+---+---+---+ | loopback data | write +---+---+---+---+---+---+---+---+ | loopback data | read +---+---+---+---+---+---+---+---+ A write loopback of from 1 to 256 bytes is accepted. A read loopback of the same length is returned. All 256 bytes may be written in a single transfer; bursts limited to 128 bytes are not needed. Secondary 1F - Self-Test Initiate/Result: 8 7 | 6 5 4 | 3 2 1 +---+---+---+---+---+---+---+---+ | 0 0 0 0 0 | subtest | write +---+---+---+---+---+---+---+---+ | self-test result | read +---+---+---+---+---+---+---+---+ A write command initiates the subtest indicated in the supplied byte. A subtest of zero indiates that all subtests should be run in sequence. A read command returns the test result in the supplied byte. Identify: 8 7 | 6 5 4 | 3 2 1 +---+---+---+---+---+---+---+---+ | 0 0 1 0 0 0 0 0 | read ID byte 1 +---+---+---+---+---+---+---+---+ | 0 0 0 0 1 0 1 0 | read ID byte 2 +---+---+---+---+---+---+---+---+ An Untalk followed by a matching secondary address of 0-7 will return the Amigo ID of the translator, which is 200AH. Amigo Clear: 8 7 | 6 5 4 | 3 2 1 +---+---+---+---+---+---+---+---+ | 0 0 0 0 0 0 0 1 | write +---+---+---+---+---+---+---+---+ The control byte specifies that HP-IB command parity should be checked. ---------- DSJ Status ---------- The HIOLPRT2 driver expects the DSJ return status to range between 0 and 3, with 0 representing "OK" status. However, all three error status returns are lumped together and result in a Read Status command, followed by a channel program halt. The serivce manual has no programming information, and the comments in the driver source say that the values correspond as follows: 0 = Printer is ready to accept data 1 = Invalid byte, read status 2 = Read Status is required 3 = Invalid byte, read status Unfortunately, there is no further information to differentiate DSJ 1-3. The driver comments mention in passing that a power fail produces DSJ 2, but then so does an "alarm condition," such as opening the printer platen (so, i.e., a printer offline condition). The printer cable provides the READY, ONLINE, and BUFRDY status indications. READY asserts when printer power is on, no alarm condition (paper out, tape format error) exits, and the VFU has been initialized. ONLINE asserts when READY is asserted and the Online button is pressed. BUFRDY asserts when the printer is online and not printing or slewing. The Read Status byte provides these bits to the host: - Online - I/O buffer ready - Protocol error - Bus parity error - Paper out - Power fail ...where Online reflects the ONLINE signal, and Paper Out reflects the complement of the READY signal. The BUFRDY signal does NOT provide the I/O Buffer Ready status; the latter indicates that the interface has a bus buffer available. In theory, then, the DSJ returns could differentiate between these conditions. But there is no direct proof of this. Looking at the other HP-IB printers (2608S and HIOLPRT0, and 2631 and HIOLPRT1), we see these DSJ returns: 2608 ~~~~ 0 = Printer is ready to accept data 1 = Attention required 2 = Parity error 3 = Attention required and parity error 2631 ~~~~ 0 = Printer is ready to accept data 1 = Error, read status 2 = Read status required 3 = Parity error Of course, given that the MPE driver lumps all DSJ > 0 returns together, it doens't actually matter how the errors are assigned. ------------- Parallel Poll ------------- The driver comments say: The driver will not get [a parallel poll response] unless there is a buffer available to accept data, the printer is online, and no error conditions exist (i.e. paper out, paper jam, platen open, etc). However, the channel program is structured to send a printer command (e.g., Print Data), then wait for a poll response, then issue a DSJ, and, if the DSJ is > 0, then issue a Read Status command. This sequence means that an offline printer will accept the first command, and then the channel program will hang at the WAIT, as PPR is denied. The driver sets a five-second I/O timeout when the channel program is started, which then expires at the WAIT, and then the driver outputs the "LDEV #6 NOT READY" message. The driver then executes the "idle" program, which does a WAIT, a DSJ, and a HALT 1. This seems wrong, because each of the seven DSJs in the program are preceded by WAITs, and if PPR is denied when the printer is offline or out of paper, then that status is never read. A hint might be in the description of the power-on condition: The first ARPP cause status to be read, afterward the idle channel program is run until the second ARPP is received. Also: At any point in the driver when a "2" is returned from a DSJ denoting I/O status should be interrogated, an extra wait [WAIT, DSJ] for an ARPP (denoting that a buffer is available to receive the next secondary) is required. Maybe this is saying that PPR is denied when the last buffer is filled, and when the printer is offline or faulted, BUT ONLY after the DSJ that notifies the host of the error is received? This would be a logical extension of the power-on situation and would also comport with the bit about an "extra wait" being needed when DSJ = 2 because the first PPR is triggered by DSJ > 0.