; CPU diagnostic section 4 (D420A3)
;   Parameter 1 = path to diagnostic tape.
;
; Preconfiguration is used.
;
; Configuration locations:
;
;     Location     Default Value  Contents
;   -------------  -------------  ---------------------------------------------------
;   DB+0   002000  000001          Switch Register setting
;   DB+1   002001  000000          Section Select Register setting
;   DB+2   002002  001030          Version and update level
;   DB+3   002003  000004          Section number
;   DB+5   002005  000000          Step number
;   DB+66  002066  000006      6   Magnetic Tape DRT number
;   DB+67  002067  000003      3   System Clock DRT number
;   DB+70  002070  000101     65   Selector Channel Maintenance Board DRT number
;
; NOTE: the step number in DB+5 is off-by-one low after step 30.


echo
echo
echo ----------------------
echo D420A3 - CPU Section 4
echo ----------------------
echo
echo Loading the diagnostic.


; Cold load the CPU diagnostics tape.

attach -e -r MS0 %130000-11016_Rev-1244_CPU-64K.tape
boot MS0
boot MS0
boot MS0
boot MS0


; PATCH: this fixes a bug in step 36 (MABS test) of PD420A3 (DB+2 = 001030).
;        It changes STOR DB+6 to STOR DB+7.
;        The unpatched diagnostic always skips step 36, as it thinks
;        that there is only a single memory bank present.

; deposit 015761 STOR DB+7
deposit 015761 051007


; Configure the devices for the diagnostic.

set CLK REALTIME


echo
echo Configuring the diagnostic.


; Configure the devices for the diagnostic.

set CLK  REALTIME
set SCMB enabled
set SCMB mx


; Preconfigure the diagnostic.
;
; Set the Internal Switch Register options:
;
;   bit  0 = select the external switch register
;   bit  1 = modify the Section Select Register
;   bit  2 = optional firmware is installed
;   bit  3 = not used
;   bit  4 = not used
;   bit  5 = not used
;   bit  6 = not used
;   bit  7 = not used
;   bit  8 = not used
;   bit  9 = not used
;   bit 10 = not used
;   bit 11 = loop on the last step
;   bit 12 = not used
;   bit 13 = halt at the end of each step
; + bit 15 = halt at the end of each pass

deposit 2000 000001


; Set the Section Select Register options:
;
;   bit  0 = change the magnetic tape device number
;   bit  1 = change the clock device number
; + bit  2 = use the clock to test I/O instructions
; + bit  3 = loop only once on each step
; + bit  4 = use the selector channel maintenance PCA to test I/O instructions
;   bit  5 = change the selector channel maintenance PCA device number
;   bit  6 = not used
;   bit  7 = not used
;   bit  8 = upper memory limit bank number MSB
; + bit  9 = upper memory limit bank number
; + bit 10 = upper memory limit bank number
; + bit 11 = upper memory limit bank number LSB
; + bit 12 = enable the power-fail test
;   bit 13 = not used
;   bit 14 = not used
;   bit 15 = not used
;
; If memory is set to 16 banks (1024K), the Module Violation Test cannot be run!

deposit 2001 034170


; Start the diagnostic.

echo
echo Starting the diagnostic.
echo Expect a PAUS instruction stop if successful.

set cpu stop=PAUSE
go


; Verify the pause stop (030032)

echo
echo Verifying the CIR register and continuing with a power failure.
echo Expect halt 14 if successful.

assert CIR=030032
set cpu nostop=PAUSE
power fail


; Verify HALT 14 for a successful power failure.

echo
echo Verifying the CIR register and continuing with a power restoration.
echo Expect halt 15 for successful completion.

assert CIR=030374
power restore


; End of the diagnostic.
;
; Verify HALT 15 for a successful pass.

assert CIR=030375