>>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 2 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000007 absolute read >>CPP cmd: Channel processor executing SLFT >>CPP data: 00.000772 000000 absolute write >>CPP serv: Completion delay 389 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 2 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000005 absolute read >>CPP cmd: Channel processor executing IOCL >>CPP data: 00.000013 000000 absolute write >>IMBA imbus: Channel 1 received opcode I/O Write command IOCL register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command IOCL register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Completion delay 2 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 2 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000004 absolute read >>CPP cmd: Channel processor executing SED2 >>CPP data: 00.000771 000001 absolute read >>CPP serv: Completion delay 2 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 2 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000004 absolute read >>CPP cmd: Channel processor executing SED2 >>CPP data: 00.000771 000001 absolute read >>CPP serv: Completion delay 2 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 2 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000003 absolute read >>CPP cmd: Channel processor executing WIOC >>CPP data: 00.000771 100000 absolute read >>CPP data: 00.000772 000000 absolute read >>CPP data: 00.000003 000000 absolute read >>IMBA imbus: Channel 1 received opcode I/O Write command SMSK register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command SMSK register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Completion delay 2 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 2 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000004 absolute read >>CPP cmd: Channel processor executing SED2 >>CPP data: 00.000771 000000 absolute read >>CPP serv: Completion delay 2 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 2 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000004 absolute read >>CPP cmd: Channel processor executing SED2 >>CPP data: 00.000771 000001 absolute read >>CPP serv: Completion delay 2 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 2 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000004 absolute read >>CPP cmd: Channel processor executing SED2 >>CPP data: 00.000771 000001 absolute read >>CPP serv: Completion delay 2 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 2 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000003 absolute read >>CPP cmd: Channel processor executing WIOC >>CPP data: 00.000771 100000 absolute read >>CPP data: 00.000772 000020 absolute read >>CPP data: 00.000103 000000 absolute read >>IMBA imbus: Channel 1 received opcode I/O Write command SMSK register 0 data 000020 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command SMSK register 0 data 000020 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP serv: Completion delay 2 service scheduled >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>IOP dio: Test I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTATSTB >>IMBA csrw: Status is SIO OK | DIO OK | Power OK >>IMBA iobus: Returned data 160000 with signals (none) >>IOP dio: Start I/O order sent to device number 125 >>IMBA iobus: Received data 000000 with signals DSTARTIO >>IMBA csrw: Channel program started >>IMBA imbus: Channel 1 asserts CSRQ >>CPP serv: Program delay 2 service scheduled >>IMBA iobus: Returned data 000000 with signals (none) >>CPP serv: Channel processor running >>IMBA imbus: Channel 1 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>IMBA imbus: Channel 1 returned data 040000 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 1 >>CPP data: 00.000770 000000 absolute read >>CPP cmd: Channel processor executing SIOP >>CPP data: 00.000771 000130 absolute read >>CPP data: 00.000773 101064 absolute read >>CPP data: 00.000543 000000 absolute read >>CPP data: 00.000540 101064 absolute write >>CPP data: 00.000543 140000 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command SIOP register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 asserts CSRQ >>CPP serv: Program delay 2 service scheduled >>CPP opnd: 00.101064 003400 Read Control secondary 20 count 1 burst 1 address 00100000 chain 0 termination 101071 | record mode | right byte >>CPP opnd: 00.101071 002005 Write secondary 05 count 1 burst 1 address 00100412 chain 0 | record mode | right byte >>CPP opnd: 00.101076 001000 Wait | CPVA 0 | response 1401 >>CPP opnd: 00.101100 001416 Read secondary 16 count 256 burst 1 address 00100424 chain 0 termination 101105 | record mode | left byte >>CPP opnd: 00.101105 001000 Wait | CPVA 0 | response 1306 >>CPP opnd: 00.101107 003400 Read Control secondary 20 count 1 burst 1 address 00100000 chain 0 termination 101114 | record mode | right byte >>CPP opnd: 00.101114 000600 Interrupt/Halt 0000 | CPVA 0 >>CPP serv: Completion delay 2 service scheduled >>CPP serv: Channel processor rescheduled >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | CSRQ1 | PRO >>CPP cmd: Channel processor servicing channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBSI register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 001130 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.000543 140000 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command SIOP register 0 data 000010 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000140 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is parity freeze | REN | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 4 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 4 (Poll mask) status is (none) >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 4 data 000200 with signals ADO | DDO | PRI >>GIC csrw: Register 4 (Poll mask) control is PP 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register F data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register F (Service info) control is DMA inbound | device 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000543 100000 absolute write >>CPP data: 00.000540 101064 absolute read >>CPP data: 00.101064 003400 absolute read >>CPP data: 00.101065 000001 absolute read >>CPP cmd: Executing Read Control secondary 20 count 1 burst 1 address 00100000 chain 0 termination 101071 | record mode | right byte >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>CPP cmd: [ read_chain_stuff ] >>CPP data: 00.101067 040000 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040076 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 076 sent to bus >>GIC buf: Command byte 076 loaded into outbound FIFO count 1 >>GIC buf: Command byte 076 unloaded from outbound FIFO count 0 >>GIC xfer: DIO | ATN | EOI | NRFD | REN | IFC | HP-IB Mnemonic >>GIC xfer: 3EH | ATN | | | | | Listen 30 >>GIC imbus: Channel 11 asserts CSRQ >>CPP serv: Program delay 2 service scheduled >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040100 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 100 sent to bus >>GIC buf: Command byte 100 loaded into outbound FIFO count 1 >>GIC buf: Command byte 100 unloaded from outbound FIFO count 0 >>GIC xfer: 40H | ATN | | | | | Talk 0 >>GIC imbus: Channel 11 asserts CSRQ >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040160 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 160 sent to bus >>GIC buf: Command byte 160 loaded into outbound FIFO count 1 >>GIC buf: Command byte 160 unloaded from outbound FIFO count 0 >>GIC xfer: 70H | ATN | | | | | Secondary 10H >>DC inco: Device 0 Quick Status command started >>DC cmd: Device 0 unit 0 Quick Status 2 executing >>DC serv: Device 0 unit 0 state Execution Send controller delay 4 service scheduled >>DC state: Device 0 transitioned from Command Ready state to Execution Send state >>GIC imbus: Channel 11 asserts CSRQ >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP cmd: [ read_burst_vs_record_setup ] >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 140000 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Reception enabled >>GIC buf: Transfer count 000 loaded into outbound FIFO count 1 >>GIC buf: Transfer count 000 unloaded from outbound FIFO count 0 >>GIC imbus: Channel 11 asserts CSRQ >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 8 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 8 (DMA bank) control is DMA disabled | bank 000 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101070 100000 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 9 data 100000 with signals ADO | DDO | PRI >>GIC csrw: Register 9 (DMA address) control is address 100000 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register A data 000001 with signals ADO | DDO | PRI >>GIC csrw: Register A (DMA byte count) control is byte count 1 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000543 100000 absolute read >>CPP data: 00.000543 100002 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register B data 000100 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) control is right byte | inbound | device 0 >>IMBA imbus: Memory controller received opcode Memory Read address 00100000 data 000000 with signals ADO | DDO | PRI >>IMBA data: 00.100000 000000 dma read >>IMBA imbus: Memory controller returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000540 101064 absolute write >>CPP serv: Channel processor idled >>CPP serv: IMBA completion service entered >>CPP data: 00.000774 100000 absolute write >>CPP serv: Channel processor running >>CPP serv: Channel processor idled >>DC serv: Device 0 unit 0 state Execution Send service entered >>GIC xfer: 02H | | EOI | | | | Data >>GIC buf: Tagged data byte 002 loaded into inbound FIFO count 1 >>GIC buf: Tagged data byte 002 unloaded from inbound FIFO count 0 >>IMBA imbus: Memory controller received opcode Memory Write address 00100000 data 000002 with signals ADO | DDO | PRI >>IMBA data: 00.100000 000002 dma write >>IMBA imbus: Memory controller returned data 000000 with signals ADN | DDN | PRO >>GIC cmd: DMA completed >>GIC imbus: Channel 11 asserts CSRQ >>CPP serv: Program delay 2 service scheduled >>DC inco: Device 0 Quick Status command completed with qstat 2 >>DC state: Device 0 transitioned from Execution Send state to Command Ready state >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | PRO >>CPP cmd: Channel processor servicing channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBSI register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000530 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>CPP data: 00.000543 100002 absolute read >>CPP data: 00.000540 101064 absolute read >>CPP data: 00.101064 003400 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP cmd: [ dma_chain_stuff ] >>CPP cmd: [ dma_burst_stuff ] >>CPP data: 00.101067 040000 absolute read >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register A data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register A (DMA byte count) status is byte count 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101065 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 9 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 9 (DMA address) status is address 100001 >>GIC imbus: Channel 11 returned data 100001 with signals ADN | DDN | PRO >>CPP data: 00.101070 100001 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register B data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) status is left byte | inbound | end state 0 | device 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101067 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register B data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) status is left byte | inbound | end state 0 | device 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register B data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) status is left byte | inbound | end state 0 | device 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040137 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 137 sent to bus >>GIC buf: Command byte 137 loaded into outbound FIFO count 1 >>GIC buf: Command byte 137 unloaded from outbound FIFO count 0 >>GIC xfer: 5FH | ATN | | | | | Untalk >>GIC imbus: Channel 11 asserts CSRQ >>CPP serv: Program delay 2 service scheduled >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040077 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 077 sent to bus >>GIC buf: Command byte 077 loaded into outbound FIFO count 1 >>GIC buf: Command byte 077 unloaded from outbound FIFO count 0 >>GIC xfer: 3FH | ATN | | | | | Unlisten >>GIC imbus: Channel 11 asserts CSRQ >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000540 101071 absolute write >>CPP data: 00.000540 101071 absolute read >>CPP data: 00.101071 002005 absolute read >>CPP data: 00.101072 000001 absolute read >>CPP cmd: Executing Write secondary 05 count 1 burst 1 address 00100412 chain 0 | record mode | right byte >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>CPP cmd: [ write_chain_stuff ] >>CPP data: 00.101074 040000 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040136 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 136 sent to bus >>GIC buf: Command byte 136 loaded into outbound FIFO count 1 >>GIC buf: Command byte 136 unloaded from outbound FIFO count 0 >>GIC xfer: 5EH | ATN | | | | | Talk 30 >>GIC imbus: Channel 11 asserts CSRQ >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040040 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 040 sent to bus >>GIC buf: Command byte 040 loaded into outbound FIFO count 1 >>GIC buf: Command byte 040 unloaded from outbound FIFO count 0 >>GIC xfer: 20H | ATN | | | | | Listen 0 >>GIC imbus: Channel 11 asserts CSRQ >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040145 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 145 sent to bus >>GIC buf: Command byte 145 loaded into outbound FIFO count 1 >>GIC buf: Command byte 145 unloaded from outbound FIFO count 0 >>GIC xfer: 65H | ATN | | | | | Secondary 05H >>DC state: Device 0 transitioned from Command Ready state to Command Wait state >>GIC imbus: Channel 11 asserts CSRQ >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP cmd: [ write_setup_EOI ] >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 6 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) status is parity freeze | REN | DMA inbound >>GIC imbus: Channel 11 returned data 000140 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000142 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is parity freeze | REN | DMA outbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 100002 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is IRQ | empty >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 asserts CSRQ >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 8 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 8 (DMA bank) control is DMA disabled | bank 000 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.101075 100412 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 9 data 100412 with signals ADO | DDO | PRI >>GIC csrw: Register 9 (DMA address) control is address 100412 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register A data 000001 with signals ADO | DDO | PRI >>GIC csrw: Register A (DMA byte count) control is byte count 1 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.000543 100002 absolute read >>CPP data: 00.000543 100002 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register B data 000120 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) control is right byte | outbound | device 0 >>IMBA imbus: Memory controller received opcode Memory Read address 00100412 data 000000 with signals ADO | DDO | PRI >>IMBA data: 00.100412 000065 dma read >>IMBA imbus: Memory controller returned data 000065 with signals ADN | DDN | PRO >>GIC buf: EOI | data byte 065 loaded into outbound FIFO count 1 >>GIC cmd: DMA completed >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | CSRQ1 | PRO >>CPP data: 00.000540 101071 absolute write >>CPP serv: Channel processor rescheduled >>CPP serv: Channel processor running >>GIC imbus: Channel 11 received opcode I/O Read command SPOL1 register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000020 with signals ADN | DDN | CSRQ1 | PRO >>CPP cmd: Channel processor servicing channel 11 >>GIC imbus: Channel 11 received opcode I/O Read command OBSI register 0 data 000000 with signals ADO | DDO | PRI >>GIC imbus: Channel 11 returned data 000530 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>CPP data: 00.000543 100002 absolute read >>CPP data: 00.000540 101071 absolute read >>CPP data: 00.101071 002005 absolute read >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 040377 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is parity error | status change | FIFO abort | poll response | SRQ | available | data | empty | DCL >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP cmd: [ dma_chain_stuff ] >>CPP cmd: [ dma_burst_stuff ] >>CPP data: 00.101074 040000 absolute read >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register A data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register A (DMA byte count) status is byte count 0 >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.101072 000000 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 9 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 9 (DMA address) status is address 100413 >>GIC imbus: Channel 11 returned data 100413 with signals ADN | DDN | PRO >>CPP data: 00.101075 100413 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register B data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register B (DMA control) status is right byte | outbound | end state 0 | device 0 >>GIC imbus: Channel 11 returned data 000120 with signals ADN | DDN | PRO >>CPP data: 00.101074 040000 absolute write >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 6 data 000140 with signals ADO | DDO | PRI >>GIC csrw: Register 6 (Control) control is parity freeze | REN | DMA inbound >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 0 data 040077 with signals ADO | DDO | PRI >>GIC csrw: Register 0 (FIFO) Data ATN | 077 sent to bus >>GIC buf: Command byte 077 loaded into outbound FIFO count 2 >>GIC buf: EOI | data byte 065 unloaded from outbound FIFO count 1 >>GIC xfer: 35H | | EOI | | | | Data >>DC inco: Device 0 Describe command started >>DC serv: Device 0 unit 0 state Execution Wait controller delay 4 service scheduled >>DC cmd: Device 0 Describe executing >>DC state: Device 0 transitioned from Command Wait state to Execution Wait state >>GIC buf: Command byte 077 unloaded from outbound FIFO count 0 >>GIC xfer: 3FH | ATN | | | | | Unlisten >>GIC imbus: Channel 11 asserts CSRQ >>CPP serv: Program delay 2 service scheduled >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000540 101076 absolute write >>CPP data: 00.000540 101076 absolute read >>CPP data: 00.101076 001000 absolute read >>CPP data: 00.101077 051401 absolute read >>CPP cmd: Executing Wait | CPVA 0 | response 1401 >>CPP data: 00.000543 100002 absolute read >>CPP data: 00.000543 100001 absolute write >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 1 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 1 (Status) status is controller | system controller >>GIC imbus: Channel 11 returned data 000030 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Read command RIOC register 2 data 000000 with signals ADO | DDO | PRI >>GIC csrw: Register 2 (IRQ conditions) status is empty >>GIC imbus: Channel 11 returned data 000002 with signals ADN | DDN | PRO >>GIC imbus: Channel 11 received opcode I/O Write command WIOC register 3 data 000240 with signals ADO | DDO | PRI >>GIC csrw: Register 3 (IRQ mask) control is status change | poll response >>GIC imbus: Channel 11 returned data 000000 with signals ADN | DDN | PRO >>CPP data: 00.000540 101076 absolute write >>CPP serv: Channel processor idled >>CPP serv: Channel processor running >>CPP serv: Channel processor idled >>DC serv: Device 0 unit 0 state Execution Wait service entered >>DC state: Device 0 parallel poll response enabled