12966A Buffered Asynchronous Communications Interface Notes =========================================================== Differences between the terminal and the diagnostic hood -------------------------------------------------------- Term: - N (P/EXT) to +5 - 2 and C open - D (BA, xmit data) to terminal, U open - E (CA, RTS) to terminal - F (CD, DTR) to X (CB, CTS) and Y (DSR) and AA (RLSD) - R (EXT CLK) and 18 (DIAG) open - S (BB, recd data) to terminal - 3 (SXX) and T (SCF) open Diag: - N (P/EXT) to GND - 2 (-CCNT7) to C (CA INH) - D (BA, xmit data) to U (SPARE) - E (CA, RTS) to Y (CC, DSR) and Z (CE, RI) - F (CD, DTR) to S (BB, recd data) and X (CB, CTS) - R (EXT CLK) to 18 (DIAG) - 3 (SXX) to T (SCF) and AA (CF) General Card Notes ------------------ FIFO: - Buffer empty sets when counts down to 0; cleared by CBE - Buffer half sets when counts up to 64; cleared by CBH - Buffer full sets when counts up to 128; cleared by CBF - fifo counter is 8 bits (0-255) - fifo counter counts up even if full; fifo counter count down inhibited if empty - first char into fifo passes thru to uart, but char counter increments anyway - ovrun/pe clocked on fifo put; set if fifo input not ready (xmit) or PE from UART (recv) - valid data forced 0 on xmit; is fifo output ready on recv Flag sets when: - devint, brkflg, spchflg, ovpeflg - bfull, bhalf, bempty, chmode * valdata IFF not dcpc SRQ FF inputs: - PRESET: master reset - CLEAR: CLF executed - D: dcpc * drq * -lockout - CLK: t3 + encnt - drq = valid data avail [recv] + fifo not full [xmit] - encnt = fifo clocked Loopback transmission: - BA (txout) tied to SPARE for diag, so read status always shows BA state - DIAG (out) tied to EXT CLK (in) for diag, so setting DIAG to 1 then 0 generates one UART clock (only when EXT CLK is selected, i.e., baud rate = 0000) - clock pulse to UART is 0-1-0, i.e., positive-going pulse - 16 UART clocks shifts one bit to BA - UART txout is high when idle (so SPARE is high) - start bit (1) is 0, then data bits (5-8, msb to lsb), then stop bits (1/1.5/2) are 1 - if parity inhibited, it is omitted, not forced to 0 UART Transmission Timing: - assume master clear, first byte in UART holding register, second byte in FIFO, 5-N-1 - 1st pulse loads xmit reg - 2nd pulse puts first bit (start bit) on output (time T1) - 3rd thru 16th pulse keeps start bit on output (times T2-T15) - 17th pulse keeps start bit on output (time T16) - 18th pulse puts first data bit on output (T1) - 19th thru 97th pulses process data bits 2-5 - 98th pulse puts first stop bit on output (T1) - 99th thru 111th pulse keeps stop bit on output (times T2-T14) - 112th pulse keeps stop bit on output (time T15), xmit reg loaded with 2nd byte from FIFO (or terminates if no data) - 113th pulse puts first bit (start bit) on output (time T1) [etc.] - note that diag actually writes the wrong "start" bit in SDOUT first bit is CD = 0, which is another mark, so is ignored then real start bit (CD = 1) is written, followed by data bits and optional parity bit the first stop bit is omitted! Clocking the UART: - xmit stays idle until THR loaded (i.e., baci_uart_thr != 0) - recv stays idle until start bit (0) seen (i.e., baci_icw & OUT_CD != 0) - xmit gens 16 clocks per bit, except 8 clocks for 1/2 stop bit - recv gens 16 clocks per bit, including for 1/2 stop bit (so 1.5 treated as 2) Loopback reception: - CD (dtr) tied to CB (cts) and BB (data in) - BB is always presented on TEST - TEST is inverted from CD Echo: - echo only if receive mode - for term, reception copies character to transmission - for diag, CD tied to BB, through echo gate, to BA tied to SPARE (so SPARE follows inverted CD) Break detection: - uart sets FE (framing error) when stop bit is missing - uart transfers byte to receiver holding register, sets DR - DR shifts byte into fifo - uart receiver then idles until BB returns to mark (= 1) state; doesn't start next char until then - break counter looks for 160 contiguous 0 bits on BB, then sets break flag - meaning: no stop (1) bit but less than 160 0 bits means FE but no break flag; as FE isn't brought out, it's lost Break test: - sets CD = 1, so BB = 0 (spacing) - does 16 * 38 = 608 uart clocks - sets CD = 0, so BB = 1 (marking) - looks for break bit Problems under RTE ------------------ - no flag in CHAR MODE after ACK received in response to ENQ (not found by diag) driver action: - sets XMIT mode - outputs ENQ - delays 150 usec (~125 instr) to "let char ripple thru fifo" - sends words 1 (CHAR mode), 4 (RECV mode), and 5 (CLR INTs) to config xfer - sends word 5 (again) to clear interrupt flags - sets control >> flag now sets, because lockout = 0, srq = 0, RECV mode, CHAR mode, and FIFO not empty (from ENQ not xmitted yet)! >> problem is that card is turned to receive mode before char is transmitted from UART!!! >> fixed by checking for put != get for recv mode not empty, instead of fcount == 0 - buffer empty interrupt is occurring when ENQ transmitted shouldn't, because card turned to recv mode means that ENQ transmitted will NOT decrement counter; only char LIx will decrement counter >> also note that putting a char should reset svc time to get full time before char xmit otherwise, might xmit on next cpu instruction, which driver is NOT expecting - ENQ occurs with count = 1, so goes to fifo instead of THR, even though THR is empty Performance Issues ------------------ Slow ENQ/ACK handshaking: - xmit times OK - ENQ to ACK is ~61,000 instructions! - ENQ to ACK is ~277,000 instructions on another try ~318,000 instructions on a third try! - looks like the driver does 3 ENQ/ACKs on each full line, so ~900,000 instruction delay per line output!!! - trying CN,10,25B sends ESC^ and DC1; DC1 to ESC returned is ~411,500 instructions, so this may be a Telnet turnaround time - rest of esc sequence follows at "poll time" intervals - Crosstalk is about the same speed as QCTerm (is there some ENQ/ACK turnaround time spec?) >> much faster if ENQ/ACK handled in simulator and never passed to client Unresponsive to key during output: - Problem: not responsive to key press during output (break mode) SETEM calls CDSET with B = 5 (char mode, recv mode, clear int flags) - Seems driver only checks at end of each line? Does ENQ; if not ACK, assumes key hit and schedules PRMPT There are three ENQ/ACK sequences at the end of each line, plus an embedded sequence every 33 characters within a line. The driver checks the response to an ENQ. If it's not an ACK, an interrupt is signalled. Response checked: - 1st sequence: no - 2nd sequence: yes - 3rd sequence: yes (because output request is complete?) - emb sequence: no >> Will have to delay char reception in XMIT mode until second or third ENQ/ACK for responsiveness. >> Why is "SOH -" received from qcterm at startup? >> Does CAPSLOCK mode also upshift ESC^ terminal responses? no, because status bytes are never alphabetic Telnet Overhead: - Optimization: dump entire FIFO contents in a single Telnet send, rather than one char at a time. Time improvement on a long file dump is ~ 2:1. At poll time = 1646 (9600 baud), instr count from STC to service call is: - 1042 for mid-line output (33 characters) - 1506 for end-of-line output When driver exits, it clears device interrupt status bits and then issues STC to enable IRQ. If the poll time is too short, service call will occur and FIFO will be emptied before interrupts are cleared, meaning that the "FIFO empty" interrupt will be lost. >> Set poll time for "external" to the 9600 baud rate (1646 instructions).