HP 12584A Multiplexer ===================== General: - One or two identical cards in a system; cards need not be adjacent. - First card connects 16 RS-232 Tx lines to the 16 bits of the input bus and 16 RS-232 Rx lines to the 16 bits of the output bus; serial-to-parallel and parallel-to-serial conversions are done. DTR for all lines is set by STC and cleared by CLC. Card interrupts every 1.136 mS (periodic). - Second card connects 16 RS-232 RI + CD lines to the 16-bit input bus to indicate modem states and 16 RS-232 DTR lines to the 16-bit output bus (so DTR is individually controlled to drop connections on demand). Card does not interrupt unless programmed explicitly via STC and STF; the oscillator is not connected to flag buffer logic. Card is polled by the TSB scheduler. - Teleprinter cable uses TX, RX, and DTR. - Data set cable uses TX, RX, RI, CD, and DTR. RI + CD assertion denies input line; drop asserts input line. Asserting DTR denies output line. - Phones card configuration is set by PHONES command during system operation. - BREAK key is used to stop program execution or listing (detected how?). Diagnostic(s): - 20439A binary, 20550A source listing dated 5/1/68 is in back of 12584-9001 manual followed by diag manual (12594-9003, May-1969, 4 pages) printed messages using SIO TTY driver, but only 9 messages - 24175-80001 Rev A for 2116/15/14 no tty output; uses error halts only seems to have many more error halts - 24202-80001 Rev A for 2100 no tty output; uses error halts only seems to be same as 24175 but w/different CPU timing - test connector connects outputs to inputs, and includes lamps to indicate whether DTR is "off" or "on". Logic: - standard flag buffer, flag, irq, control logic - popio sets flag and also sets output register to all ones - crs clears control - control enables irq and also sets DTR high if CPU is running (RUN signal) - ioi gates current rs232 tx lines onto I/O bus; there are no latches - internal clock runs at 880 Hz (1136 uS period) - clock (output on pin 22) looped to "flag storage FF" (input on pin Z) - flag storage FF sets on clock pulse - flag buffer sets on rising edge of Z (end of clock pulse) * SIR * ~FLAG - flag (i.e., flag buffer * ENF) clears flag storage FF Operation: - card causes an interrupt every 1.136 mS; 8 interrupts per serial bit, 88 interrupts per serial character (1 start + 8 data + 2 stop bits). - on interrupt, CPU does LIA and tests input lines for start (0) bits when a start bit is seen, CPU counts 12 interrupts (8 for start bit + 4 to get middle of 1st data bit) then tests input lines again to obtain data. This repeats every 8 interrupts until 2 stop bits received - on interrupt, CPU assembles output word. If first call after output byte is available, sets start (0) bit, else sets next data bit. Then waits 8 interrupts before setting next bit. Before exiting each interrupt, does OTA to output current line state. - line state is 1 for idle input or idle output - all mux I/O is done in response to interrupt, so all output is synchronous (i.e., no OTAs except at interrupt time) - Serial data is transmitted LSB first. Simulation: - Need timer unit at 1.136 mS real time; this must run continuously, because output isn't done except when interrupt occurs, so must poll for output as well as input. This prevents idling, but then TSB can't idle in any case. - Do NOT need individual line service entries because all lines are updated synchronously at interrupt (timer service) time. - Don't really need a poll unit; input and connection polls can be done by timer unit. But may be simpler to have one at 10 mS calibrated time. - Probably need FASTTIME, else limited to 110 baud * sim multiplier (so maybe 1200 baud calibrated). But can't speed up that much, else saturates CPU. - Must buffer one character if poll unit used, so that completing one input does not have to wait for next calibrated 10 mS to get next character. - Need 16-element arrays for tx_data, rx_data, tx_cntr, rx_cntr, rx_buffer. Poll service: -- start_stop_bits = 2#11_0000_0000_0 tmxr_poll_conn (mptr) tmxr_poll_rx (mptr) for line in lines'range loop if rx_buffer (line) = empty -- empty is 0, occupied = TMXR_VALID + char and then tmxr_rqln (lptr) > 0 then -- char is present rx_buffer (line) := Shift_Left (tmxr_getc_ln (lptr)) or start_stop_bits; end if end loop Timer service: -- receive section input_reg := not 0 -- start with all input bits = 1 for line in lines'range loop if rx_cntr (line) > 0 then -- currently receiving if rx_data (line) and 1 = 0 then -- if current bit is 0 input_reg := input_reg and not bit (line) -- then clear corresponding input bit end if rx_cntr (line) := rx_cntr (line) - 1 -- decrement counter if rx_cntr (line) mod 8 = 0 then -- if end of current bit rx_data (line) := Shift_Right (rx_data (line)) -- move next bit into place end if elsif rx_buffer (line) /= empty then -- not receiving, character waiting rx_data (line) := rx_buffer (line) -- get from buffer rx_buffer (line) := empty -- clear buffer input_reg := input_reg and not bit (line) -- set start bit rx_cntr (line) := 87 -- set counter = 11 * 8 - 1 end if end loop -- transmit section (sends char before two stop bits are output) for line in lines'range loop if tx_cntr (line) > 0 then -- currently transmitting if tx_cntr (line) mod 8 = 0 then -- if start of new bit tx_data (line) := Shift_Left (tx_data (line)) -- move old bits to make room if output_reg and bit (line) /= 0 then -- if new bit is 1 tx_data (line) := tx_data (line) or 1 -- set corresponding char bit end if end if tx_cntr (line) := tx_cntr (line) - 1 -- decrement counter if tx_cntr (line) = 0 then -- if char done tmxr_putc_ln (tx_data (line)) -- transmit data tmxr_poll_tx (mptr) -- poll to send end if elsif output_reg and bit (line) = 0 then -- if start bit tx_data (line) := 0 -- clear output char tx_cntr (line) := 71 -- set counter = 9 * 8 - 1 end if end loop set flag storage if flag = clear then set flag buffer end if 24202 Diagnostic Procedure - load PTR - P = 2, S[5:0] = mux SC, S[11:6] = oscillator frequency (*) - PRESET, RUN - HLT 107074 (hardware initialized) - S = 000000 - RUN - HLT 107077 (configuration complete) - S = 000001 (use external register) - PRESET, RUN - HLT 102077 (good pass) Oscillator frequency (MSB determines): 11 = 2622 Hz loop count = 8115-8245 (330 baud) 10 = 2384 Hz loop count = 8937-9091 (300 baud) 9 = 1748 Hz loop count = 12272-12470 (220 baud) 8 = 1192 Hz loop count = 18050-18340 (150 baud) 7 = 874 Hz loop count = 24785-25285 (110 baud) Switch Register: 14 = suppress error halts 13 = loop on current test 0 = use external switch register Oscillator test does: - CLF - SFS (syncs program with oscillator pulse) - CLF - cntr = 0 - ISZ, SFS, JMP loop to increment counter - CLF - ISZ, JMP loop to repeat above loop 150 times - cntr should be above (+) lower limit, below (-) upper limit