HP 21xx/1000 Operational Notes ============================== ---------------- Hardware History ---------------- 21xx Family (Date Introduced): · 2116 : 1966 · 2115 : 1967 · 2114 : 1968 2100 Family (Date Introduced): · 2100A : 1971 - 2100S : 1000 Family (Date Introduced): · 1000 M-Series : 1974 (introduced as the 21MX) · 1000 E-Series : 1976 (introduced as the 21MXE) · 1000 F-Series : 1979 L-Series Family (Date Introduced): · 1000 L-Series : 1979 · 1000 XL-Series : 1980 A-Series Family (Date Introduced): · 1000 A600 : 1982 · 1000 A700 : 1982 · 1000 A900 : 1983 · 1000 A400 : 1986 · 1000 A990 : 1991 Relative CPU performance, normalized to a 1000 E-Series: - 2114 : 0.22 - 2115 : 0.37 - 2116 : 0.42 - 2100 : 0.55 - 1000-M : 0.45 - 1000-E : 1.0 - 1000-F : 1.4 - 1000-L : 0.3 - A400 : 1.1 - A600 : 1.0 - A700 : 1.67 - A900 : 3.3 - A990 : 6.7 ---------------- Software History ---------------- - SIO : 1966 - BCS : 1966 - RTE : 1968 - DOS : 1969 - MTS : 1970 - DOS-M : 1971 - RTE-B : 1972 - RTE-II : 1972 (2226, 2301, 2440) - RTE-C : 1972 - DOS-III : 1975 - RTE-III : 1976 (2126, 2140) - RTE-Mxxx : 1977 (2226, 2301, 2440, 2540) - RTE-IVA : 1978 (2226, 2301, 2440) - RTE-IVB : 1979 (2326, 2340, 2440, 2540) - RTE-IVE : 1981 (2301) - RTE-6/VM : 1981 (2326, 2340, 2440, 2540, 4010, 5010, 5020) - RTE-A.1 : 1982 - RTE-A : 1983 ------------------------ RTE Driver Control Words ------------------------ RTE EXEC calls using request codes 1 (read) and 2 (write) include a control word that specifies the device and device-specific behavior. The word has the following format: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - | U | - | Z | - | X | A | K | V | M | Logical Unit | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Setting the U bit forces the call be unbuffered, even if the device is buffered. Setting the Z bit passes two optional parameter words to the driver. The X, A, K, V, and M bits are defined by the various drivers as follows: DVR10 (calcomp) - no bits DVR12 (2767) - no bits DVR11 (2892) - read V+M 0-3 = Hollerith, Column Image Binary, Hollerith, Packed Binary DVR15 (7261) - read V+M 0-3 = Hollerith, Column Image Binary, Hollerith, Packed Binary DVM72 (12566) - rw K+V = special handling DVR33 (12732) - rw X+A 11 = read/write with tight margin DVR10 (7210) - M = binary A 0/1 = new/old size DVR00 - M 0/1 = ASCII/binary V 0/1 = tape input by buffer length/tape input by first byte length K 0/1 = keyboard read not echoed/keyboard read echoed A 0/1 = teleprinter punch ASCII or binary per M/ASCII only X 0/1 = regular/special formatting DVR37 (HPIB) - M 0/1 = ASCII/binary X 0/1 = normal/transparent DVA13 (TV) - all bits = special handling DVA12 (26xx) - V 0/1 = cctl/no cctl X 0/1 = normal/transparent (honest; overrides V bit) DVR05 (264x) - M 0/1 = ASCII/binary DVA05 K 0/1 = keyboard read not echoed/keyboard read echoed A 0/1 = normal/block read (A set requires X set) X 0/1 = normal/transparent DVB12 (2608) - V 0/1 = cctl/no cctl A 0/1 = buffer is data/buffer is VFU definition X 0/1 = normal/transparent (honest; overrides V bit) DVR32 (7905) - X 0/1 = normal/verify after write DVC12 (2608S) - V 0/1 = cctl/no cctl A 0/1 = buffer is data/buffer is VFU definition X 0/1 = normal/transparent (honest; overrides V bit) DVS23 (7974) - X 0/1 = normal/transparent DVR23 (7970) - M 0/1 = ASCII/binary X 0/1 = normal/transparent DVA47 (3070) - M 0/1 = ASCII/binary V 0/1 = single rw/rw with offline input K 0/1 = keyboard read not echoed/keyboard read echoed A 0/1 = read from keyboard/reader; write to display/printer X 0/1 = standard read/write-read ----------------------------------- Dual-Channel Port Controller (DCPC) ----------------------------------- A correctly designed I/O card can request that DCPC steal consecutive I/O cycles during a transfer. Such a card must assert SRQ by T4 (E/F) or T5 (M) of each I/O cycle. The standard I/O circuitry asserts SRQ along with the device flag at T2 and so is capable of stealing only every other cycle. Cards must be FIFO buffered to steal every cycle, with SRQ remaining asserted while the buffer is not full (writing) or not empty (reading). As an example, the 12821A Disc Interface is capable of asserting SRQ to steal every I/O cycle. The diagnostic for this card tests for this by starting a multi-word DCPC transfer and then testing for completion after one instruction. The I/O instruction (LIA) used to obtain the DCPC word count will be held off by a CPU freeze until the DCPC transfer completes and so will return zero. The 12821A interface does not clear SRQ on CLF, as most interfaces do. Instead, SRQ is asserted continuously for the duration of the transfer and is denied by interface logic when the transfer ends or when the FIFO is empty (for a read) or full (for a write). So if the FIFO indicates that more data can be accommodated after the current DCPC cycle completes, SRQ will remain asserted, and DCPC will steal the next cycle as well. DCPC interacts differently with the M-Series and the E/F-Series CPUs. For the M-Series, a DCPC cycle freezes the CPU if it attempts an I/O cycle (including IAK) or a directly-interfering memory cycle. An interleaved memory cycle is allowed (a memory cycle takes about 1/2 of an I/O cycle). Otherwise, the control processor is allowed to run. For the E/F-Series, a DCPC cycle freezes the CPU for the entire time. Therefore, during consecutive I/O cycle steals, the M-Series CPU will run until an IOG instruction is attempted, whereas the E/F-Series will freeze completely. (The 211x/2100 behave as the E/F, i.e., DMA freezes the CPU entirely.) In hardware, then, the E/F-Series will freeze as soon as the diagnostic starts DCPC. The M-Series will execute until the diagnostic attempts the LIA instruction, whereupon it too will freeze. On all machines, the freeze terminates when the DCPC count expires, and so the LIA returns zero. --------------------------- Initial Binary Loader (IBL) --------------------------- The IBL microcode processes bits 15-14 (to select the loader) and bits 11-6 (to select the boot device). A memory write/read test is done to identify memory size. The test starts at 077777 and goes down by 010000 each time. The overflow flag will be set if there is no memory in the machine, or if the select code of the boot device is less than 10 octal. As each instruction is read from the ROM, it is checked to see if it is an I/O instruction by ANDing with 172000 and comparing the value to 102000 (this is actually done by ANDing with 172000 and then XORing with 075777; the final value will be 177777 if the result of the AND was 102000). If it is, then it is further checked to see that it is not a halt instruction (by ANDing the instruction with 000700; the result will be 000000 if the instruction was a halt) and that the select code is >= 10 octal. If all of these tests pass, the target select code is modified by adding the boot select code minus 10 octal to the instruction; this allows the loader to be configured for devices that require multiple adjacent cards. Then the (possibly updated) instruction is written to memory. The target select code is added unconditionally to the value in word 63. This is intended to configure DMA control word 1. On completion of the IBL, P is set to the first instruction (0x7700), M is set to the penultimate loader address (0x7776), and T is set to the contents of memory addressed by M. Word 64 will contain the twos-complement of the starting address of the loader. ----------------- M and T Registers ----------------- When the machine halts, the front panel microroutines display the T register after initiating a read of memory via the M register. So T always reflects the contents of memory addressed by M. As the DMA card contains its own M register, the CPU M register is not affected by DMA cycles, and therefore DMA operations may be excluded from further consideration. With respect to the M register, the 21MX-M and the 21MX-E and -F behave differently when entering the halt mode. When the 21MX-M is halted, M retains its previous value. Clearing the CPU run flip-flop results in diverting the next attempted transfer to microinstruction location 0 (the start of the FETCH routine) to the front panel microcode instead. Because this diversion bypasses the fetch of the next instruction, the M register will contain whatever value had been set by the execution of the previous instruction. The 21MX-E and -F perform a similar diversion, although the transfer occurs at the execution of the JTAB micro-order within the FETCH routine. To improve execution speed, though, these machines anticipate execution of memory-reference instructions by loading the M register with what would be the operand address in an MRG instruction before checking for halts. For a non-MRG instruction, the value in M will be meaningless, and for an MRG instruction, M will be the operand address of the instruction that was not executed due to the pending halt, i.e., that of the next instruction. To meet M-series users' expectations, particularly that M point to the HLT instruction that halted the machine, M (and therefore T) are explicitly set upon entry to the front panel halt-state microcode. For machine halts due to the front panel HALT button being pressed or due to execution of a HLT instruction not in an interrupt trap cell, M is set to P-1. Note that for operator halts following multiword instructions, this means that M will point to the last word of the multiword instruction, rather than the opcode of that instruction. If, however, the machine halts due to the execution of a HLT instruction in an interrupt trap cell, M is set instead to the address of the trap cell (P still points to the next instruction to be executed). References: "HP 21MX M-Series Computer RTE Microprogramming Reference Manual," 02108-90032, October 1976; "HP 1000 E-Series and F- Series Microprogramming Reference Manual," 02109-90004, April 1980; "HP 1000 M/E/F-Series Computers Engineering and Reference Documentation, 92851-90001, March 1981. ------------------ Firmware Detection ------------------ HP software executes several instructions that may be undefined or unimplemented in order to detect the installation of certain firmware. The programs depend on the behavior of the CPU when the firmware is missing. Enabling the UNIMPL and/or UNDEF simulation stops will cause software execution to stop. These instructions are known to be tested by the listed programs: Instruction Program Reason for Test ------------ -------- ---------------------------------------------------- 100060 TIMER RTE-6/VM Use of M-Series OS instruction software replacements 101100 RRR16 DiagConf Identification of 2114 by absence of EAU 105226 .FLUN Identification of 2100 FFP by absence of .FLUN 105355 RTE-6/VM OS self-test 105477 RTE-6/VM VMA self-test 105617 SIGNAL/1000 self-test ------------- CPU Detection ------------- The 24296-90001 Diagnostic Configurator runs a series of tests to determine the type of CPU under which it is running. These tests are: * Store in S, read S, compare; if <>, 2115/2116, else 2114/2100/21MX (LDA =B172525 / OTA 1 / LIB 1 / CPA B) * (2115/2116) If mem size > 8K, then 2116, else 2115 * If EAU, then 2100/21MX, else 2114 (LDA =B172525 / CLB / RRR 16 / SZA) * If S-bus floats to zero, then 2100, else 21MX-M/E (LIA 6 / SZA -- 21MX manual says LIA 6 returns 177777B) * If TIMER (100060) instruction skips, then 21MX-M, else 21MX-E (CCB / TIMER / JMP x -- behaves as MPY in 21MX-M, resume P + 2) The S-bus of the 21MX is implemented in tri-state TTL and is pulled high. The S-bus of the 2100 and earlier machines is implemented in CTL and is pulled low. Select codes 1-7 are on the S-bus, and so non-decoded states (e.g., LIA 6) return -1. Select codes > 10B are on the I/O bus (CTL) and so appear low when not decoded. Select code 0 is gated from the I/O bus on 21MX machines for compatibility with 2100 and earlier systems and so read as zero. In summary: * LIA 0 returns 0 on all systems. * LIA 1-7 (non-decoded) return -1 on 21MX and 0 on earlier systems. * LIA 10-77 (non-decoded) return 0 on all systems. --------- CPU Speed --------- The 24296-90001 Diagnostic Configurator provides a one millisecond timer for use by the diagnostic programs. The timer is a two-instruction software loop, plus four instructions of entry/exit overhead, based on the processor type. The values provided are: Loop Instr CPU Count /msec ------ ----- ----- 2114 246 496 2115 246 496 2116 309 622 2100 252 508 1000-M 203 410 1000-E 1573 * 1577 * The E-Series TIMER instruction is used instead of a software loop. TIMER re-executes an internal decrement until the supplied value reaches zero. ------------------ Standard Equipment ------------------ According to the diagnostic configurator manual, the following systems were equipped as indicated: Feature 21MXE 2100A 2116C ------------------------ ----- ----- ----- Power-fail/auto-restart S S O Extended arithmetic unit S S O DMA/DCPC O O O Memory parity check S S O Memory protect O S O Floating point S O N Dynamic mapping system O N N IOP firmware O O N NOTES: * S = standard, O = optional, N = not available. * Memory protect was standard on the 2100 but could be disabled with a jumper. * The 2114B had only a single-channel DMA. ------------------------------------ 12731A Memory Expansion Module (MEM) ------------------------------------ MP/MEM Interaction: * MP asserts CTL5 when MP is enabled. This enables the MEM "protected mode". If MP isn't present, CTL5 is denied, so MEM works as though MP was present but not enabled. * MP asserts MPCND when an MPCK micro-order is executed and the target address is above the lower bound of protected memory (i.e., 2 or above if not a JMP instruction, else 0 or above). Note that this is not the qualifier for an MP fence check (MP viol = CTL5 * MPCK * lower bound < addr < upper bound), as MPCND doesn't depend on CTL5 or the upper bound. * MEM asserts MEV if MEM violation detected with MAPON * CTL5 asserted. This would be due to: -- privileged instruction attempted -- read from a read-protected page -- write to a write-protected page (write = MPCND asserted) -- write to an unmapped base-page (write = MPCND asserted) -- write using the alternate map (write = MPCND asserted) * When the alternate map is enabled, writes are permitted only in the unprotected mode, regardless of page protections or the MP fence setting. This behavior is not mentioned in the MEM documentation, but it is tested by the MEM diagnostic and is evident from the MEM schematic. Referring to Sheet 2 in the ERD, gates U125 and U127 provide this logic: WTV = MPCNDB * MAPON * (WPRO + ALTMAP) The ALTMAP signal is generated by the not-Q output of flip-flop U117, which toggles on control signal -CL3 assertion (generated by the MESP microorder) to select the alternate map. Therefore, a write violation is indicated whenever a memory protect check occurs while the MEM is enabled and either the page is write-protected or the alternate map is selected. The hardware reference manuals that contain descriptions of those DMS instructions that write to the alternate map (e.g., MBI) say, "This instruction will always cause a MEM violation when executed in the protected mode and no bytes [or words] will be transferred." However, they do not state that a write violation will be indicated, nor does the description of the write violation state that this is a potential cause. Presumably, this behavior is used because the MP fence setting would apply to writes in the alternate map, although if MP is enabled, the fence would have been set for the needs of the program executing in the current map. Requiring MP to be disabled ensures that the fence setting will not be used to qualify write permissions. * If MPV and MEV both occur (e.g., write below fence to write-protected page), MEV takes precedence in setting the MP's MEV flag, i.e., SFS 05 skips. Note that the MEM ERD says that MPCND asserts only if a write is above the MP fence, implying that a concurrent MP/MEM violation cannot occur, and therefore that the MEV flag would test as clear for a write below the fence to a write-protected page. This is wrong. Actually, MPCND asserts for writes above the LOWER-BOUND of protected memory; MPCND isn't conditional on the fence value at all. // *** DM viols mustn't occur if MEM off (MAPON is viol qualifier)! // // NOTE: if BP rd/wr prot, viol even if access is to unmapped part // MEBEN affects memory controller but not violation logic // bp viol will be inhibited by -MEBEN, but not rd/wr viol // // jmp to unmapped portion with DMS OFF will not fail because MAPON is viol qualifier Protected Mode -------------- The literature regarding bit 11 of the MEM status register (the protected mode bit) is contradictory. The 21MX Computer Series Reference Manual (02108-90002) says, "If the DMS and memory protect are enabled, the computer is in the protected mode," implying that both are needed. However, the HP 1000 M/E/F-Series Computers Engineering and Reference Documentation (92851-90001) says on page V-11, "The protected mode is enabled whenever the memory protect card is enabled," but then on page V-24 says, "The protected mode is entered by turning the mapping system on and executing a STC 05 assembly instruction which sets CTL5- low to the MEM." As it turns out, the bulk of the documentation is wrong. Checking the schematics reveals that the protected mode bit is simply the CTL5- signal inverted and passed through. CTL5- is generated on the MP PCA and is the inversion of the MP control flip-flop output; the DMS enable flip-flop on the MEM is not involved. So the protected mode bit should be on when MP is on, regardless of the state of DMS. ---------------------------- 12892A/B Memory Protect (MP) ---------------------------- STC 05 turns on MP CLC 05 is NOP STF 05 turns on PE interrupt capability CLF 05 turns off PE interrupt capability SFS 05 skips if DMS interrupt SFC 05 skips is MP interrupt LIA 05 loads violation register (bit 15 0/1 = MP/PE viol) OTA 05 stores fence register Jumper Settings: W3 - HLTPE - OUT - in for obey PE HALT switch on CPU, out for PE interrupt always W4 - MX - IN - in for 21MX-M, out for 21MX-E W5 - JSB - IN - in for JSB 0/1 legal, out for JSB 0/1 illegal W6 - INT - IN - in for indirect interrupt holdoff, out for no holdoff W7 - SEL1 - OUT - in for all I/O legal, out for only SC 01 I/O legal W8 - RME - OUT - in for MEM restores map at IAK, out for MEM stays in system map Jumper Features: * W5 (JSB) -- out decodes JSB for (JMP + -A01) violation [JSB 0/1 are illegal] -- in inhibits JSB decode [JSB 0/1 are legal] * W6 (INT) -- out forces -MPINTON low always (when MP enabled) [no ind holdoff] -- in sets -MPINTON low after three indirect levels [ind holdoff] * W7 (SEL1) -- out sets SEL1 high when I/O to SC 1 [I/O to SC 1 except HLT legal] -- in forces SEL1 high always [I/O any SC except HLT legal] I/O viol = HLT + -SEL1 Mem viol = MPCARRY * (JMP + -A01) (MPCARRY = EA below fence) MP checks occur on: * JMP, JLY, JPY below fence * ISZ, JSB, STA, STB, DST, SAX, SAY, SBX, SBY, STX, STY, MBT, SBT, CBS, SBS, MVW below fence and above 1 (i.e., A and B register accesses are OK). * I/O instruction except SC 01 (overflow/S register) ----------------------------------- When a PE occurs, if A1S1 is HALT PE, CPU halts. If A1S1 is INT/IGNORE, then if CLF 05 done to disable IRQ, PE is ignored and FP LED illuminates. If STF 05 done, PE interrupts and FP LED extinguishes. PON clears CNTRLFF, FLAGFF, FLGBFF (MP is off) PON sets PARENFF (parity checking is on) PARENFF sets by STF 05, or PON (==> enables PE checks) PARENFF clears by CLF 05 or PE (==> disables PE checks) PARERRFF sets by PE (==> selects PE viol for LIA) PARERRFF clears by STC 05 or PON (==> selects MP viol for LIA) CNTRLFF sets by STC 05 (==> enables MP checks) CNTRLFF clears by PON or executing a HLT or non-IOG trap cell instruction during IAK (==> disables MP checks) FLGBFRFF sets by PE (regardless of ION) or MPV * ION FLGBFRFF clears by PON, IAK FLAGFF sets by FLGBFRFF set FLAGFF clears by PON, FLGBFRFF clear FLAGFF causes IRQ and determines priority chain MEVFLGFF sets by MEU violation MEVFLGFF clears by STC 05, PON MEVFLGFF tested by SFS 05, SFC 05 (n.b., NOT FLAGFF!) PE causes FP PE LED to set IAK causes FP PE LED to clear NOTE: FLAGFF clearing by FLGBFRFF clearing is not the usual I/O procedure. In a regular I/O card, FLGBFRFF clears on IAK (to clear IRQ), but FLAGFF stays set until CLF. For MP, the FLAGFF directly tracks the FLGBFRFF, clocked by ENF. ------------------------------- MPCK MICRO-ORDER Invoked for: All IOG instructions ST* JSB ISZ JMP DST (both M and M+1) ------------- S*X, S*Y STX, STY SBS, CBS MVW SBT (as a word address) MBT (calls SBT internally) JLY, JPY, JRS ---------------- XMM, XS* DJP, SJP, DJS, SJS UJS, UJP MBF, MBI, MBW, MWF, MWI, MWW US*, SSM, SY*, PA*, PB* NOTE: MEM status is updated before MPCK for DJP, DJS, JRS, SJP, SJS, UJP, UJS. ------------------------------------------- MP and DM violation checks appear to occur in parallel, with DM violation reporting taking precedence (i.e., SF* only checks MEU violation flag). For example, a JSB to an address below the MP fence AND on a write-protected page will cause both an MP and a DM violation. A single INT5 will occur, and as the MEU violation flag is the only one reported, it will appear as a DM error. ---------------------------------------- 12936A/12620A Privileged Interrupt Fence ---------------------------------------- The privileged interrupt fence card is required for 12920A multiplexer operation under RTE. The 12936A Privileged Interrupt Fence card was superceded by the 12620A Breadboard I/O card. Bitsavers has the 12936A manual, and page 5-4 of the M/E/F Interfacing Guide (02109-90006) has the schematic for the 12620A. There is a diagnostic for the 12936A in the 24396A set. The two cards do not behave the same. The 12620A card has the normal control and flag logic and reacts to the standard I/O instructions. The 12936A has the flag flip-flop clear with CLF, but STF was ignored. Instead, the flag set was on OTA/B. RTE (RTIOC) does STC on $CIC entry. On return, CLC and STF are done. Because POPIO clears control and flag on the 12936A, and because STF is ignored on that card, only the control flip-flop is affected; the flag is always clear. On entry, the STC drops PRL to higher select codes, and on exit, the CLC restores PRL. No interrupt is generated. The 12620A card responds to all of the I/O instructions. POPIO sets the flag, so the STC on entry denies PRL to higher select codes, but also causes an interrupt when the interrupt system is turned back on. However, the trap cell is initialized to a NOP, so no transfer occurs. On exit, the CLC asserts PRL. So, even though the cards are different electrically, the net result is the same, no matter which one is used. ------------------------------------------------ 13181B/13183B Tape Drive Interface (7970B/7970E) ------------------------------------------------ Timing information for use in the SIMH simulator: Hardware timing at 45 IPS 13181 diag | 13183 diag (based on 1580 instr/msec) instr msec SCP msec | instr msec SCP msec ----------------------------- | ---------------------------- - BOT start delay : btime = 161512 102.22 184 104-207 | 252800 160.00 288 60-207 - motion cmd start delay : ctime = 14044 8.89 16 8-10 | 17556 11.11 20 11-13 - GAP traversal time : gtime = 175553 111.11 200 104-130 | 105333 66.67 120 60-75 - IRG traversal time : itime = 24885 15.75 - 14-17 | 27387 17.33 - 15-18 - rewind initiation time : rtime = 878 0.56 1 1 | 878 0.56 1 1 - data xfer time / word : xtime = 88 55.56us - 6-11 | 44 27.78us - 0-4 NOTE: The 13181-60001 Rev. 1629 tape diagnostic fails test 17B subtest 6 with "E116 BYTE TIME SHORT" if the correct data transfer time is used for the 13181A interface. Rev. 2040 of the tape diagnostic fixes this problem and passes with the correct data transfer time. The Rev. 2040 diagnostic uses these constants (minimum time in milliseconds; maximum is 125% of minimum). The times depend on speed (these are for 45 IPS): DEC 1 13181 REW | DEC 1 13183 REW DEC 8 " WRITE | DEC 11 " WRITE DEC 10 " CLEAR | DEC 10 " CLEAR DEC 104 " GAP | DEC 60 " GAP DEC 14 " IRG | DEC 15 " IRG DEC 14 " MIN BYTE | DEC 11 " MIN BYTE DEC 19 " MAX BYTE | DEC 15 " MAX BYTE Test 16 (octal) uses RFF (read forward until file mark) command, 223B. The 13183B interface doesn't use IOBO4, so this is seen as command 203B, FSF (forward space file). Looks like test 16 will fail on real hardware, because FSF doesn't transfer data. ------------------------------------------- 12845A/12845B Line Printer Interface (2607) ------------------------------------------- For a DMA transfer, 12845A needs first character sent by OTA. 12845B can transfer entire buffer via DMA. 2607 provides three status bits: bit 15 -- printer ready (online) bit 14 -- paper out bit 0 -- printer idle Existing LPT status: 040000 -- if not attached 100000 -- if attached and active 100001 -- if attached and not active Set interface as 12845B for diag. The diagnostic looks for these status responses (after RUN from halt): Status Message Wanted Command to use -------------------------------------------- ------ -------------------- H040 PWR OFF LP,PRESS RUN 140001 SET LPT POWEROFF H041 PWR ON LP,READY LP,PRESS RUN 100001 SET LPT POWERON H042 PRINT SW OFF,PRESS RUN 000000 SET LPT OFFLINE H043 PRINT SW ON,PRESS RUN 100001 SET LPT ONLINE H044 OPEN PLATEN,PRESS RUN 000000 SET LPT OFFLINE H045 CLOSE PLATEN,PRESS RUN [--] SET LPT ONLINE H046 REMOVE PAPER FROM LP,PRESS RUN 000000 DETACH LPT H047 RESTORE PAPER IN LP, READY LP,PRESS RUN [--] ATTACH LPT ------------------------------------ 12653A Line Printer Interface (2767) ------------------------------------ Diagnostic expected maximum timing (STC to interrupt) -- operation is to accumulate a delay incurred before the NEXT print operation completes, e.g., a CR is acknowledged immediately if printer is idle, but next print action following CR will wait until previous print action completes before acknowledging. normal char -- before end of 20-char zone: this wait = 1 ms, next wait unchanged at end of 20-char zone: this wait = accum., next wait = 40 ms CR -- this wait = accum., next wait = 40 ms LF -- if at perf skip: this wait = accum + 90 ms, next wait = 170 ms not at perf skip: this wait = accum, next wait = 80 ms FF -- this wait = accum + 780 ms, next wait = 40 ms + 13 ms * lines to BOF hardware timing: ctime -- character xfer time = 0.001 ms = 2 ptime -- zone printing time = 40 ms = 63200 (35 ms = 55300) stime -- paper slew time = 13 ms = 20540 (11 ms = 17380) (Note that printer acks before print motion stopped, allowing continuous slew. The diagnostic apparently looks for this, so the actual times have to be trimmed a bit to satisfy the diagnostic.) ----------------------------- 12920A 16-Channel Multiplexer ----------------------------- The mux has three cards: two data channels and one control channel. They are installed in the card cage in this order: [sc+n] control card "MUXM" ("muxc_dev") [sc+1] upper data card "MUX" ("muxu_dev") [sc] lower data card "MUXL" ("muxl_dev") Note that the manual states, "The control PCA does not have to be adjacent." Differences between A and B Versions ------------------------------------ - Master reset (CLC 0): [A] 100 msec of CLC 0s must be executed [B] only one CLC 0 is needed SEEKING bit is set while interface resets and clears when done - Break flag: [A] Set at xmit start bit, reset when a 1 is seen [B] As above, but flag is buffered, so value sets at end of xmit Test Cable ---------- The diagnostic uses a test cable, 30062-60003. Documentation on page 4-14 of the 12920 A/B Asynchronous Multiplexer Interface Diagnostic Reference Manual (12920-90009, Apr-1978) shows that the cable connects C1 and C2 of one port to S1 and S2 of another. However, the diagnostic sources, 12920-19001 (data) and 12920-19004 (control), clearly indicate that both the control/status lines and the transmit/receive lines must be symmetrically connected. The operative statements are lines 1131-1135 and 1692-1695 in the data diagnostic, and lines 1314-1319 in control diagnostic. Both sections reverse the transmit and receive port numbers entered by the operator and then reexecute the tests. Therefore, the test cable must have this wiring: Connector A Connector B Pin Mux Designation Pin Mux Designation --- --------------- --- --------------- 2 Data In 3 Data Out 3 Data Out 2 Data In 4 Status 2 8 Command 2 6 Command 1 20 Status 1 7 Common Return 7 Common Return 8 Command 2 4 Status 2 20 Status 1 6 Command 1 ---------------------------------- 21MX E-Series Special Instructions ---------------------------------- The E-series adds three undocumented instructions to the base set: TIMER, EXECUTE, and DIAG. These are listed in the ERD in paragraph 5-7 on page IA 5-5. The instruction codes are: TIMER - 100060 EXECUTE - 100120 DIAG - 100000 The functions are described there as follows: * TIMER increments the B register until B is either 0, or a halt or an interrupt occurs. TIMER increments B once every 630 ns. independent of any other factors (except DCPC activity). Usage: LDB TIMER [B is now zero] * EXECUTE executes the instruction pointed to by the next word. Control is passed back to the instruction following, unless the executed instruction was a branch or a multiple word instruction. In the latter case, the instruction will not work correctly, as the DEFs for a multiword instruction are fetched from memory after the execute DEF, instead of after the target opcode. Usage: EXECUTE DEF [return here] * DIAG runs microcoded self-tests that are destructive to memory. If executed with the CPU running, it is a NOP. To run, INSTR STEP must be used. There are three microcoded tests; #1 is a CPU test, #2 is a 32K memory test, and #3 is a full memory test (if DMS is present). DIAG runs test #1 and #3. E-Series Decoding and Execution ------------------------------- The three instructions decode as part of the EAU set. The jump micro-orders affected are: TIMER - 100060 (10 000 000 0011 0000) -- JTAB = 200, J74 = 3 EXECUTE - 100120 (10 000 000 0101 0000) -- JTAB = 200, J74 = 5 DIAG - 100000 (10 000 000 0000 0000) -- JTAB = 200, J74 = 0 JTAB 200 transfers to JTBL1000 [00113]. That contains a J74 to EM1000 [00240]. The latter causes the following transfers: TIMER - [00243] JMP TIMER EXECUTE - [00245] JSB RETNFP DIAG - [00240] JMP STFL DIAG The code at label TIMER does an interrupt test, an increment, and a loop if non-zero. Label DIAG does a test for HALT mode and an return if not (NOP). Otherwise, it runs test #1 and #3, then returns to the front panel HALT code. EXECUTE is odd. Here is the microcode path: 00000 FETCH READ FTCH PASS IRCM TAB 00001 JTAB INC PNM P 00113 JTBL1000 JMP J74 EM1000 00246 FPDIAG JSB RETNFP 01422 RETNFP READ RTN 00247 READ RTN 00000 FETCH ... Assume that the following code is present in memory: 00100 100120 EXECUTE 00101 000200 DEF CLEAR 00102 102077 HLT 77B 00200 002400 CLEAR CLA The control processor executes this as follows (from the pipeline read, at entry, T = 100120 and P = 00101): 00000 -- IR := 100120, M := junk, READ of MRG operand 00001 -- M := 00101, P := 00102 00113 00246 -- TOS := 00247 01422 -- READ of 00101 (00200) 00247 -- READ of 00101 (00200) 00000 -- IR := 000200, M := junk, READ At this point, we "execute" the "DEF CLEAR"! So I don't see how this instruction is supposed to work. M-Series Decoding and Execution ------------------------------- The three instructions decode as part of the EAU set. The jump micro-orders affected are: TIMER - 100060 (10 000 000 00110000) -- JTAB = 200 EXECUTE - 100120 (10 000 000 01010000) -- JTAB = 200 DIAG - 100000 (10 000 000 00000000) -- JTAB = 200 JTAB 200 transfers to EAU [00102]. That contains a JEAU to EAUTABLE [00330]. The JEAU micro-order maps IR bits 11, 9-7 and 5-4 to bits 2-0 of the microcode jump address. The map is detailed on page IC-84 of the ERD. The inputs to the JEAU mapper and the resulting map outputs are: JEAU IN: v vv v vv TIMER - 100060 (10 000 000 00110000) -- JEAU IN = 000011, OUT = 111 EXECUTE - 100120 (10 000 000 01010000) -- JEAU IN = 000001, OUT = 101 DIAG - 100000 (10 000 000 00000000) -- JEAU IN = 000000, OUT = 100 Therefore, the JMP JEAU causes the following transfers: TIMER - [00337] JMP MPY EXECUTE - [00335] JMP ASL DIAG - [00334] JMP RRL So, on an M-series, TIMER decodes as MPY, EXECUTE decodes as ASL, and DIAG decodes as RRL. That implies that the instruction after TIMER will be interpreted as the address of the multiplier, and the address after EXECUTE will be interpreted as the next instruction to execute after the ASL. ----------------------------------------- RTE Reconfiguration Console Determination ----------------------------------------- During a reconfiguration ("slow") boot, RTE automatically determines whether the new console should use DVR00 or DVR05. It does this by executing the following instruction sequence directed at the console I/O card: LDB .5 PRESUME DVR05 LDA =B150077 12966 MASTER RESET WORD CLF SC OTA SC SFS SC CLB USE DVR00 ... So the selection depends on the 12966 card setting the device flag in response to a "master reset" command, whereas the 12880/12531 cards will not. ------------------------------------------------- RTE-6/VM Microcode Bypass for E/F-Series Machines ------------------------------------------------- During bootup, RTE-6/VM checks the type of the processor. If an E- or F-Series machine is detected, the OS and VMA microcode self-test instructions are executed. If these fail, as they will if the microcode is not present, a HLT 21B occurs. The test is in OS module SCHD6 (92084-1X478 REV.5000) at entry point $NOMI: * SEE IF M OR E/F CCB OCT 100060 * NOP BELOW TO RUN WITHOUT MICROCODE $NOMI SZB SKIP IF E OR F JMP TOIT0 NO OS/VMA MICROCODE IF M cca set a=-1 if os microcode OCT 105355 YES, IF IT PASSES SELF-TEST jmp badvm did'nt pass self test give HLT 21 STX $MCRO =0 IF NO OS MICROCODE, ELSE "REV.CODE" * NOW DO VMA SELFTEST & PROCEED ONLY IF IT PASSES CLA CAY Y= 0 FOR VMA SELFTEST ENTRY OCT 105242 JMP BADVM IF NOT THERE YOU LOSE Opcode 100060 is TIMER on an E/F-Series. On an M-Series, the instruction decodes as a MPY and so returns to P+2. So if the return is to P+1 with B = 0, the machine is an E- or F-Series; otherwise, it's an M-Series. As the comment indicates, the test may be bypassed to allow RTE-6/VM to run on an E/F-Series without OS/VMA microcode. To change the SZB to a NOP in the disc image, search for the first occurrence of this pattern (n.b., SIMH images will be byte-reversed): 0F00 (007400 CCB) 8030 (100060 TIMER) 0C02 (006002 SZB) ...and change the 0C02 to 0000. ------------------------------------------ RTE-6/VM Offline Restoration from Mag Tape ------------------------------------------- Attempting to load the RTE offline restoration program, !BCKOF, via a 7970E on an M-Series fails with a HLT 00B. This occurs for the same reason that the 7970 boot loader ROM fails, i.e., a timing error. The offline restoration is hosted on an RTE-IVE system. Because the 7970 boot loader ROM is used to start the system, RTE is split into a number of separate tape files. This is because the DMS maps must be altered between files to load the various parts into the correct physical memory locations. The boot loader ROM is used to load the first part of the system into the first 32K of physical memory. This includes the RTE-IVE configurator (92068-18068), which receives control. The configurator sets up DMS and loads the remainder of the system, one segment at a time. Unfortunately, the configurator essentially uses a copy of the ROM code to load from tape (at label LOAD4), and the ROM data transfer loop is not fast enough on an M-Series with a 45 IPS 7970E drive. As a result, timing errors occur, leading to the halt. A modified 12992D boot loader ROM has been written that is fast enough, and this code could be used to create a modified $CNFG program. The offline restoration program (RTE-IVE system) would have to be regenerated to incorporate the modified code. The answer file used is 92084-17167, and the system creation procedure is 92084-17182. For reasons not clear, the converted RTE-IVE system file, which contains subfiles, is split into 14 separate files for distribution. The command file that does this is 92084-17180. NOTE: The RTE-IVE $CNFG determines the device from which to load the system by examining the first two words of the IBL loader space and comparing that to known code sequences. For example, the mag tape loader ROM must begin with LIB 1 and SLB,RSS for the mag tape to be used as the load device. Also, the select code of the load device is determined by searching the first 32 words for an I/O instruction. -------------------------------------------- 7970B/E Magnetic Tape Drive Ordering Options -------------------------------------------- 7970B 9-track, NRZI-encoded, 800 bpi, read-after-write, 45 ips: - opt 001: 37.5 ips - opt 002: 25 ips - opt 010: add-on slave drive 45 ips - opt 011: add-on slave drive 37.5 ips - opt 012: add-on slave drive 25 ips 7970E 9-track, phase-encoded, 1600 bpi, read-after-write, 45 ips: - opt 001: 37.5 ips - opt 002: 25 ips - opt 005: add-on master drive 45 ips - opt 006: add-on master drive 37.5 ips - opt 007: add-on master drive 25 ips - opt 010: add-on slave drive 45 ips - opt 011: add-on slave drive 37.5 ips - opt 012: add-on slave drive 25 ips -------------------------------- RTE OS Boot Extension Signatures -------------------------------- The signatures are contained in the first four words at the start of each disc image. In hex representation, they are: - RTE-IVB ICD : 676D 06C0 776B 0B40 (LDA HHIGH ; CMA,CCE ; STA HRCNT ; ERB) - RTE-6/VM ICD : 676D 06C0 776B 0B40 (LDA HHIGH ; CMA,CCE ; STA HRCNT ; ERB) - RTE-6/VM CS/80: 6720 0403 8541 7720 (LDA TSWC ; SZA,RSS ; LIA 1 ; STA TSWC) - MPE MAC, CS/80: 5359 5354 454D 2044 ("SYSTEM D") These represent the start of the boot extension for RTE and the start of the disc label for MPE. The boot extension machine instructions are: RTE-IVB ICD ----------- 62000 LDA EQU 062000B 72000 STA EQU 072000B 01200 O0 EQU HSTRT-1400B 02600 063555 HSTRT ABS LDA+HHIGH-O0 (word 1) 02601 003300 CMA,CCE (word 2) 02602 073553 ABS STA+HRCNT-O0 (word 3) 02603 005500 ERB (word 4) 02753 000000 HRCNT NOP 02755 077377 NW#DS OCT 77377 02755 HHIGH EQU NW#DS RTE-6/VM ICD ------------ 062000 LDA EQU 062000B 072000 STA EQU 072000B 000000R O0 EQU HSTRT-1400B 01400 063555 HSTRT ABS LDA+HHIGH-O0 (word 1) 01401 003300 CMA,CCE (word 2) 01402 073553 ABS STA+HRCNT-O0 (word 3) 01403 005500 ERB (word 4) 01553 000000 HRCNT NOP 01555 077377 NW#DS OCT 77377 001555R HHIGH EQU NW#DS RTE-6/VM CS/80 -------------- 001000R O EQU *-1400B 02400 063440 TSTRT ABS LDA-O+TSWC (word 1) 02401 002003 SZA,RSS (word 2) 02402 102501 LIA 1 (word 3) 02403 073440 ABS STA-O+TSWC (word 4) 02440 000000 TSWC DEC 0 And the disc label is: MPE MAC and CS/80 ----------------- 00000 051531 LABEL ASC 6,SYSTEM DISC (word 1) 00001 051524 (word 2) 00002 042515 (word 3) 00003 020104 (word 4) 00004 044523 00005 041440 ---------------------------------------- CS/80 Compatable Diagnostic Configurator ---------------------------------------- Diagnostic input devices: - 2748/2758/2737 paper tape reader - 7970 magnetic tape drive - 7900/7901 disc drive - 7905/7920 disc drive (MAC) - 2644/2645 minicartridge tape drive - CS80 cartridge tape or disc - 7974/7978 magnetic tape drive 24296-80001 1533 01/05 A01343 00101 00004 DIAGNO - provides 2748/2758/2737, 7970, 7900/7901 24296-80001 1627 01/01 A01342 00101 00004 DIAGNO - adds 7905/7920, 2644/2645 24296-80001 2522 01/01 A51977 00110 00004 &DGCNF - adds CS80 93566-18021 2546 01/01 A64247 00112 00004 &DGCNF - adds 7974/7978 02100-90157 June 1985 describes CS/80 disc/tape creation in Appendix C. Uses CS80BD program that is on Keymaster: 24396-16001 2522 01/01 A51978 00110 00005 %C80BD 24396-16002 2522 01/01 A51969 00110 00007 !C80BX 24396-16002 2903 01/01 A73351 00115 00007 !C80BX 24396-17001 2522 01/01 A73352 00115 00004 #C80BD 24396-17002 2522 01/01 A51971 00110 00004 *C80BD 24396-17999 2522 01/01 A51972 00110 00003 A24396 24396-18001 2522 01/01 A51979 00110 00004 &C80BD 24396-18002 2522 01/01 A51973 00110 00004 &C80BX Absolute binary diagnostic programs are converted to memory images for writing to CS/80 media. The CS/80 boot extension is written to block 0. It is loaded by the CS/80 boot loader ROM, and in turn it loads the CS/80 diagnostic configurator. The configurator then loads diagnostics as usual. CS80BD can be run under simulation to process the files and write a type 1 file containing the processed output. Then it would have to be run on a real system connected to HPDrive emulating a 7914 + CTD in order to write the CTD (no CS/80 support in SIMH yet). Would have to gen a CS/80 system with CTD support to run on the M-Series. Result would be a CTD image that could be used with HPDrive (as a 9144) to load diagnostics into CPUs with minimum hardware: - 16K RAM - DCPC - 12992J loader ROM - 12821A DI card - 12531/12880/12966 terminal card A wholly different option would be to write a PC program that emulated the minicartridge drives on a 264x terminal (QCTerm and Reflection do not emulate these). Then one could use diagnostics in minicartridge format (e.g., SIMH mag tape format) with the PC connected via a serial port to a BACI. Then the hardware requirements would be: - 16K RAM - 12992C loader ROM - 12966 BACI Of course, I do not have a BACI (although I do have a 12992C ROM), so this is of limited interest to me. But it shouldn't be that hard; the escape sequence support should be pretty minimal: - ESC e fast binary read until file mark (boot ROM) - ESC & p 0 C to rewind - ESC & p 2 C to space forward one file - ESC & p 2 R to read the next record One point: the diagnostic configurator CTD driver uses DCPC, as do the disc and tape drivers. The minicartridge driver does not. So a bad DCPC card would not prevent loading with minicartridges. This may be a notable advantage. ------------------ RS-232 Connections ------------------ The RS-232 standard defines two wiring conventions: Data Terminal Equipment (DCE) and Data Communication Equipment (DCE). Both employ a DB-25 connector. The signals are defined from the point of view of DTE, which transmits data on pin 2 and receives data on pin 3. DCE transmits on pin 3 and receives on pin 2. HP cables and systems are wired as follows: Convention Connector Connection ---------- --------- ---------------------------------- DCE DB-25F HP 12828A Multiplexer Panel DCE DB-25F HP 12880-60002 Terminal Cable DCE DB-25M HP 12880-60003 Terminal Cable DTE DB-25M HP 13232A 264x Terminal Cable DTE DB-25F HP 13232C 264x Terminal Cable DTE DB-25F HP 64000 "To Modem" Connector DCE DB-25F HP 64000 "To Peripheral" Connector DCE DB-25F HP 3000 TIC Modem Connector DCE DE-9F HP 3000 TIC Terminal Connector DCE DB-25F HP 3000 ATP Terminal Cable DTE DE-25M PC Serial Cable -------------------------------------- Fixed-Head and Moving-Head Disc Drives -------------------------------------- The simulator currently supports these disc drives: Dev Interface Drive Loader Units Cyls Heads Secs Words Bytes --- --------- --------- ------ ----- ---- ----- ---- ----- ----------- DA 12821A 7906H 12992H 4 411 4 48 128 20,201,472 12821A 7920H 12992H 4 823 5 48 128 50,565,120 12821A 7925H 12992H 4 823 9 64 128 121,356,288 DP 12557A 2870A BMDL 4 203 4 12 128 2,494,464 13210A 7900A 12992F 4 203 4 24 128 4,988,928 13210A 7901A 12992F 4 203 2 24 128 2,494,464 DQ 12565A 2883A 12992A 2 203 20 23 128 23,905,280 DR 12606B 2770A BBDL 1 - 32 90 64 368,640 12606B 2771A BBDL 1 - 64 90 64 737,280 12606B 2771A-001 BBDL 1 - 128 90 64 1,474,560 12610B 2773A BBDL 1 - 192 32 64 786,432 12610B 2773A-001 BBDL 1 - 256 32 64 1,048,576 12610B 2773A-002 BBDL 1 - 320 32 64 1,310,720 12610B 2774A BBDL 1 - 384 32 64 1,572,864 12610B 2774A-001 BBDL 1 - 448 32 64 1,835,008 12610B 2774A-002 BBDL 1 - 512 32 64 2,097,152 12610B 2775A BBDL 1 - 768 32 64 3,145,728 -- 12610C 2766A BBDL 1 - 128 32 64 524,288 -- 12610C 2766A-002 BBDL 1 - 256 32 64 1,048,576 -- 12610C 2766A-003 BBDL 1 - 384 32 64 1,572,864 -- 12610C 2766A-004 BBDL 1 - 512 32 64 2,097,152 DS 13175D 7905A 12992B 8 411 3 48 128 15,151,104 13175D 7906A 12992B 8 411 4 48 128 20,201,472 13175D 7920A 12992B 8 823 5 48 128 50,565,120 13175D 7925A 12992B 8 823 9 64 128 121,356,288 The 2884A is the order number for the second 2883A drive. The 2770A and 2771A are fixed-head disc drives. The 2773A, 2774A, and 2775A are fixed-head drum drives. The 2770A may be expanded from 32 to 64 heads, and the 2771A may be expanded from 64 to 128 heads. An expanded 2770A (2770A-001) is identical to an unexpanded 2771A. The 2766A fixed-head disc drive replaced the 2770A and 2771A. The base 2766A has 32 heads and may be expanded to 64 (-002), 96 (-003), or 128 (-004) heads. These drives appear to be accessed as 32/64/96/128 "system tracks" of 128 sectors per track (each "system track" is equivalent to four hardware tracks). These drives are not currently simulated. The 2773A may be expanded from 48 heads to 64 or 96 heads. The 2774A may be expanded from 96 to 128 heads. An maximally expanded 2773A is equivalent to an unexpanded 2774A. ------------------ 7900A First Status ------------------ On page 3-5, the 13210A Disc Drive Interface Kit Operating and Service Manual (13210-90003 November 1974) says: "First status (bit 14) is set when the selected disc drive goes from not-ready to ready status. First status is cleared with the execution of a Status Check command." Consequently, the DP device sets first status when the unit is attached and clears it when a Status Check is done. This behavior is present from at least version 3.2-0 onward. However, when the moving-head version of RTE ("RTE-I MH") was resurrected, the paper tape bootstrap was observed to halt with a "disc error" indication. The bootstrap code does a Seek followed by a Read. After Read completion, the code ends with: STATS LIA DC GET THE STATUS FROM THE DATA CHANNEL RBL,CLE,ERB REMOVE SIGN BIT FROM THE TRANSFER ADDRESS SLA,RSS ANY ERRORS? JMP B,I NO. GO TO THE BOOT EXTENSION HLT 11B HALT FOR THE ERROR JMP RETRY RETRY THE SEEK AND READ On examination, the A register contained 040001, which is First Status + Any Error. The moving-head paper tape bootstrap for RTE-II (92001-18016) is almost the same as the RTE-I bootstrap. However, the ending status check is different: DSKDQ LIA DC GET THE STATUS FROM THE DATA CHANNEL RBL,CLE,ERB REMOVE SIGN BIT FROM ADDRESS SLA,RSS ANY ERRORS? JMP B,I NO. GO TO THE EXTENSION * CPA JSTLD-ADCON IS THIS THE FIRST TIME? RSS YES, TRY AGAIN. HLT 11B NO HALT JMS#A JMP S#ART-ADCON RETRY ON RESTART * JSTLD OCT 040001 So it checks explicitly for the expected first status and does an automatic retry. The 12992A boot loader ROM and the 7900 BMDL also clear first status explicitly. The boot ROM (12992-18022) does this: LOOP OTA CC DO 7900 STATUS TO STC CC,C CLEAR FIRST SEEK SFS DC STATUS JMP *-1 INA GET NEXT DRIVE CPA D7 ALL CLEARED? RSS YES JMP LOOP Entry is with the A-register set to the subchannel number (0-3). By looping until A = 7, all four possible drives are addressed. The BMDL (from 24353-18003, the "loader loader") does: SEEKC OCT 30000 (= IOR A) LDB MASK OTB CC ISSUE READ COMMAND STC CC,C START READ TO CLEAR 1ST STATUS LDA SEEKC OTA DC ISSUE CYCLINDER ADDR (0) STC DC,C TELL CTRL. CYL. ADDRS IS LOADED OTA CC ABORT READ, SEND SEEK COMND STC CC,C START SEEK Note that a Read is expected to clear the First Status bit, although the BMDL doesn't actually check the disc status. An initial assumption was that the earliest 7900s did not return First Status and that later ones did. The 7900A was introduced in the May 1972 HP Journal, and the earliest service manual is dated August 1974. However, nothing in the 7900 Service Manual backdating information suggested this. Moreover, the Model 7900A/7901A Disc Drives Interface Guide (5952-5446 Jul-1973) describes the First Status bit. The situation remained unresolved until a 2000F system was generated that included the 27xx drum memory with the 7900. In this configuration, the system is bootstrapped from the drum, and the 7900 is initialized as part of the system startup. This failed with a HLT 2, which the operator's manual documents as, "Erroneous system transfer has occurred." The source of the version of the 7900 loader that incorporates the drum is not available. However, the source for the loader without the drum shows that this sequence leads to the halt: * * STATUS * STC BSDAT,C SET UP DATA CHANNEL LDA BSTUS GET STATUS COMMAND JSB BSCMD JSB BSWTD WAIT FOR WORD LIA BSDAT LOAD STATUS WORD AND BSBST MASK OFF BIT 15 SZA,RSS SKIP IF BAD STATUS JMP FBSTA,I STATUS OK. JUMP OVER SST BSERR EQU * HLT 2 RECOVERABLE HALT JMP BSLD Once again, the A-register content is 040001, indicating First Status + Any Error, and there is no special handling for First Status. Preceding the Status Check call is a Seek and a Read. So this code also implies that the First Status return is not expected here. The fact that two different programs for two different product groups expect First Status to be clear suggests that either Seek or Read will clear it, even though this is not the documented behavior. The BMDL also suggests that Read will clear it. Therefore, the schematics for the 7900A disc drive and the 13210A disc interface were reexamined closely. Page 5-43 ("Drive Control Assembly A9 Schematic Diagram") of the 7900A Disc Drive Operating and Service Manual (07900-90002 February 1975) shows that the First Status flip-flop is set on the low-to-high transition of the Drive Ready signal. It is cleared on the low-to-high transition of the ~Clear Status signal. Assertion of Clear Status also clears the Attention flip-flop, as does assertion of the Set Cylinder signal that is asserted to the drive for a Seek command. Page 5-39 ("Input/Output Multiplex Assembly A7 Schematic Diagram") shows that Clear Status is asserted when Drive Control and Controller Outbus 7 are asserted. These signals are sent from the interface, which is controlled by a ROM state machine. Page 5-5 ("Disc Interface 1 PCA Schematic") of the 13210A Disc Drive Interface Kit Operating and Service Manual (13210-90003 November 1974) shows that the Control and Outbus 7 signals are asserted together in controller state 0001. The content of the state ROM is not given. However, the command flowcharts on pages 4-9 through 4-13 show that ROM State 0001 is entered for the Status Check command (4-13), as well as for the Read, Write, Check Data, and Initialize commands (4-11), but not for the Seek and Address Record commands (4-9). There is no flowchart for the Refine Sector command, so entry into State 0001 is unknown. This shows that, contrary to the documentation, First Status is cleared on a Read, Write, Check Data, or Initialize command, as well as on a Status Check command, and not only on the latter. This explains why the RTE-I bootstrap and the 2000F (drum version) disc initialization routine expects First Status to be clear even though no Status Check command has occurred since the heads loaded. Therefore, the DP device has been modified to clear First Status (as well as Attention) at the start of the Read, Write, Check Data, Initialize, Refine Sector, and Status Check commands. This permits the RTE-I paper tape bootstrap and 2000F startup routines to succeed without halting. --- 24353-18003 (loader loader) says 7900 BMDL also boots 2870. BMDL disc bootstrap starts at x7750. Code is: * DISC BOOTSTRAP -- LOADS DISC PRE-BOOT PROCESSOR FROM * TRACK 0, SECTOR 0, DRIVE 0 * HEAD # INPUT FROM SWITCH REG * * STARTING ADDRESS - X7750B * *** "PRESET" MUST BE PRESSED * SEEKC OCT 30000 (= IOR A) LDB MASK LDR23 EQU * OTB CC ISSUE READ COMMAND LDR24 EQU * STC CC,C START READ TO CLEAR 1ST STATUS <== !!!!! LDA SEEKC LDR25 EQU * OTA DC ISSUE CYCLINDER ADDR (0) LDR26 EQU * STC DC,C TELL CTRL. CYL. ADDRS IS LOADED LDR27 EQU * OTA CC ABORT READ, SEND SEEK COMND LDR28 EQU * STC CC,C START SEEK LDA DMACW OTA 6 ISSUE DMA CONTROL WORD LDA ADDR1 OTA 2 ISSUE START MEM ADDR (2011B) LDR29 EQU * STC DC,C TELL CNTR. HEAD/SECT LOADED STC 2 SET FOR WORD COUNT OTA 2 ISSUE WORD COUNT (HUGE) LDR2A EQU * OTB CC ISSUE READ COMND LDR2B EQU * STC DC,C PREVENT SPURIOUS DMA TRANS. STC 6,C START DMA LDR2C EQU * STC CC,C START DISK READING LDR2D EQU * SFS CC WAIT FOR DISK TRANS (6144 WORDS) JMP *-1 JSB ADDR2,I DONE; JUMP INTO MEM (2055B,I) The disc-resident bootstrap (CHS 0/0/0) starts at label START and does handle being loaded either from paper tape or BMDL (2011/2055). It does this: ALF,ALF MULTIPLY BY RAR 128 CMA,INA AND SUBTRACT FROM SLOAD ABS ADA-O+#WDTK NUMBER OF WORDS PER TRACK ABS STA-O+P#WDS SET POSITIVE # WORDS CMA,INA AND ABS STA-O+N#WDS NEGATIVE # WORDS THIS TRACK >> RSS SKIP OVER BBDL ADDRESS DEF >> ABS 2000B+BENT-OO DEFINE ADDRESS OF BENT ABS LDA-O+RECNT GET NUMBER LEFT SSA,RSS IF POSITIVE ABS JMP-O+PLOAD+I+I DONE - SO EXIT ABS ADA-O+P#WDS ELSE SET TO READ ABS STA-O+RECNT SAVE REMANING COUNT SSA NEXT TRACK CLA USE MIN. OF NUMBER ON TRACK OR ABS ADA-O+N#WDS NUMBER LEFT STC 2 SET DMA FOR WORD COUNT ...whereas the RTE-I disc-resident bootstrap does this: ALF,ALF RAR CMA,INA ADA C 1640 STA C 1636 CMA,INA STA C 1637 >> >> LDA C 1631 SSA,RSS JMP C 1506,I ADA C 1636 STA C 1631 SSA CLA ADA C 1637 STC 2 So the RTE-I bootstrap is not BMDL-compatible and must be loaded via the paper tape bootstrap. The RTE-I paper tape boostrap does: 0: 040001 1: 077500 2: NOP 3: NOP 4: NOP 5: NOP 6: NOP 7: NOP 10: NOP 11: NOP 12: NOP 13: NOP 14: CLC 0,C 15: LDA 77 =B000000 16: OTA 22 17: STC 22,C SET CYL = 0 20: LDA 74 =B030000 21: OTA 23 22: STC 23,C SEEK 23: SFS 22 WAIT FOR CYL ACCEPT 24: JMP 23 25: LDA 73 =B001000 26: OTA 22 27: STC 22,C SET HEAD = 2 SECTOR = 0 30: LDA 76 =B120022 31: OTA 6 SET CW1 = STC, CLC, SC 22 32: CLC 2 33: LDB 71 =B177500 34: OTB 2 SET CW2 = INBOUND, ADDRESS 077500 35: LDA 70 =B177600 36: STC 2 37: OTA 2 SET CW3 = WORD COUNT 128 40: SFS 23 WAIT FOR SEEK COMPLETION 41: JMP 40 42: LDA 75 =B020000 43: CLC 23 44: OTA 23 45: STC 22,C START DATA CHANNEL 46: STC 6,C START DMA 47: STC 23,C READ 50: SFS 23 WAIT FOR READ COMPLETION 51: JMP 50 52: STF 6 STOP DMA 53: STC 22,C ENABLE DATA CHANNEL 54: LDA 72 =B000000 55: CLC 23 56: OTA 23 57: STC 23,C STATUS CHECK 60: SFS 22 WAIT FOR STATUS RETURN 61: JMP 60 62: LIA 22 63: RBL,CLE,ERB 64: SLA,RSS 65: JMP 1,I 66: HLT 11 67: JMP 14 70: 177600 71: 177500 72: 000000 73: 001000 74: 030000 75: 020000 76: 120022 77: 000000 100: JMP 14 <== entry point ----------------------------- 12566B Microcircuit Interface ----------------------------- The 12566B Microcircuit Interface card is used to attach several peripherals to the HP 1000: - 12653A Line Printer Interface (2767) - 12732A Flexible Disc Subsystem (2 each) - 12875A Processor Interconnect Kit (2 each) In addition, it is required by several diagnostics as an adjunct device when testing their primary devices, both as a source of interrupts and as a data loopback device. The card has nine jumpers, labeled W1-W9, that affect the electrical configuration, as follows: W1 - Device Command Signal ----------------------------------------------- A - Ground true asserted with STC B - Positive true asserted with STC C - Pulsed ground true asserted for T6 and T2 W2 - Device Command Flip-Flop -------------------------------------------- A - Clears on positive edge of Device Flag B - Clears on negative edge of Device Flag C - Clears on ENF (T2) W3 - Device Flag Signal -------------------------------------------------------- A - Sets Flag Buffer and strobes data on positive edge B - Sets Flag Buffer and strobes data on negative edge W4 - Output Data Register ------------------------------------------------ A - Output data is gated by the data flip-flop B - Output data is continuously available W5 - Input Data Register bits 0-3 W6 - Input Data Register bits 4-7 W7 - Input Data Register bits 8-11 W8 - Input Data Register bits 12-15 ------------------------------------------ IN - Register is latched by Device Flag OUT - Register is transparent W9 - Device Command Flip-Flop ------------------------------------------ A - Cleared by CLC, CRS, and Device Flag B - Cleared by CRS and Device Flag For normal device use, the card must be jumpered as follows: W1 W2 W3 W4 W5 W6 W7 W8 W9 Device --- --- --- --- --- --- --- --- --- ------------------------------------------ A B A B OUT IN IN IN A 12566B-004 Line Printer Interface (9866) B A B B OUT IN IN OUT A 12653A Line Printer Interface (2767) A B B B IN IN IN OUT B 12732A Flexible Disc Subsystem (Control) A A B B IN IN IN IN B 12732A Flexible Disc Subsystem (Data) (must change W2 to B for GP Register Diag) A B B B IN IN IN IN A 12875A Processor Interconnect Kit For diagnostic use, the jumper configurations required are: W1 W2 W3 W4 W5 W6 W7 W8 W9 DSN Diagnostic --- --- --- --- --- --- --- --- --- ------ --------------------------------- C B B B IN IN IN IN A 143300 General Purpose Register C B B B IN IN IN IN A 141203 I/O Instruction Group C B B B IN IN IN IN A 102103 Memory Expansion Unit C B B B IN IN IN IN A 101220 DMA/DCPC for 2100/1000 B A A B IN IN IN IN A -- DMA for 2100 (24195) B A A B IN IN IN IN A 101105 DMA for 2114/2115/2116 (24322) B C A A/B IN IN IN IN A 101105 DMA for 2114/2115/2116 (24322) B C B B IN IN IN IN A -- DMA for 2115/2116 (24185) (not relevant; interrupt only) 101112 Extended Instruction Group (not relevant; interrupt only) 101213 M/E-Series Fast FORTRAN Package 1 (not relevant; interrupt only) 101115 M/E-Series Fast FORTRAN Package 2 (not relevant; interrupt only) 101121 F-Series FPP-SIS-FFP (not relevant; interrupt only) 102305 Memory Protect/Parity Error The diagnostics that specify jumper settings above test data writing and reading and so require the installation of the HP 1251-0332 diagnostic test (loopback) connector in place of the normal device cable connector. This test connector connects each data output bit with its corresponding data input bit and connects the Device Command output signal to the Device Flag input signal. Diagnostic applicability per CPU is: W1 W2 W3 W4 DSN Diagnostic 1000 2100 2116 2115 2114 --- --- --- --- ------ ------------------------------ ---- ---- ---- ---- ---- C B B B 143300 General Purpose Register x - - - - ? ? ? ? 143020 I/O Channel - x - - - B A A B 24163 General Purpose Register - - x x x B C A A/B 24163 General Purpose Register - - x x x C B B B 141203 I/O Instruction Group x - - - - C B B B 102103 Memory Expansion Unit x - - - - C B B B 101220 DMA/DCPC for 2100/1000 x x - - - B A A B 24195 DMA for 2100 - z - - - B A A B 101105 DMA for 2114/2115/2116 (24322) - - x x x B C A A/B 101105 DMA for 2114/2115/2116 (24322) - - x x x B C B B -- DMA for 2115/2116 (24185) - - x x - Under simulation, device command and flag active edges are essentially irrelevent for normal device use, as long as action takes place at the proper time. For loopback diagnostics, though, edge selection is important and is complicated by I/O timing that varies from CPU model to model and from CPU to DMA cycles. Jumpers W1-W3 determine the primary card action in the loopback configuration. From the table above, there are four settings used: 1. C-B-B (DMA/DCPC for 2100/1000 + GPR) 2. B-A-A (DMA for 2100, HP 24195) 3. B-C-A (DMA for 2114/2115/2116, HP 24322) 4. B-C-B (DMA for 2115/2116, HP 24185) The 2116/15/14 and 2100/1000 use different I/O timing. The allowed jumper settings by CPU are: CPU Jumper Settings ---- ----------------------- 211x B-C-A or B-C-B or B-A-A 2100 B-A-A or C-B-B 1000 C-B-B For B-C-B, ENF (T2) assertion clears the Command Flip-Flop, which denies DEV FLG, which sets the Flag Buffer Flip-Flop. The ENF-to-FBF delays are: Sig Typ. Gate Device Dir Delay Signal ---- ------ --- ----- ----------- U86C 7400 H-L 7 U77C 7410 L-H 11 U75A 7440 H-L 8 DEV CMD out U87A 7400 L-H 11 DEV FLG in (delay: 110 ns H-L, 150 ns L-H) U87C 7400 H-L 7 U87D 7400 L-H 11 U86D 7400 H-L 7 U85B 7440 L-H 13 U87B 7400 H-L 7 U35B 7420 L-H 12 FBF Q So ENF L-H to FBF Q L-H is 244 ns typical. As ENF lasts 200 ns (2116) or 225 ns (2115), the Flag Flip-Flop does not set in this cycle and instead sets in the following cycle. Setting #1 asserts Device Command from T6 of one cycle through T2 of the next cycle. The Command flip-flop sets on STC and clears at T6 (the start of the Device Command signal). The Flag Buffer flip-flop is set by the Device Flag signal at T6 as well. As the Flag flip-flop sets at T2 of the next cycle, SKF can be asserted for the instruction following the STC. SRQ asserts with Flag and is detected at the end of the second cycle, so DMA cycles can occur on every other machine cycle. Setting #2... Setting #3 sets the Command flip-flop on STC and clears it at T2 of the next cycle. Device Command asserts with the Command flip-flop, so from STC of one cycle until T2 of the next cycle. The Flag Buffer flip-flop is set by the Device Flag signal on STC as well. If CLF is specified with STC, both the set and reset signals to the Flag Buffer flip-flop are asserted concurrently. Whether the Flag Buffer remains set or not depends on which signal denies first. The set signal asserts for 300 ns., while one T-period is 200 ns. As the Flag flip-flop sets at T2 of the next cycle, SKF can be asserted for the instruction following the STC. SRQ asserts with Flag and is detected at the end of the second cycle, so DMA cycles can occur on every other machine cycle. Setting #4... The 2116, 2115, and 2114 CPUs use an eight-period I/O cycle, designated T0-T7, while 2100 and 1000 CPUs use a five-period cycle designated T2-T6. -------------------- CPU Cycle --------------------- 211x Timing 2100 Timing 1000 Timing Signal T2-T3-T4-T5-T6-T7-T0 T2-T3-T4-T5-T6 T2-T3-T4-T5-T6 ------ -------------------- -------------- -------------- ENF T2 T2 T2 STF T3 T3 T3 CLF T4 T4 T4 STC T4 T4 T4 CLC T4 T4 T4 IOO T3-T4 T3-T4 T3-T4 IOI T4-T5 T4-T5 T4-T5 SFS T3-T4-T5-T6-T7-T0 T3-T4-T5-T6 T3-T4-T5 SFC T3-T4-T5-T6-T7-T0 T3-T4-T5-T6 T3-T4-T5 -------------------- DMA Cycle --------------------- 211x Timing 2100 Timing 1000 Timing Signal T2-T3-T4-T5-T6-T7-T0 T2-T3-T4-T5-T6 T2-T3-T4-T5-T6 ------ -------------------- -------------- -------------- ENF T2 T2 T2 CLF T4-T5 T3 T3 STC T3-T4 T3 T3 CLC T4-T5 T3-T4 T3-T4 IOO T3-T4 T3-T4 T3-T4 IOI T2 T2-T3 T2-T3 srqset T6 T5 T5 This means that STC and CLF are coincident and one T-period in duration (200 ns) EXCEPT when asserted for a 211x DMA cycle, where they are two T-periods in duration (400 ns) and STC leads CLF by one T-period. T-period duration varies by model: Model Duration ------ -------- 2116 200 ns 2115 250 ns 2114 250 ns 2100 196 ns 1000-M 325 ns 1000-E 280 ns* E-Series timing is variable. Periods T3-T5 are 280 ns. Periods T2 and T6 are either 175 ns or 280 ns, depending on the specific micro-order executed. A DMA cycle is initiated by asserting Device Flag, which sets the Flag Buffer flip-flop. At T2 (ENF), the Flag flip-flop sets, asserting SRQ. At the end of T4, SRQ is sampled and sets the Cycle Request flip-flop, which steals the next cycle (T2-T6) for DMA use. DMA asserts CLF during T3, which clears the Flag and Flag Buffer, denying SRQ. The Cycle Request flip-flop is cleared at the end of T4 during the DMA cycle. So asserting Device Flag by T2 of the first cycle (T2-T6) initiates DMA control for the second cycle (T2-T6). Reasserting Device Flag as soon as SRQ denies will set the Flag flip-flop on the next T2 (third cycle), and DMA will control the fourth cycle. So the 12566B card can, at best, obtain DMA control for every other cycle. For the 12566B, setting jumpers W1-W3 to C-B-B uses this DMA timing: T2 - T3 - STC -> sets Command flip-flop CLF -> clears Flag Buffer and Flag flip-flops T4 - T5 - T6 - asserts Device Command -> asserts Device Flag -> sets Flag Buffer flip-flop and clears Command flip-flop T2 - sets Flag flip-flop -> asserts SRQ T3 - denies Device Command -> denies Device Flag T4 - SRQ initiates DMA cycle T5 - T6 - T2 - T3 - STC -> sets Command flip-flop CLF -> clears Flag Buffer and Flag flip-flops T4 - T5 - T6 - asserts Device Command... Setting jumpers W1-W3 to B-A-A or B-C-A uses this DMA timing: T2 - T3 - STC -> sets Command flip-flop CLF -> clears Flag Buffer and Flag flip-flops T4 - asserts Device Command -> asserts Device Flag -> sets Flag Buffer flip-flop and clears Command flip-flop -> denies Device Command -> denies Device Flag T5 - T6 - T2 - sets Flag flip-flop -> asserts SRQ T3 - T4 - SRQ initiates DMA cycle T5 - T6 - T2 - T3 - STC -> sets Command flip-flop CLF -> clears Flag Buffer and Flag flip-flops T4 - asserts Device Command -> asserts Device Flag -> sets Flag Buffer flip-flop and clears Command flip-flop -> denies Device Command -> denies Device Flag T5 - T6 - ==> MAYBE this has nothing to do with the card strapping! For the 2115/2116, the test that fails is the byte packing test. Byte packing takes TWO DMA CYCLES for each word (one for each byte), leading to a full word transferred every THREE machine instructions! ...BUT...this should already be occurring, so what is going on? Maybe it's because each byte should take two machine cycles (total of four), and it's only taking three? ---- 143300 GP Reg uses C B B 101220 DMA/DCPC for 2100/1000 uses C B B 24195 DMA for 2100 uses B A A 101105 DMA for 2114/2115/2116 uses B A A 101105 DMA for 2114/2115/2116 uses B C A 24185 DMA for 2115/2116 uses B C B ----- 24185-8000x Rev. A has: STC 6,C TURN ON DMA1 NOP STC CH,C LIA CH INPUT BITS 8-15 OF OUTPUT WORD STA PWOU2 SAVE STC CH,C LIA CH INPUT BITS 0-7 OF OUTPUT WORD STA PWOL2 SAVE 12578-90013 page DMA-1 says jumpers must be B-C-B-B, which is: W1B - Device Command goes positive true starting at T4 W2C - Device Command clears on ENF (T2) W3B - Device Flag sets Flag Buffer and strobes data on negative edge W4B - Output data is continuously available This produces a DMA cycle every other instruction: - cycle 1: STC, CLF assert at T4 -> DEVCMD, DEVFLG assert at T4 --> Flag Buffer and Flag clear - cycle 2: ENF asserts at T2 -> DEVCMD, DEVFLAG deny at T2 --> Flag Buffer sets -> Flag sets (because still in T2) --> SRQ sets - cycle 2: SRQ seen at T6 -> cycle requested - cycle 3: STC, CLF assert at T4... So cycle 1, cycle 3, etc. are DMA cycles, while cycle 2, cycle 3, etc. are CPU cycles. 24322-1800x Rev. 1502 (DSN 101105) has: STC 6,C TURN ON DMA1 NOP STC CH,C LIA CH INPUT BITS 8-15 OF OUTPUT WORD STA PWOU2 SAVE STC CH,C LIA CH INPUT BITS 0-7 OF OUTPUT WORD STA PWOL2 SAVE ...which is identical to 12578. 02100-90217 page 4 says jumpers must be B-A-A-B, which is: W1B - Device Command goes positive true starting at T4 W2A - Device Command clears on positive edge of Device Flag W3A - Device Flag sets Flag Buffer and strobes data on positive edge This arrangement does NOT assert SRQ after DMA sends the first STC/CLF! Because DEVFLG sets on the same edge as DEVCMD, and DEVCMD clears on this same edge, DEVCMD (and therefore DEVFLG) produces a positive pulse of a 100 ns or so. This sets Flag Buffer, but because CLF asserts 200 ns later for a period of 400 ns, Flag Buffer (and Flag, and so SRQ) are cleared. DMA then stops until the programmed STC CH,C is issued, which does assert SRQ because... NO!!!!!!!!!! This produces a DMA cycle every other instruction: - cycle 1: STC, CLF assert at T4 -> DEVCMD, DEVFLG assert at T4 --> Flag Buffer and Flag clear - cycle 2: ENF asserts at T2 -> DEVCMD, DEVFLAG deny at T2 --> Flag Buffer sets -> Flag sets (because still in T2) --> SRQ sets - cycle 2: SRQ seen at T6 -> cycle requested - cycle 3: STC, DLF assert at T4... ...or B-C-A-x, which is: W1B - Device Command goes positive true starting at T4 W2C - Device Command clears on ENF (T2) W3A - Device Flag ets Flag Buffer and strobes data on positive edge The only way this works is if: STC 6,C TURN ON DMA1 (dma cycle) NOP STC CH,C LIA CH INPUT BITS 8-15 OF OUTPUT WORD (dma cycle) STA PWOU2 SAVE STC CH,C LIA CH INPUT BITS 0-7 OF OUTPUT WORD STA PWOL2 SAVE If the second DMA cycle occurs before the first LIA CH, the diagnostic fails because the second byte is in the input data register when the first is expected. It appears that: - DMA steals the first cycle after the STC 6 because STF CH was done earlier, so SRQ is already asserted when the DMA transfer enable flip-flop is set. - The 12566 card will assert SRQ on every other I/O cycle. Questions: - Why is the NOP instruction present? It must be to add a delay, but the first DMA cycle occurs between the STC 6 and the NOP, while the second occurs between the NOP and the STC CH,C. So it looks as though the NOP actually prevents the code from working.... - Why are the STC CH,C instructions present? DMA is configured to do STC and CLF to the I/O card, so the instructions duplicate the DMA signals. The STC CH,C instruction would postpone the next DMA cycle if it occurred during the intervening cycle, i.e., if the first DMA cycle occurred immediately prior: STC 6,C TURN ON DMA1 NOP (dma cycle) STC CH,C LIA CH INPUT BITS 8-15 OF OUTPUT WORD (dma cycle) STA PWOU2 SAVE STC CH,C LIA CH INPUT BITS 0-7 OF OUTPUT WORD STA PWOL2 SAVE ...because the CLF would clear the Flag and therefore deny SRQ for that cycle; Flag would set and SRQ would reassert at T2 of the LIA instruction, enabing a DMA cycle to follow. But the NOP seems to preclude that. To work as expected, the code should be: STC 6,C TURN ON DMA1 (dma cycle) LIA CH INPUT BITS 8-15 OF OUTPUT WORD (dma cycle) STA PWOU2 SAVE LIA CH INPUT BITS 0-7 OF OUTPUT WORD STA PWOL2 SAVE But it isn't, and it works as written, so there's something else at work here. --------------------------------------------------- 2116 machine cycle is T0-T7. 2116 CPU I/O cycle: - STC is T4 - CLF is T4 2116 DMA I/O cycle: - STC is T3-T4 - CLF is T4-T5 2116 DMA samples SRQ at T6. --------------------------------------------------- The two DMA diagnostics for the 2116 (and 2115 and 2114) are 24185-80001 Rev. A and 24322-18001 Rev. 1502. The corresponding manuals give three different strapping arrangements for the 12566 card: 1. B-C-B (24185) 2. B-A-A (24322) 3. B-C-A (24322) The code that tests byte packing is the same for the two diagnostics: STF CH [...] STC 6,C TURN ON DMA1 NOP STC CH,C LIA CH INPUT BITS 8-15 OF OUTPUT WORD STA PWOU2 SAVE STC CH,C LIA CH INPUT BITS 0-7 OF OUTPUT WORD STA PWOL2 SAVE ...so all three strapping arrangements must produce the same behavior. The two STC CH,C instructions in the code above suggests that DMA does not run I/O cycles on its own. And, in fact, the B-C-A strapping does not set the Flag flip-flop (or, to be accurate, sets and then clears the Flag Buffer flip-flop in the same cycle, so that ENF does not set the Flag flip-flop). A peculiarity of the 2116 is that the DMA and CPU cycles use different pulse durations -- DMA asserts STC for T3-T4 and CLF for T4-T5, but the CPU asserts both for T4 only. This is significant, as the B-C-A strapping allows the extension of CLF into T5 during a DMA cycle to clear the Flag Buffer flip-flop, which does not occur with the coincident STC and CLF signals in a CPU cycle. Consequently, this strapping prevents a DMA cycle from setting the flag while allowing a CPU cycle to set it during the cycle following STC assertion. For the 2100, the two DMA diagnostics are 24195-80001 Rev. A and 24322-18002 Rev. 1705. The corresponding manuals give two strapping arrangements for the 12566 card: 1. B-A-A (24195) 2. C-B-B (24322) Both of these strappings set the flag in the cycle following the STC for both DMA and CPU cycles, so both execute one instruction following the STC before SRQ and/or an interrupt occurs. For the 1000, the DMA diagnostic is 24322-18002 Rev. 1705. This is the same as is used for the 2100, and so the strapping arrangement is the same: 1. C-B-B (24322) This behaves as above for the 2100, i.e., the flag sets during the cycle following the STC. In summary, asserting STC sets the flag in the following cycle for all strappings and CPU combinations except a 2116 DMA cycle with B-C-A strapping. For any of these three strappings, the simulator must: - not set the flag after STC during a DMA cycle - set the flag after the instruction after the STC during a CPU cycle (i.e., schedule the flag set after two event ticks) - not alter the flag for a CLC following an STC during a CPU cycle. --------- 100 ns increments For the 12566B, setting jumpers W1-W3 to C-B-B uses this DMA timing: T2 - T2+ - T3 - STC -> sets Command flip-flop CLF -> clears Flag Buffer and Flag flip-flops T3+ - T4 - T4+ - T5 - T5+ - T6 - asserts Device Command -> asserts Device Flag -> sets Flag Buffer flip-flop and clears Command flip-flop T6+ - T2 - sets Flag flip-flop -> asserts SRQ T2+ - T3 - denies Device Command -> denies Device Flag T3+ - T4 - SRQ initiates DMA cycle T4+ - T5 - T5+ - T6 - T6+ - T2 - T3 - STC -> sets Command flip-flop CLF -> clears Flag Buffer and Flag flip-flops T4 - T5 - T6 - asserts Device Command... ================================================================================================================================================================ W1 C - Device Command Signal pulsed ground true asserted for T6 and T2 W2 B - Device Command Flip-Flop clears on negative edge of Device Flag W3 B - Device Flag Signal sets Flag Buffer and strobes data on negative edge : T2 : T3 : T4 : T5 : T6 : T2 : T3 : T4 : T5 : T6 : T2 : T3 : T4 : T5 : T6 : +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ + | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | + +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ : : : +---------+ : : +---------+ : STC CLF | | : : | | : ----------+ +-----------------------------------------------------------------------------------------+ +------------------------------ : : : +----------------------------------+ : : +----------------------------------+ : DEVCMD FF | | : : | | : ----------+ +----------------------------------------------------------------+ +----- : : : ----------------------------------------+ : +--------------------------------------------- : DEVCMD | : | : : DEVFLG +-------------------+ : : : : : +-------------------+ : : DEVFLG DELAY | : | : : ---------------------------------------------+ : +---------------------------------------- : : : : ---------------------------------------------+ : +--------------------------------------------- : DEVCMD FF RESET | : | : : +--------------+ : : : : : +--------------+ : : FLGBUF FF SET | : | : : ---------------------------------------------+ : +--------------------------------------------- : : : : ----------+ +------------------------------------------------------------ : FLGBUF FF | | : : : +----------------------------------+ : : : : srq sampled : : srq sampled : : ----------+ : +------------------------------------------------------- FLG FF | : | : +---------------------------------------+ ================================================================================================================================================================ W1 B - Device Command Signal positive true asserted with STC W2 A - Device Command Flip-Flop clears on positive edge of Device Flag W3 A - Device Flag Signal sets Flag Buffer and strobes data on positive edge : T2 : T3 : T4 : T5 : T6 : T2 : T3 : T4 : T5 : T6 : T2 : T3 : T4 : T5 : T6 : +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ + | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | + +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ : : : +---------+ : : +---------+ : STC CLF | | : : | | : ----------+ +-----------------------------------------------------------------------------------------+ +------------------------------ : : : +----+ : : +----+ : DEVCMD FF | | : : | | : ----------+ +----------------------------------------------------------------------------------------------+ +----------------------------------- : : : +----+ : : : DEVCMD | | : : : DEVFLG ----------+ +------------------------------------------------------------------------------------------ : : : : ---------------+ +------------------------------------------------------------------------------------ : DEVFLG DELAY | | : : : +----+ : : : : : : ---------------+ +------------------------------------------------------------------------------------- : DEVCMD FF RESET | | : : : +----+ : : : : : : +----+ : : : FLGBUF FF SET | | : : : ---------------+ +------------------------------------------------------------------------------------- : : : : ----------+ +------------------------------------------------------------------------------------------ : FLGBUF FF | | : : : +----+ : : : : srq sampled : : srq sampled : : ----------+ : +------------------------------------------------------- FLG FF | : | : +---------------------------------------+ ================================================================================================================================================================ W1 B - Device Command Signal positive true asserted with STC W2 C - Device Command Flip-Flop clears on ENF (T2) W3 A - Device Flag Signal sets Flag Buffer and strobes data on positive edge : T2 : T3 : T4 : T5 : T6 : T2 : T3 : T4 : T5 : T6 : T2 : T3 : T4 : T5 : T6 : +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ + | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | + +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ : : : +---------+ : : +---------+ : STC CLF | | : : | | : ----------+ +-----------------------------------------------------------------------------------------+ +------------------------------ : : : +---------------------------------------+ : +---------------------------------------+ DEVCMD FF | | : | | ----------+ +-----------------------------------------------------------+ + : : : +---------------------------------------+ : : DEVCMD | | : : DEVFLG ----------+ +------------------------------------------------------- : : : : ---------------+ +------------------------------------------------- : DEVFLG DELAY | : | : : +---------------------------------------+ : : : : : +---------------------------------------+ +---------------------------------------+ +------ : DEVCMD FF RESET | | | | | : ----------+ +---------+ +---------+ : : : : +--------------+ : : : FLGBUF FF SET | | : : : ---------------+ +---------------------------------------------------------------------- : : : : ----------+ +------------------------------------------------------------------------------------------ : FLGBUF FF | | : : : +----+ : : : : srq sampled : : srq sampled : : ----------+ : +------------------------------------------------------- FLG FF | : | : +---------------------------------------+ ================================================================================================================================================================ 24185: W1 B - Device Command Signal positive true asserted with STC W2 C - Device Command Flip-Flop clears on ENF (T2) W3 B - Device Flag Signal sets Flag Buffer and strobes data on negative edge : T2 : T3 : T4 : T5 : T6 : T2 : T3 : T4 : T5 : T6 : T2 : T3 : T4 : T5 : T6 : +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ + | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | + +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+ : : : +---------+ : : +---------+ : STC CLF | | : : | | : ----------+ +-----------------------------------------------------------------------------------------+ +------------------------------ : : : +---------------------------------------+ : +---------------------------------------+ DEVCMD FF | | : | | ----------+ +-----------------------------------------------------------+ + : : : +---------------------------------------+ : : DEVCMD | | : : DEVFLG ----------+ +------------------------------------------------------- : : : : ---------------+ : +------------------------------------------------- : DEVFLG DELAY | : | : : +---------------------------------------+ : : : : : +---------------------------------------+ +---------------------------------------+ +------ : DEVCMD FF RESET | | | | | : ----------+ +---------+ +---------+ : : : : : +--------------+ : : FLGBUF FF SET : | | : : -------------------------------------------------------+ +---------------------------------- : : : : ----------+ : +------------------------------------------------------+ : FLGBUF FF | : | : | : +--------------------------------------------+ : +-------------------- : : srq sampled : : srq sampled : : ----------+ : : +------------------------------------------------------+ : FLG FF | : : | : : | : +--------------------------------------------+ : +--------------------- : ================================================================================================================================================================ W1 B - Device Command Signal positive true asserted with STC W2 A - Device Command Flip-Flop clears on positive edge of Device Flag W3 A - Device Flag Signal sets Flag Buffer and strobes data on positive edge type signal = (L, LtoH, H, HtoL); -- low, rising, high, falling card_reset cmd FF := CLEAR if W1=B then device_command := L else device_command := H device_reset device_flag := L (or H) -- this is the idle state CRS (and CLC if W9=A) cmd FF := CLEAR if device_command = H then cancel card_service device_command := HtoL call handshake -- or maybe just inline here? STC cmd FF := SET if device_command = L then device_command := LtoH call handshake -- or maybe just inline here? handshake if device_command = LtoH then call card_service device_command := H elsif device_command = HtoL then call card_service device_command := L card_service call device_service if device_flag = LtoH then device_flag := H flag buffer FF := SET cmd FF := CLEAR device_command := HtoL call device_service device_command := L if device_flag = HtoL then device_flag := L device_service if device_command = LtoH then schedule card_service -- I/O operation delay elsif device_command = H then do I/O operation device_flag := LtoH elsif device_command = HtoL then device_flag := HtoL else -- device_command = L device_flag := L ------------------- Remote Program Load ------------------- RPL is a feature that was present in the E-Series from its inception. As reported in the March 1977 HP Journal article: Remote program load (RPL) is a feature of the E-Series base set microcode that allows users to initiate an automatic bootstrap and run operation from either a local or a remote site. This operation consists of a complete bootstrap load operation from disc, communication line, or other specified device, followed automatically by its execution. Thus, RPL is useful in distributed processing systems where automatic startup must be initiated from a remote or unattended location. [...] The RPL process can be triggered in any of three ways: an I/O interface manipulating the processor RUN flip-flop, cold power-up of the processor, or execution of a HALT instruction. Any of these events can trigger RPL provided other conditions are met. The operator panel key must be in the LOCK position, and the configuration switch block located on the processor board must be properly set. Eight switches there are used to provide the I/O device select code and ROM loader selection previously provided by the operator. In addition, a switch that enables RPL must be in the enable position. [...] Special care must be used in systems that run with RPL enabled because the RPL process will be initiated by every HALT encountered. There is also a figure that shows a 12966A or 12968A BACI card as the source of the remote halt by pulling the i/O backplane RUN signal low. The BACI schematic shows that the card has an uncommitted driver (2N4401 transistor collector pulldown to ground) connected to the RUN line. The driver input is brought to the card-edge connector but is not used in any of the HP-standard communications cables. The RUN signal is mentioned in the I/O section of the HP 1000 M/E/F-Series Computer Technical Reference Handbook in connection with RPL, but the description states simply that pulling the line low "reset[s] the computer's Run flip-flop, and return[s] the computer to its halt microroutines." Checking the schematic in the HP 1000 M/E/F-Series Computers Engineering and Reference Documentation shows that the flip-flop can be reset but not set via the RUN line. Page 2-13 in the reference section of the Technical Reference Handbook states that RPL is initiated if RPL is enabled via switch S8, the LOCK/OPERATE switch is in the LOCK position, and either (a) cold power-up, (b) halt instructions 1060xx or 1070xx are executed, (c) forced halts initiated by the I/O system. It continues that RPL is inhibited by (a) LOCK/OPERATE switch in the OPERATE position, (b) auto-restart enabled, power coming up, and PRESET not pressed, (c) halts 1020xx or 1030xx, or (d) halt caused by a parity error. The M/E/F-Series ROM History in the Communicator/1000 for Software Update 6.2 shows seven firmware releases for the E-Series base-set ROMs. The descriptions are: 1. Fix bug in floating-point routine. 2. Fix bug in DLD 0 instruction. 3. Redefine "RPL after halt" feature. 4. Remove potential failure when executing RPL after halt. 5. Add "RJ30" micro-order to LIA and MIA instructions. 6. Add "Suspend Halt" state for use with 91750A DS/1000 Forced Cold Load feature. Fix 3 is mentioned on page 25 of the Communicator 1000 Issue 16 (November 1977) in an article titled, "Auto Boot-Up for 21MXE Computers." It states: The auto boot-up/RPL capability available with the HP 21MX E-Series computer has been enhanced to provide mode flexibility. The new 21MX E-Series computer (2109B/2113B) contains a new power supply that is not dependent on a reset signal, so the full capability of auto boot-up/RPL can be realized. [...] All of the functions just described will be done automatically when power is applied to the system, or when a HLT instruction, 1060XX or 1070XX, is executed. [...] The auto boot-up/RPL definition for the HP 21MX E-Series computers (2109A/2113A, A-Model) has been modified to provide more flexibility. [...] Once the switches are configured, the computer will take appropriate action if auto boot-up/RPL is enabled. If it is enabled, then on power-up or HLT (1060XX or 1070XX only), the microcode of the base set will store the configuration switches into the appropriate S-Register bits, jump to the IBL microcode routine, and jump to the RUN microcode routine, which issues a RUN signal to the computer. Note that the original mention of pulling the I/O backplane RUN signal down is not present. The 02113-18007 source file contains the E-Series base set microcode. The comments apparently document Fix 6 above: Edited 801003 The front panel and halt routines were modified to add a new halt state, called "Suspend Halt". This state will be entered only if the following conditions are met: 1) RPL switches on the CPU board are enabled. 2) LOCK/OPERATE switch set to LOCK. 3) Parity error FF clear. 4) Halt 1020XX or 1030XX executed. If these conditions are all met, the CPU will enter the Suspend Halt (SH) state. The CPU will halt with the halt displayed in the T-Register but the Run FF will be set. This will allow an I/O device to pull the RUN line on the I/O backplane low and reboot the computer following a 102, 103 halt. Pressing any front panel switch sensed by NSTB will cause the microcode to go to the normal halt routine with the Run FF clear. This seems to imply that pulling the RUN line low did not work, i.e., would halt the computer but not initiate the RPL process. The microcode does check the LOCK switch via the RUNE condition, so it should not be possible to initiate RPL with the switch in the OPERATE position. Note that the NSTB condition occurs when none of the MODE, STORE, <<. >>, INC M, DEC M, PRESET, IBL, RUN, or INSTR STEP button is pressed. -------------------------------------- 12578A Direct Memory Access Diagnostic -------------------------------------- The 12578A DMA card is used with the 2115 and 2116 computers. It implements byte packing and unpacking, and this feature is tested by the diagnostic. The diagnostic uses a 12566B Microcircuit Interface card with a loopback connector. The card is strapped in a fashion different from that used when running diagnostics on the 2100 and 1000 systems: - for 2116 DMA (12578): W1-B, W2-C, W3-B, W4-B, W5-W8-in, W9-A - for 1000 DMA (12897): W1-C, W2-B, W3-B, W4-B, W5-W8-in, W9-A The differences are: - W1: B = +true device command level at T4 C = -true device command pulse from T6 through T2 - W2: B = device command clears on negative-going device flag C = device command clears on ENF With the connector, device command is looped back to device flag. With W3 in position B, the flag buffer sets and input data is latched on the negative-going edge of device flag. The implication of this for the 12578A diagnostic is that the STC that occurs during the DMA cycle sets the device command flip-flop at T3, resulting in a low-to-high transition on the device flag signal. Because W3 is in position B, this produces no change in the card. At the next T2 (ENF), during the execution of the next instruction, the device command flip-flop clears, denying the device flag signal. This negative edge propagates through a delay and several gates and eventually sets the flag buffer flip-flop. The flag buffer output is used to set the flag flip-flop at T2, and the flag output is used to assert SRQ. SRQ is sampled at T6, enabling a CPU freeze and a DMA cycle in lieu of the following instruction. Because the device command, flag buffer, and flag flip-flops are S-R latches, they respond to signal levels instead of edges. Looking at the path through the gates from ENF to the output of the flag buffer appears to delay the signal about 200 nanoseconds. This is exactly the length of the ENF pulse, meaning that the flag flip-flop will not set until the next T2 of the following instruction execution, and this implies that the next DMA cycle will occur at the end of the second instruction after the previous cycle. Therefore, DMA will steal every third cycle with this jumper configuration. For the 1000 configuration, the STC that occurs during the DMA cycle sets the device command flip-flop, which sets the party-line flip-flop at T6, resulting in a low-true pulse on the device flag signal. This causes a high-going pulse that sets the flag buffer flip-flop. At the next T2, the flag sets, asserting SRQ. SRQ is sampled at T4 (E/F-Series) or T5 (M-Series), enabling a CPU freeze and a DMA cycle one instruction after the last cycle. Therefore, DMA will steal every other cycle with this jumper configuration. Test 17 of the diagnostic tests output unpacking. A one-word packed DMA transfer is set up to the 12566B card. The diagnostic starts DMA and then does two LIA instructions. It expects to read the high byte and then the low byte of the transferred word value. The code, though, is a little odd: STC 6,C TURN ON DMA1 * [ high byte DMA cycle ] NOP STC CH,C * [ low byte DMA cycle ] LIA CH INPUT BITS 8-15 OF OUTPUT WORD STA PWOU2 SAVE STC CH,C LIA CH INPUT BITS 0-7 OF OUTPUT WORD STA PWOL2 SAVE SFS 6 JSB FLG.1,I E50. DMA1 FLG NOT SET AFTER XFR With the 211x jumper configuration, the two DMA output cycles will occur between the STC 6 and the NOP, and between the first STC CH,C and the LIA CH. Because the input data is latched on the trailing edge of the device flag signal (as W3 is in position B), the input register obtains the output data at T2 of the instruction following a DMA cycle. So the high byte is latched at T2 of the NOP. The low byte would normally be latched at T2 of the first LIA CH, and as data isn't stored in the A register until IOI at T4-T5, it should obtain the second byte data instead. However, DMA is programmed to issue a CLC at the end of the transfer, so the second DMA cycle issues both STC and CLC, and that inhibits setting the device flag, leaving the high byte present in the input register. When the second STC CH,C is executed, device command is set, and at T2 of the following LIA CH, it is reset, leading to the input register latching the low byte data. The first STC CH,C doesn't seem to do anything. One additional point: the 12607B/12578A/12895A DMA Controllers for the 21xx computers do not experience startup latencies if they are enabled with SRQ already asserted, e.g., by an STF . For these cards, STC 6 sets the TE flip-flop at T4, which enables SRQ to the CR1 flip-flop. With TE and SRQ asserted, the CR1 flip-flop is set at T6, which enables CR1 to the PH5 flip-flop. With CR1 asserted, the PH5 flip-flop sets at T7, freezing the CPU for the next cycle. So with SRQ already asserted, DMA will steal the cycle immediately after the STC 6 instruction. ----------------------------------------------- Microcode interruptibility failures on the 2100 ----------------------------------------------- Several diagnostics (IOP, FFP) test the interruptibility of certain instructions. These diagnostics fail on the 2100 but pass on the 21MX. On the 21MX, testing is done by using a standard interface card (e.g., the 12566B), setting the control and flag flip-flops on the card, and then enabling the interrupt system immediately before executing the instruction to be tested. This means that the interrupt flag ("intrq") passed to the simulation routine is set and can be detected by the instruction handler. The 2100 diagnostics use the time-base generator card for interruptibility tests. They set the card to the minimum time (100 microseconds), start the card, turn the interrupt system on, delay about 75 microseconds, and then execute the instruction under test. The expectation is that the TBG will tick some time during the instruction execution. Under simulation, though, all instructions take the same amount of "time," so the interrupt occurs some time after the tested instruction completes, and the diagnostic fails. The TBG hardware explicitly resets its internal counters on IOO, so that the first interval is the same as the subsequent ones. About the only way to simulate interruptibility on the 2100 would be to advance the simulator clock by an appropriate amount during the instruction execution, then recalculating interrupts, based on event timer expirations, and then aborting execution if an interrupt is detected. Whether that is worthwhile, just to pass the diagnostics, is debatable. Also questionable is the effect that would have on the wall-time calibration of the TBG.