HP 21xx/1000 Instruction Set Notes ================================== The HP 21xx/1000 instruction set is fairly irregular -- undoubtedly a legacy of its original implementation in hardware in the 2116 and the accretion of microprogrammed instructions in the 2100 and 1000 CPUs. Initially, there were five base-set instruction groups: 1. Memory-Reference Group (MRG) 2. Shift-Rotate Group (SRG) 3. Alter-Skip Group (ASG) 4. I/O Group (IOG) 5. Macroinstruction Group (MAC) All of the instructions added after the 2116 are in the Macroinstruction Group. The 2116 offered two hardware options that extended the instruction set. The first is the 12579A Extended Arithmetic Unit. The second is the 2152A Floating Point Processor, which is interfaced through, and therefore requires, the EAU. The EAU adds 10 instructions including integer multiply and divide and double-word loads, stores, shifts, and rotates. The FPP adds 30 floating-point arithmetic, trigonometric, logarithmic, and exponential instructions. -------------------- Instruction Decoding -------------------- The base set groups are decoded from bits 15-12 and 10, as follows: 15 14-12 10 Group Address Ranges -- ----- -- ----- ------------------------------- x nnn x MRG 010000-077777 and 110000-177777 0 000 0 SRG 000000-001777 and 004000-005777 0 000 1 ASG 002000-003777 and 006000-007777 1 000 1 IOG 102000-103777 and 106000-107777 1 000 0 MAC 100000-101777 and 104000-105777 Where: x = don't care n = any combination other than all zeros The MAC group is subdivided into the Extended Arithmetic Group (EAG) and the User Instruction Group (UIG), based on bits 11, 9, and 8, as follows: 11 9 8 Group Address Range -- -- -- ----- ------------- 0 0 0 EAG 100000-100377 0 0 1 EAG 100400-100777 0 1 0 EAG 101000-101377 0 1 1 UIG-1 101400-101777 1 0 0 EAG 104000-104377 1 0 1 EAG 104400-104777 1 1 0 UIG-0 105000-105377 1 1 1 UIG-1 105400-105777 All of the 2116 FPP instructions are in the UIG sets: 3 use 10144x opcodes and the rest use 1050xx and 1054xx opcodes. The 2100 decodes only UIG-0 instructions, whereas the 1000s use both UIG sets. In particular, the 105740-105777 range is used by the 1000 Extended Instruction Group (EIG), which is part of the base set. The 21xx and 1000 M/E/F-Series machines do not trap unimplemented instructions. In general, unimplemented EAG instructions cause erroneous execution, and unimplemented UIG instructions execute as NOP. However, there are machine-to- machine variations, and some unimplemented instructions execute as other, defined instructions. ---------------------- I/O Group Instructions ---------------------- Canonical encoding: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | R | 1 | H | i/o op | select code | IOG +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: R = A/B register (0/1) H = hold/clear flag (0/1) Specific encoding: 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | - 1 H | 0 0 0 | select code | HLT +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | - 1 0 | 0 0 1 | select code | STF +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | - 1 1 | 0 0 1 | select code | CLF +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | - 1 H | 0 1 0 | select code | SFC +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | - 1 H | 0 1 1 | select code | SFS +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | R 1 H | 1 0 0 | select code | MIA/B +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | R 1 H | 1 0 1 | select code | LIA/B +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | R 1 H | 1 1 0 | select code | OTA/B +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 0 1 H | 1 1 1 | select code | STC +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 1 H | 1 1 1 | select code | CLC +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Decoding bits 15-6: bits ---- bits 7-6 ---- 15-8 00 01 10 11 ---- --- --- --- --- 204 HLT STF SFC SFS 205 MIA LIA OTA STC 206 HLT CLF SFC SFS 207 MIA LIA OTA STC 214 HLT STF SFC SFS 215 MIB LIB OTB CLC 216 HLT CLF SFC SFS 217 MIB LIB OTB CLC ---------------------------------------- Unimplemented vs. undefined instructions ---------------------------------------- SIMH provides a CPU flag, STOP_INST, that can be used to stop the simulator if an undefined or unimplemented instruction execution is attempted. The default value of 0 allows execution to continue; setting the value to 1 stops execution. However, the documentation is contradictory as to whether the intended condition is attempted execution of an UNDEFINED instruction (i.e., one not listed in the CPU manual) or an UNIMPLEMENTED instruction (i.e., one not simulated by SIMH). "hp2100_doc.pdf" says the former, and "hp2100_cpu.c" says the latter. Moreover, it is not clear whether "unimplemented" is intended to mean instructions for which no simulation code is currently written (e.g., DS/1000 firmware) or instructions not present in the currently selected CPU model (e.g., floating-point in a 2116). To my knowledge, there are no "unpredictable" instructions in the 21xx series. All instruction execution is deterministic. Also, with the exception of the (currently unsupported) A-Series, no 21xx/1000 machine trapped on undefined instructions. The 1000-MEF machines dispatched each instruction with a microcoded jump, based on certain bits in the instruction register. So every instruction decoded successfully. The only documented response to unimplemented instructions was for the UIG codes (101xxx and 105xxx), which were used for CPU firmware options; a "missing" instruction defaulted to a NOP. Unfortunately, this often had catastrophic effects on a program using such instructions. As most were multi-word, the NOP would result in the execution of the second word of the instruction, which was often a data pointer. The current HP2100 simulator handles STOP_INST = 1 inconsistently. Attempted execution of instructions corresponding to unselected firmware options will cause a simulator stop. Execution of undefined UIG codes will cause a stop, except for undefined codes in the "base" floating-point instruction set, which execute as the associated defined code (as on the hardware). Execution of some undefined base set instructions is allowed, including the E/F-Series TIMER instruction on the M-Series (but not on the 21xx machines), except for the DIAG and EXECUTE instructions, which are prohibited on the M-Series as well as the 21xx. Ideally, STOP_INST would provide several modes: A. allow execution of every possible instruction code by matching what the hardware does B. stop on every instruction code not explicitly documented and enabled for the particular hardware configuration C. stop on all undefined, unimplemented, and unselected codes except those known to be used by CPU detection and/or operating systems D. stop on unselected and unimplemented UIG (firmware option) codes, but allow all undefined and unselected base-set instructions Mode A matches the machine but is not particularly useful. Because the 21xx/1000 does not trap on illegal instructions, a program that wanders off into the weeds typically just quits working, as every bit pattern causes some sort of execution. It would be more helpful to the average user if the simulator stopped in such cases. Mode B is useful for the developer, as it will cause stops where an OS or diagnostic intentionally attempts CPU model or option detection. This aids bringing up a new OS under simulation or refining an I/O device implementation. Mode C is useful for the end-user, as it will stop if the simulator is not configured properly for the software, or if the software uses features not yet implemented in the simulator. It should be the default, as this will help to resolve configuration problems more easily than Mode A. -------------------------------------- Undefined (Non-Canonical) Instructions -------------------------------------- The MRG instructions are fully decoded. The SRG instructions are partially decoded. These instructions contain two enable bits for the two shift and rotate operation fields. If an enable bit is zero (disabled), then the associated operation field bits become "don't care," although canonically the bits should be zeros. The operation fields depend on the A/B register select bit, as does the SLA/B operation field. If both enable bits are zero, and the SLA/B operation field is zero, then the register select bit becomes "don't care." In all cases, execution is defined. The ASG instructions are also partially decoded. All operation fields except the CLE/CME/CCE, SEZ, and RSS fields depend on the A/B register select bit. If an instruction contains none of the dependent fields, then the register select bit becomes "don't care." In all cases, execution is defined. The IOG instructions are fully decoded, except for bit 11, which is "don't care" for the HLT, STF, CLF, SFC, and SFS instructions. Bit 9, the "hold/clear" bit, is specified as 0 for the SFC and SFS instructions; however, setting bit 9 to 1 will clear the flag after testing (RTE depends on this behavior in $CIC, where it is used to test the state of the interrupt system and turn it off in the same instruction). In all cases, execution is defined. UIG instruction decoding depends on the individual firmware module. If the module is absent, the assigned instructions execute as NOP. Otherwise, execution of unimplemented instructions within a module depend on the specific module coding. Typically, they are coded as NOPs but in some cases cause erroneous execution or perform undocumented actions. The EAG instructions are decoded partially, with many "don't care" bits. Moreover, undefined instruction decoding varies from machine-to-machine. Canonical encoding: 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 0 0 0 | 0 0 0 | 0 1 | shift count | ASL +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 0 0 0 | 0 0 0 | 1 0 | shift count | LSL +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 0 0 0 | 0 0 1 | 0 0 | shift count | RRL +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 0 0 0 | 0 1 0 | 0 0 0 | 0 0 0 | MPY +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 0 0 0 | 1 0 0 | 0 0 0 | 0 0 0 | DIV +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 0 0 1 | 0 0 0 | 0 1 | shift count | ASR +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 0 0 1 | 0 0 0 | 1 0 | shift count | LSR +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 0 0 1 | 0 0 1 | 0 0 | shift count | RRR +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 0 | 0 1 0 | 0 0 0 | 0 0 0 | DLD +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 0 | 1 0 0 | 0 0 0 | 0 0 0 | DST +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 2116 EAU decoding (qualified by 15 * ~14 * ~13 * ~12 * ~10): - ASL : ~11 * ~9 * 4 - LSL : ~11 * ~9 * 5 - RRL : ~11 * ~9 * 6 - MPY : ~11 * 7 - DIV : ~11 * 8 - ASR : ~11 * 9 * 4 - LSR : ~11 * 9 * 5 - RRR : ~11 * 9 * 6 - DLD : 11 * 7 - DST : 11 * 8 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 0 | 0 | 0 | - | - | - | - | 1 | shift count | ASL +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 0 | 0 | 0 | - | - | - | 1 | - | shift count | LSL +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 0 | 0 | 0 | - | - | 1 | - | - | shift count | RRL +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 0 | 0 | - | - | 1 | - | - | - | - - - - | MPY +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 0 | 0 | - | 1 | - | - | - | - | - - - - | DIV +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 0 | 0 | 1 | - | - | - | - | 1 | shift count | ASR +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 0 | 0 | 1 | - | - | - | 1 | - | shift count | LSR +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 0 | 0 | 1 | - | - | 1 | - | - | shift count | RRR +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 | 0 | - | - | 1 | - | - | - | - - - - | DLD +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 | 0 | - | 1 | - | - | - | - | - - - - | DST +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 2100 EAU decoding (qualified by 15 * ~14 * ~13 * ~12 * ~10): - MPY (RAR 210) : ~11 * ~9 * ~8 * 7 * ~6 * ~5 * ~4 - DIV (RAR 220) : ~11 * ~9 * 8 * ~7 * ~6 * ~5 * ~4 - DLD (RAR 310) : 11 * ~9 * ~8 * 7 * ~6 * ~5 * ~4 - DST (RAR 320) : 11 * ~9 * 8 * ~7 * ~6 * ~5 * ~4 - ASR (RAR 241) : ~11 * 9 * ~8 * ~7 * ~6 * ~5 * 4 - ASL (RAR 201) : ~11 * ~9 * ~8 * ~7 * ~6 * ~5 * 4 - LSR (RAR 242) : ~11 * 9 * ~8 * ~7 * ~6 * 5 * ~4 - LSL (RAR 202) : ~11 * ~9 * ~8 * ~7 * ~6 * 5 * ~4 - RRR (RAR 244) : ~11 * 9 * ~8 * ~7 * 6 * ~5 * ~4 - RRL (RAR 204) : ~11 * ~9 * ~8 * ~7 * 6 * ~5 * ~4 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | shift count | ASL +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | shift count | LSL +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | shift count | RRL +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | - - - - | MPY +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | - - - - | DIV +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | shift count | ASR +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | shift count | LSR +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | shift count | RRR +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | - - - - | DLD +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | - - - - | DST +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Note that the 2100 microcode uses a "legal entry point" (LEP) micro-order to validate ROM jumps. An invalid jump address executes microcode NOPs until either a LEP or EOP ("end of phase") micro-order is encountered. This means that while a different instruction may execute, the micromachine will not hang or execute improperly. 1000 M-Series decoding dispatched on upper 8 bits: - ASL (200) : ~7 * ~5 * 4 - LSL (200) : ~7 * 5 * ~4 - RRL (200) : ~7 * ~5 * ~4 - MPY (200) : 7 + 5 * 4 (i.e., 011 or 1xx) - DIV (201) - ASR (202) : ~7 * ~5 * 4 - LSR (202) : ~7 * 5 * ~4 - RRR (202) : ~7 * ~5 * ~4 - DLD (210) - DST (211) 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 0 | 0 0 0 | 0 0 0 | 0 | - | 0 | 1 | shift count | ASL +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 0 | 0 0 0 | 0 0 0 | 0 | - | 1 | 0 | shift count | LSL +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 0 | 0 0 0 | 0 0 0 | 0 | | 0 | 0 | shift count | RRL +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 0 | 0 0 0 | 0 0 0 | 0 | - | 1 | 1 | - - - - | [MPY] +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 0 | 0 0 0 | 0 0 0 | 1 | - | - | - | - - - - | MPY +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 0 | 0 0 0 | 0 0 1 | - - - - - - - - | DIV +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 0 | 0 0 0 | 0 1 0 | 0 | - | 0 | 1 | shift count | ASR +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 0 | 0 0 0 | 0 1 0 | 0 | - | 1 | 0 | shift count | LSR +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 0 | 0 0 0 | 0 1 0 | 0 | - | 0 | 0 | shift count | RRR +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 0 | 0 0 0 | 0 1 0 | 0 | - | 1 | 1 | - - - - | [NOP] +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 0 | 0 0 0 | 0 1 0 | 1 | - | - | - | - - - - | [NOP] +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 0 | 0 0 1 | 0 0 0 | - - - - - - - - | DLD +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 0 | 0 0 1 | 0 0 1 | - - - - - - - - | DST +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 1000 E/F-Series decoding: 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 0 | 0 0 0 | 0 0 0 | 0 0 0 0 | - - - - | DIAG (NOP) +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 0 | 0 0 0 | 0 0 0 | 0 0 0 1 | shift count | ASL +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 0 | 0 0 0 | 0 0 0 | 0 0 1 0 | shift count | LSL +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 0 | 0 0 0 | 0 0 0 | 0 0 1 1 | - - - - | TIMER +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 0 | 0 0 0 | 0 0 0 | 0 1 0 0 | shift count | RRL +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 0 | 0 0 0 | 0 0 0 | 1 0 0 0 | 0 0 0 0 | MPY +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 0 | 0 0 0 | 0 0 1 | - - - - - - - - | DIV +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 0 | 0 0 0 | 0 1 0 | 0 0 0 1 | shift count | ASR +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 0 | 0 0 0 | 0 1 0 | 0 0 1 0 | shift count | LSR +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 0 | 0 0 0 | 0 1 0 | 0 1 0 0 | shift count | RRR +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 0 | 0 0 1 | 0 0 0 | - - - - - - - - | DLD +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 0 | 0 0 1 | 0 0 1 | - - - - - - - - | DST +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Undefined HP 1000 Instructions ------------------------------ 0 000 ~~~~~ [010-013 = SRG] 0 000 10x xxx xx0 xxx (A/B = B, but SLA/B disabled: same as no skip, bit 11 ignored) [004, 014 = ASG] 0 000 x10 000 000 000 (ASG, but no operation enabled: same as NOP) 1 000 x1x (IOG) ~~~~~~~~~~~~~~~ [214, 216 = IOG] 1 000 11x 000 xxx xxx (HLT + bit 11: same as HLT) 1 000 11x 001 xxx xxx (STF/CLF + bit 11) 1 000 011 01x xxx xxx (SFC/SFS + H/C bit 9 set) 1 000 110 01x xxx xxx (SFC/SFS + bit 11) 1 000 111 01x xxx xxx (SFC/SFS + bit 11 + H/C set) 1 000 x0x (EAU) ~~~~~~~~~~~~~~~ 1 000 000 011 xxx xxx 1 000 000 101 xxx xxx 1 000 000 110 xxx xxx 1 000 000 111 xxx xxx 1 000 001 010 xxx xxx 1 000 001 010 xxx xxx 1 000 001 1xx xxx xxx ---------------------- User Instruction Group ---------------------- There are three instruction ranges in the User Instruction Group (UIG): Opcode Range Group ------------- ----- 105000-105377 UIG-0 101400-101777 UIG-1 105400-105777 UIG-1 The HP 2100 provides only the UIG-0 range, while the 1000 M/E/F-Series provides both ranges. The instructions in UIG-1 dispatch to the same microcode locations independent of bit 11. Bit 11 is the A/B-register select bit, which may be used, e.g., as in the XLA (101724) and XLB (105724) instructions. If bit 11 is not used to distinguish between instructions, then both the 105xxx and 101xxx forms of a given instruction will invoke the same microcode, although the 105xxx form is always canonical. UIG Instructions IR 7-4 Option Name 2100 1000-M 1000-E 1000-F --- ------------- ------ -------------------------- ------ ------ ------ ------ 0 105000-105137 00-05 Floating Point opt std std std 0 105000-105362 00-17 2000 I/O Processor opt - - - 0 105200-105237 10-11 Fast FORTRAN Processor opt opt opt std 0 105240-105257 12 RTE-IVA/B Extended Memory - - opt opt 0 105240-105257 12 RTE-6/VM Virtual Memory - - opt opt 0 105300-105317 14 Distributed System - - opt opt 0 105320-105337 15 Double Integer - - opt - 0 105320-105337 15 Scientific Instruction Set - - - std 0 105340-105357 16 RTE-6/VM Operating System - - opt opt 1 10x400-10x437 00-01 2000 I/O Processor - opt opt - 1 10x460-10x477 03 2000 I/O Processor - opt opt - 1 10x460-10x477 03 Vector Instruction Set - - - opt 1 10x520-10x537 05 Distributed System - opt - - 1 10x600-10x617 10 SIGNAL/1000 Instruction Set - - - opt 1 10x700-10x737 14-15 Dynamic Mapping System - opt opt std 1 10x740-10x777 16-17 Extended Instruction Group - std std std -------------------------------------------- Single-Precision Floating Point Instructions -------------------------------------------- Instr. 2100/1000-M/E Description ------ ------------- ----------------------------------- FAD 105000 Single real add FSB 105020 Single real subtract FMP 105040 Single real multiply FDV 105060 Single real divide FIX 105100 Single integer to single real fix FLT 105120 Single real to single integer float Bits 3-0 are not decoded by these instructions, so FAD (e.g.) would be executed by any instruction in the range 105000-105017. 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 0 0 | 0 0 - | - - - | FAD +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | addend address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 0 0 | 0 1 - | - - - | FSB +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | subtrahend address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 0 0 | 1 0 - | - - - | FMP +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | multiplier address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 0 0 | 1 1 - | - - - | FDV +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | divisor address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 0 1 | 0 0 - | - - - | FIX +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 0 1 | 0 1 - | - - - | FLT +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ ------------------------------------- Floating-Point Processor Instructions ------------------------------------- Instr. 1000-F Description ------ ------ -------------------------------------- FAD 105000 Single real add .XADD 105001 Extended real add .TADD 105002 Double real add [EAD] 105003 [5-word add] [tst] 105004 [Floating Point Processor self test] [xpd] 105005 [Expand exponent] [rst] 105006 [Floating Point Processor reset] [stk] 105007 [Process stack of operands] [chk] 105010 [FPP addressing check] .DAD 105014 Double integer add FSB 105020 Single real subtract .XSUB 105021 Extended real subtract .TSUB 105022 Double real subtract [ESB] 105023 [5-word subtract] .DSB 105034 Double integer subtract FMP 105040 Single real multiply .XMPY 105041 Extended real multiply .TMPY 105042 Double real multiply [EMP] 105043 [5-word multiply] .DMP 105054 Double integer multiply FDV 105060 Single real divide .XDIV 105061 Extended real divide .TDIV 105062 Double real divide [EDV] 105063 [5-word divide] .DDI 105074 Double integer divide FIX 105100 Single real to integer fix .XFXS 105101 Extended real to integer fix (.DINT) .TXFS 105102 Double real to integer fix (.TINT) [EFS] 105103 [5-word FIXS] .FIXD 105104 Real to double integer fix .XFXD 105105 Extended real to double integer fix .TFXD 105106 Double real to double integer fix [EFD] 105107 [5-word FIXD] .DSBR 105114 Double integer subtraction (reversed) FLT 105120 Integer to single real float .XFTS 105121 Integer to extended real float (.IDBL) .TFTS 105122 Integer to double real float (.ITBL) [ELS] 105123 [5-word FLTS] .FLTD 105124 Double integer to real float .XFTD 105125 Double integer to extended real float .TFTD 105126 Double integer to double real float [ELD] 105127 [5-word FLTD] .DDIR 105134 Double integer divide (reversed) 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 0 0 | 0 0 0 | 0 0 0 | FAD +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | addend address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 0 0 | 0 0 0 | 0 0 1 | .XADD +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | result address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | augend address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | addend address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 0 0 | 0 0 0 | 0 1 0 | .TADD +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | result address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | augend address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | addend address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 0 0 | 0 0 0 | 0 1 1 | .EADD +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | result address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | augend address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | addend address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 0 0 | 0 0 0 | 1 0 0 | [test] +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ : return location if the firmware is not installed : P+1 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ : return location if the firmware is installed : P+2 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 0 0 | 0 0 1 | 1 0 0 | .DAD +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | addend address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 0 0 | 0 1 0 | 0 0 0 | FSB +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | subtrahend address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 0 0 | 0 1 0 | 0 0 1 | .XSUB +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | result address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | minuend address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | subtrahend address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 0 0 | 0 1 0 | 0 1 0 | .TSUB +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | result address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | minuend address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | subtrahend address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 0 0 | 0 1 0 | 0 1 1 | .ESUB +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | result address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | minuend address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | subtrahend address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 0 0 | 0 1 1 | 1 0 0 | .DSB +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | subtrahend address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 0 0 | 1 0 0 | 0 0 0 | FMP +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | multiplier address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 0 0 | 1 0 0 | 0 0 1 | .XMPY +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | result address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | multiplicand address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | multiplier address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 0 0 | 1 0 0 | 0 1 0 | .TMPY +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | result address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | multiplicand address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | multiplier address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 0 0 | 1 0 0 | 0 1 1 | .EMPY +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | result address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | multiplicand address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | multiplier address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 0 0 | 1 0 1 | 1 0 0 | .DMP +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | multiplier address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 0 0 | 1 1 0 | 0 0 0 | FDV +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | divisor address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 0 0 | 1 1 0 | 0 0 1 | .XDIV +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | result address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | dividend address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | divisor address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 0 0 | 1 1 0 | 0 1 0 | .TDIV +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | result address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | dividend address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | divisor address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 0 0 | 1 1 0 | 0 1 1 | .EDIV +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | result address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | dividend address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | divisor address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 0 0 | 1 1 1 | 1 0 0 | .DDI +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | divisor address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 0 1 | 0 0 0 | 0 0 0 | FIX +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 0 1 | 0 0 0 | 0 0 1 | .XFXS +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | operand address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 0 1 | 0 0 0 | 0 1 0 | .TXFS +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | operand address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 0 1 | 0 0 0 | 0 1 1 | .EXFS +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | operand address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 0 1 | 0 0 0 | 1 0 0 | .FIXD +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 0 1 | 0 0 0 | 1 0 1 | .XFXD +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | operand address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 0 1 | 0 0 0 | 1 1 0 | .TFXD +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | operand address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 0 1 | 0 0 0 | 1 1 1 | .EFXD +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | operand address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 0 1 | 0 0 1 | 1 0 0 | .DSBR +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | minuend address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 0 1 | 0 1 0 | 0 0 0 | FLT +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 0 1 | 0 0 0 | 0 0 0 | .XFTS +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | result address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 0 1 | 0 0 0 | 0 0 0 | .TFTS +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | result address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 0 1 | 0 0 0 | 0 0 0 | .EFTS +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | result address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 0 1 | 0 0 0 | 0 0 0 | .FLTD +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 0 1 | 0 0 0 | 0 0 0 | .XFTD +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | result address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 0 1 | 0 0 0 | 0 0 0 | .TFTD +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | result address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 0 1 | 0 0 0 | 0 0 0 | .EFTD +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | result address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 0 1 | 0 1 1 | 1 0 0 | .DDIR +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | dividend address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ ------------------------------- 2000 I/O Processor Instructions ------------------------------- Instr. 2100 1000-M/E Description ------ ---------- ---------- -------------------------------------------- SAI 105060-117 101400-037 Store A indexed by B (+/- offset in IR<4:0>) LAI 105020-057 105400-037 Load A indexed by B (+/- offset in IR<4:0>) CRC 105150 105460 Generate CRC RESTR 105340 105461 Restore registers from stack READF 105220 105462 Read F register (stack pointer) INS -- 105463 Initialize F register (stack pointer) ENQ 105240 105464 Enqueue PENQ 105257 105465 Priority enqueue DEQ 105260 105466 Dequeue TRSLT 105160 105467 Translate character ILIST 105000 105470 Indirect address list (similar to $SETP) PRFEI 105222 105471 Power fail exit with I/O PRFEX 105223 105472 Power fail exit PRFIO 105221 105473 Power fail I/O SAVE 105362 105474 Save registers to stack MBYTE 105120 105765 Move bytes (MBT) MWORD 105200 105777 Move words (MVW) SBYTE 105300 105764 Store byte (SBT) LBYTE 105320 105763 Load byte (LBT) The SAI and LAI index offsets in IR bits 4-0 are biased by +16, so, e.g., an offset of -16 is represented by bits 4-0 = 00B, an offset of 0 by 20B, and an offset of +15 by 37B. 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 0 0 1 | 1 0 0 | 0 | index offset | SAI +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 1 0 0 | 0 | index offset | LAI +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 1 0 0 | 1 1 0 | 0 0 0 | CRC +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | accumulated CRC value | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 1 0 0 | 1 1 0 | 0 0 1 | RESTR +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 1 0 0 | 1 1 0 | 0 1 0 | READF +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 1 0 0 | 1 1 0 | 0 1 1 | INS +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 1 0 0 | 1 1 0 | 1 0 0 | ENQ +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ : return location if queue was empty : P+1 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ : return location if queue was not empty : P+2 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 1 0 0 | 1 1 0 | 1 0 1 | PENQ +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 1 0 0 | 1 1 0 | 1 1 0 | DEQ +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ : return location if queue was empty : P+1 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ : return location if queue was not empty : P+2 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 1 0 0 | 1 1 0 | 1 1 1 | TRSLT +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | character count value | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 1 0 0 | 1 1 1 | 0 0 0 | ILIST +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | address list address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | count of pointers | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 1 0 0 | 1 1 1 | 0 0 1 | PRFEI +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | I/O instruction | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | flag word value | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | entry address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 1 0 0 | 1 1 1 | 0 1 0 | PRFEX +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | entry address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 1 0 0 | 1 1 1 | 0 1 1 | PRFIO +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | I/O instruction | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | flag word value | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 1 0 0 | 1 1 1 | 1 0 0 | SAVE +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ ---------------------- Fast FORTRAN Processor ---------------------- Instr. 2100 1000-M 1000-E 1000-F Instr. 2100 1000-M 1000-E 1000-F ------ ------ ------ ------ ------ ------ ------ ------ ------ ------ 105200 -- [nop] [nop] [test] 105220 .XFER .XFER .XFER .XFER 105201 DBLE DBLE DBLE DBLE 105221 .GOTO .GOTO .GOTO .GOTO 105202 SNGL SNGL SNGL SNGL 105222 ..MAP ..MAP ..MAP ..MAP 105203 .XMPY .XMPY .XMPY .DNG 105223 .ENTR .ENTR .ENTR .ENTR 105204 .XDIV .XDIV .XDIV .DCO 105224 .ENTP .ENTP .ENTP .ENTP 105205 .DFER .DFER .DFER .DFER 105225 -- .PWR2 .PWR2 .PWR2 105206 -- .XPAK .XPAK .XPAK 105226 -- .FLUN .FLUN .FLUN 105207 -- XADD XADD .BLE 105227 $SETP $SETP $SETP $SETP 105210 -- XSUB XSUB .DIN 105230 -- .PACK .PACK .PACK 105211 -- XMPY XMPY .DDE 105231 -- -- .CFER .CFER 105212 -- XDIV XDIV .DIS 105232 -- -- -- ..FCM 105213 .XADD .XADD .XADD .DDS 105233 -- -- -- ..TCM 105214 .XSUB .XSUB .XSUB .NGL 105234 -- -- -- -- 105215 -- .XCOM .XCOM .XCOM 105235 -- -- -- -- 105216 -- ..DCM ..DCM ..DCM 105236 -- -- -- -- 105217 -- DDINT DDINT DDINT 105237 -- -- -- -- 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 0 0 0 | 0 0 0 | [test] +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ : return location if the firmware is not installed : P+1 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ : return location if the firmware is installed : P+2 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 0 0 0 | 0 0 1 | DBLE +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | return address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | result address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | operand address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 0 0 0 | 0 1 0 | SNGL +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | return address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | operand address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 0 0 0 | 0 1 1 | .XMPY +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | result address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | multiplicand address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | multiplier address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 0 0 0 | 0 1 1 | .DNG +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 0 0 0 | 1 0 0 | .XDIV +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | result address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | dividend address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | divisor address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 0 0 0 | 1 0 0 | .DCO +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | operand address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ : return location if x = y : P+2 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ : return location if x < y : P+3 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ : return location if x > y : P+4 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 0 0 0 | 1 0 1 | .DFER +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | destination address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | source address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 0 0 0 | 1 1 0 | .XPAK +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | operand address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 0 0 0 | 1 1 1 | XADD +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | return address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | result address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | augend address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | addend address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 0 0 0 | 1 1 1 | .BLE +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | return address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | result address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | operand address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 0 0 1 | 0 0 0 | XSUB +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | return address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | result address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | minuend address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | subtrahend address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 0 0 1 | 0 0 0 | .DIN +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 0 0 1 | 0 0 1 | XMPY +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | return address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | result address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | multiplicand address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | multiplier address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 0 0 1 | 0 0 1 | .DDE +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 0 0 1 | 0 1 0 | XDIV +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | return address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | result address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | dividend address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | divisor address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 0 0 1 | 0 1 0 | .DIS +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | operand address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 0 0 1 | 0 1 1 | .XADD +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | result address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | augend address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | addend address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 0 0 1 | 0 1 1 | .DDS +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | operand address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 0 0 1 | 1 0 0 | .XSUB +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | result address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | minuend address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | subtrahend address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 0 0 1 | 1 0 0 | .NGL +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | return address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | operand address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 0 0 1 | 1 0 1 | .XCOM +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | mantissa address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 0 0 1 | 1 1 0 | ..DCM +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | operand address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 0 0 1 | 1 1 1 | DDINT +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | return address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | result address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | operand address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 0 1 0 | 0 0 0 | .XFER +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 0 1 0 | 0 0 1 | .GOTO +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | return address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | index address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | first transfer address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ : ... : +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | last transfer address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 0 1 0 | 0 1 0 | ..MAP +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | base address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | first subscript address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | second subscript address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ : ... : +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | last dimension length address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 0 1 0 | 0 1 1 | .ENTR +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | first parameter address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 0 1 0 | 1 0 0 | .ENTP +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | first parameter address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 0 1 0 | 1 0 1 | .PWR2 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | exponent address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 0 1 0 | 1 1 0 | .FLUN +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 0 1 0 | 1 1 1 | $SETP +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | count address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 0 1 1 | 0 0 0 | .PACK +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | exponent value | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 0 1 1 | 0 0 1 | .CFER +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | destination address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | source address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 0 1 1 | 0 1 0 | ..FCM +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 0 1 1 | 0 1 1 | ..TCM +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | operand address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ ------------------------- RTE-IVA/B Extended Memory ------------------------- Instr. 1000-E/F Description ------ -------- ---------------------------------------------- .EMIO 105240 EMA I/O MMAP 105241 Map physical to logical memory [test] 105242 [self test] .EMAP 105257 Resolve array element address 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 1 0 0 | 0 0 0 | .EMIO +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | return address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | buffer size address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | array table address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | last subscript address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ : ... : +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | first subscript address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ : return location if error : P+n +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ : return location if buffer is mapped : P+n+1 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 1 0 0 | 0 0 1 | MMAP +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | return address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | relative page count from EMA start to segment start address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | page count address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 1 0 0 | 0 1 0 | [test] +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 1 0 1 | 1 1 1 | .EMAP +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | return address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | array address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | array table address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | last subscript address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ : ... : +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | first subscript address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ : return location if error : P+n +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ : return location if page is mapped : P+n+1 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ ----------------------------------------- RTE-6/VM Virtual Memory Area Instructions ----------------------------------------- Instr. 1000-E/F Description ------ -------- ---------------------------------------------- .PMAP 105240 Map VMA page into map register $LOC 105241 Load on call [test] 105242 [self test] .SWP 105243 [Swap A and B registers] .STAS 105244 [STA B; LDA SP] .LDAS 105245 [LDA SP] .MYAD 105246 [NOP in microcode] .UMPY 105247 [Unsigned multiply and add] .IMAP 105250 Integer element resolve address and map .IMAR 105251 Integer element resolve address .JMAP 105252 Double integer element resolve address and map .JMAR 105253 Double integer element resolve address .LPXR 105254 Map pointer in P+1 plus offset in P+2 .LPX 105255 Map pointer in A/B plus offset in P+1 .LBPR 105256 Map pointer in P+1 .LBP 105257 Map pointer in A/B registers 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 1 0 0 | 0 0 0 | .PMAP +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ : return location if error : P+1 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ : return location if page is mapped : P+2 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 1 0 0 | 0 0 1 | $LOC +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | logical starting page of node | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | relative page from partition start to node start | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | relative page from partition start to base page | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | current path word address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | leaf node number | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | ordinal number | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 1 0 0 | 0 1 0 | [test] +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ : return location if the firmware is not installed : P+1 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ : return location if the firmware is installed : P+2 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 1 0 0 | 0 1 1 | [.swp] +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 1 0 0 | 1 0 0 | [.stas] +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 1 0 0 | 1 0 1 | [.ldas] +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 1 0 0 | 1 1 1 | [.umpy] +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | multiplier address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 1 0 1 | 0 0 0 | .IMAP +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | array table address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | last subscript address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ : ... : +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | first subscript address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 1 0 1 | 0 0 1 | .IMAR +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | address of array table address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 1 0 1 | 0 1 0 | .JMAP +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | array table address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | last subscript address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ : ... : +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | first subscript address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 1 0 1 | 0 1 1 | .JMAR +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | address of array table address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 1 0 1 | 1 0 0 | .LPXR +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | pointer address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | offset address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 1 0 1 | 1 0 1 | .LPX +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | offset address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 1 0 1 | 1 0 0 | .LBPR +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | pointer address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 0 | 1 0 1 | 1 1 1 | .LBP +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ --------------------------- Double Integer Instructions --------------------------- Instr. 1000-E 1000-F Description ------ ------ ------ ----------------------------------------- [test] 105320 -- [self test] .DAD 105321 105014 Double integer add .DMP 105322 105054 Double integer multiply .DNG 105323 105203 Double integer negate .DCO 105324 105204 Double integer compare .DDI 105325 105074 Double integer divide .DDIR 105326 105134 Double integer divide (reversed) .DSB 105327 105034 Double integer subtract .DIN 105330 105210 Double integer increment .DDE 105331 105211 Double integer decrement .DIS 105332 105212 Double integer increment and skip if zero .DDS 105333 105213 Double integer decrement and skip if zero .DSBR 105334 105114 Double integer subtraction (reversed) 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 1 | 0 1 0 | 0 0 0 | test +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ : return location if the firmware is not installed : P+1 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ : return location if the firmware is installed : P+2 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 1 | 0 1 0 | 0 0 1 | .DAD +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | addend address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 1 | 0 1 0 | 0 1 0 | .DMP +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | multiplier address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 1 | 0 1 0 | 0 1 1 | .DNG +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 1 | 0 1 0 | 1 0 0 | .DCO +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | operand address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ : return location if x = y : P+2 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ : return location if x < y : P+3 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ : return location if x > y : P+4 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 1 | 0 1 0 | 1 0 1 | .DDI +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | divisor address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 1 | 0 1 0 | 1 1 0 | .DDIR +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | dividend address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 1 | 0 1 0 | 1 1 1 | .DSB +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | subtrahend address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 1 | 0 1 1 | 0 0 0 | .DIN +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 1 | 0 1 1 | 0 0 1 | .DDE +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 1 | 0 1 1 | 0 1 0 | .DIS +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | operand address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 1 | 0 1 1 | 0 1 1 | .DDS +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | operand address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 1 | 0 1 1 | 1 0 0 | .DSBR +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | minuend address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ -------------------------- Scientific Instruction Set -------------------------- Instr. 1000-F Description ------ ------ ---------------------------------------------- TAN 105320 Tangent SQRT 105321 Square root ALOG 105322 Natural logarithm ATAN 105323 Arc tangent COS 105324 Cosine SIN 105325 Sine EXP 105326 E to the power X ALOGT 105327 Common logarithm TANH 105330 Hyperbolic tangent DPOLY 105331 Double-precision polynomial evaluation /CMRT 105332 Double-precision common range reduction /ATLG 105333 Compute (1-x)/(1+x) for .ATAN and .LOG .FPWR 105334 Single-precision exponentiation .TPWR 105335 Double-precision exponentiation [tst] 105337 [self test] 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 1 | 0 1 0 | 0 0 0 | TAN +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ : return location if error : P+1 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ : return location if operand in range : P+2 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 1 | 0 1 0 | 0 0 1 | SQRT +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ : return location if error : P+1 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ : return location if operand in range : P+2 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 1 | 0 1 0 | 0 1 0 | ALOG +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ : return location if error : P+1 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ : return location if operand in range : P+2 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 1 | 0 1 0 | 0 1 1 | ATAN +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 1 | 0 1 0 | 1 0 0 | COS +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ : return location if error : P+1 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ : return location if operand in range : P+2 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 1 | 0 1 0 | 1 0 1 | SIN +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ : return location if error : P+1 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ : return location if operand in range : P+2 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 1 | 0 1 0 | 1 1 0 | EXP +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ : return location if error : P+1 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ : return location if operand in range : P+2 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 1 | 0 1 0 | 1 1 1 | ALOGT +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ : return location if error : P+1 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ : return location if operand in range : P+2 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 1 | 0 1 1 | 0 0 0 | TANH +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 1 | 0 1 1 | 0 0 1 | DPOLY +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | F | S | - - - - - - - - - - - - - | T | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | result address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | argument address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | coefficient address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | numerator order address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | denominator order address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 1 | 0 1 1 | 0 1 0 | /CMRT +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | result address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | constant address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | argument address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 1 | 0 1 1 | 0 1 1 | /ATLG +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | operand address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 1 | 0 1 1 | 1 0 0 | .FPWR +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | base address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 1 | 0 1 1 | 1 0 1 | .TPWR +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | result address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | base address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 1 | 0 1 1 | 1 1 1 | test +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ -------------------------------------- RTE-6/VM Operating System Instructions -------------------------------------- Instr. 1000-E/F Description ------ -------- ---------------------------------------------- $LIBR 105340 Enter privileged/reentrant library routine $LIBX 105341 Exit privileged/reentrant library routine .TICK 105342 TBG tick interrupt handler .TNAM 105343 Find ID segment that matches name .STIO 105344 Configure I/O instructions .FNW 105345 Find word with user increment .IRT 105346 Interrupt return processing .LLS 105347 Linked list search .SIP 105350 Skip if interrupt pending .YLD 105351 .SIP completion return point .CPM 105352 Compare words LT/EQ/GT .ETEQ 105353 Set up EQT pointers in base page .ENTN 105354 Transfer parameter addresses (utility) $OTST * 105355 OS firmware self test .ENTC 105356 Transfer parameter addresses (priv/reent) .DSPI 105357 Set display indicator Opcodes 105354-105357 are "dual use" instructions that take different actions, depending on whether they are executed from a trap cell during an interrupt. When executed from a trap cell, they have these actions: Instr. 1000-E/F Description ------ -------- ---------------------------------------------- $DCPC * 105354 DCPC channel interrupt processing $MPV * 105355 MP/DMS/PE interrupt processing $DEV * 105356 Standard device interrupt processing $TBG * 105357 TBG interrupt processing 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 1 | 1 0 0 | 0 0 0 | $LIBR +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | address of the Temporary Data Block or zero | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 1 | 1 0 0 | 0 0 1 | $LIBX +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | address of the subroutine entry point | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 1 | 1 0 0 | 0 1 0 | .TICK +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ : return location if an EQT timed out : P+1 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ : return location if an EQT did not time out : P+2 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 1 | 1 0 0 | 0 1 1 | .TNAM +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ : return location if name is not found : P+1 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ : return location if name is found : P+2 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 1 | 1 0 0 | 1 0 0 | .STIO +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | return address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | first I/O instruction address to configure | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ : ... : +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | last I/O instruction address to configure | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 1 | 1 0 0 | 1 0 1 | .FNW +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | increment address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ : return location if word is not found : P+2 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ : return location if word is found : P+3 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 1 | 1 0 0 | 1 1 0 | .IRT +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | P-register restore address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 1 | 1 0 0 | 1 1 1 | .LLS +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | address of the search value | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | address of the offset to the search key | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ : return location if the linked list is in error : P+3 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ : return location if the search value is not found : P+4 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ : return location if the search value is found : P+5 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 1 | 1 0 1 | 0 0 0 | .SIP +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ : return location if no interrupt is pending : P+1 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ : return location if interrupt is pending : P+2 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 1 | 1 0 1 | 0 0 1 | .YLD +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | point of resumption after interrupt | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 1 | 1 0 1 | 0 1 0 | .CPM +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | first argument address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | second adgument address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ : return location if argument 1 = argument 2 : P+3 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ : return location if argument 1 < argument 2 : P+4 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ : return location if argument 1 > argument 2 : P+5 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 1 | 1 0 1 | 0 1 1 | .ETEQ +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 1 | 1 0 1 | 1 0 0 | .ENTN +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | parameter block address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 1 | 1 0 1 | 1 0 1 | test +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ : return location if the firmware is not installed : P+1 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ : return location if the firmware is installed : P+2 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 1 | 1 0 1 | 1 1 0 | .ENTC +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | parameter block address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 1 | 1 0 1 | 1 1 1 | .DSPI +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Opcodes 105354-105357 are "dual use" instructions that take different actions, depending on whether they are executed from a trap cell during an interrupt. When executed from a trap cell, they have these encodings: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 1 | 1 0 1 | 1 0 0 | $DCPC +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 1 | 1 0 1 | 1 0 1 | $MPV +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 1 | 1 0 1 | 1 1 0 | $DEV +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 0 1 1 | 1 0 1 | 1 1 1 | $TBG +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ ---------------------- Vector Instruction Set ---------------------- Single-Precision Double-Precision Instr. Opcode Subcod Instr. Opcode Subcod Description ------ ------ ------ ------ ------ ------ ----------------------------- VADD 101460 000000 DVADD 105460 004002 Vector add VSUB 101460 000020 DVSUB 105460 004022 Vector subtract VMPY 101460 000040 DVMPY 105460 004042 Vector multiply VDIV 101460 000060 DVDIV 105460 004062 Vector divide VSAD 101460 000400 DVSAD 105460 004402 Scalar-vector add VSSB 101460 000420 DVSSB 105460 004422 Scalar-vector subtract VSMY 101460 000440 DVSMY 105460 004442 Scalar-vector multiply VSDV 101460 000460 DVSDV 105460 004462 Scalar-vector divide VPIV 101461 0xxxxx DVPIV 105461 0xxxxx Vector pivot VABS 101462 0xxxxx DVABS 105462 0xxxxx Vector absolute value VSUM 101463 0xxxxx DVSUM 105463 0xxxxx Vector sum VNRM 101464 0xxxxx DVNRM 105464 0xxxxx Vector norm VDOT 101465 0xxxxx DVDOT 105465 0xxxxx Vector dot product VMAX 101466 0xxxxx DVMAX 105466 0xxxxx Vector maximum value VMAB 101467 0xxxxx DVMAB 105467 0xxxxx Vector maximum absolute value VMIN 101470 0xxxxx DVMIN 105470 0xxxxx Vector minimum value VMIB 101471 0xxxxx DVMIB 105471 0xxxxx Vector minimum absolute value VMOV 101472 0xxxxx DVMOV 105472 0xxxxx Vector move VSWP 101473 0xxxxx DVSWP 105473 0xxxxx Vector swap .ERES 101474 -- -- -- -- Resolve array element address .ESEG 101475 -- .VPRG 105475 -- Load MSEG maps .VSET 101476 -- -- -- -- Vector setup -- -- -- [test] 105477 -- [self test] Execution sets bit 15 of the second word to 1 to indicate that the instruction has been interrupted. This allows the instruction to resume at the correct point in the vector operation. Bit 15 is set to 0 before exiting for instruction completion. The .ESEG instruction behaves slightly differently when invoked with the 105475 opcode. The microcode source calls it a .VPRG instruction, but the only difference is that it sets the MSEG start and size to 0 and 32, respectively, instead of obtaining them from the ID extension. In all other respects, the instructions are identical. The .ERES, .VSET, and test instructions do not test bit 11, so they will be invoked with either the 101xxx or 105xxx forms. The 101xxx forms are canonical for the first two, while the 105xxx form is canonical for the self-test instruction. 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | P | 0 1 | 1 0 0 | 1 1 0 | 0 0 0 | (D)VADD +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 0 0 0 | P | 0 0 | 0 0 0 | 0 0 0 | 0 | P | 0 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | vector 1 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | increment 1 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | vector 2 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | increment 2 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | vector 3 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | increment 3 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | element count address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | P | 0 1 | 1 0 0 | 1 1 0 | 0 0 0 | (D)VSUB +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 0 0 0 | P | 0 0 | 0 0 0 | 0 1 0 | 0 | P | 0 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | vector 1 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | increment 1 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | vector 2 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | increment 2 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | vector 3 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | increment 3 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | element count address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | P | 0 1 | 1 0 0 | 1 1 0 | 0 0 0 | (D)VMPY +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 0 0 0 | P | 0 0 | 0 0 0 | 1 0 0 | 0 | P | 0 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | vector 1 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | increment 1 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | vector 2 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | increment 2 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | vector 3 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | increment 3 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | element count address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | P | 0 1 | 1 0 0 | 1 1 0 | 0 0 0 | (D)VDIV +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 0 0 0 | P | 0 0 | 0 0 0 | 1 1 0 | 0 | P | 0 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | vector 1 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | increment 1 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | vector 2 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | increment 2 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | vector 3 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | increment 3 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | element count address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | P | 0 1 | 1 0 0 | 1 1 0 | 0 0 0 | (D)VSAD +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 0 0 0 | P | 0 0 | 1 0 0 | 0 0 0 | 0 | P | 0 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | scalar address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | vector 1 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | increment 1 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | vector 2 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | increment 2 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | element count address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | P | 0 1 | 1 0 0 | 1 1 0 | 0 0 0 | (D)VSSB +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 0 0 0 | P | 0 0 | 1 0 0 | 0 1 0 | 0 | P | 0 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | scalar address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | vector 1 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | increment 1 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | vector 2 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | increment 2 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | element count address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | P | 0 1 | 1 0 0 | 1 1 0 | 0 0 0 | (D)VSMY +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 0 0 0 | P | 0 0 | 1 0 0 | 1 0 0 | 0 | P | 0 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | scalar address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | vector 1 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | increment 1 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | vector 2 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | increment 2 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | element count address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | P | 0 1 | 1 0 0 | 1 1 0 | 0 0 0 | (D)VSDV +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 0 0 0 | P | 0 0 | 1 0 0 | 1 1 0 | 0 | P | 0 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | scalar address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | vector 1 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | increment 1 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | vector 2 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | increment 2 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | element count address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | P | 0 1 | 1 0 0 | 1 1 0 | 0 0 1 | (D)VPIV +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | - - - - - - - - - - - - - - - | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | scalar address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | vector 1 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | increment 1 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | vector 2 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | increment 2 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | vector 3 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | increment 3 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | element count address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | P | 0 1 | 1 0 0 | 1 1 0 | 0 1 0 | (D)VABS +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | - - - - - - - - - - - - - - - | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | vector 1 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | increment 1 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | vector 2 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | increment 2 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | element count address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | P | 0 1 | 1 0 0 | 1 1 0 | 0 1 1 | (D)VSUM +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | - - - - - - - - - - - - - - - | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | scalar address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | vector 1 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | increment 1 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | element count address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | P | 0 1 | 1 0 0 | 1 1 0 | 1 0 0 | (D)VNRM +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | - - - - - - - - - - - - - - - | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | scalar address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | vector 1 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | increment 1 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | element count address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | P | 0 1 | 1 0 0 | 1 1 0 | 1 0 1 | (D)VDOT +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | - - - - - - - - - - - - - - - | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | scalar address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | vector 1 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | increment 1 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | vector 2 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | increment 2 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | element count address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | P | 0 1 | 1 0 0 | 1 1 0 | 1 1 0 | (D)VMAX +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | - - - - - - - - - - - - - - - | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | result address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | vector 1 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | increment 1 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | element count address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | P | 0 1 | 1 0 0 | 1 1 0 | 1 1 1 | (D)VMAB +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | - - - - - - - - - - - - - - - | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | result address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | vector 1 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | increment 1 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | element count address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | P | 0 1 | 1 0 0 | 1 1 1 | 0 0 0 | (D)VMIN +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | - - - - - - - - - - - - - - - | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | result address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | vector 1 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | increment 1 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | element count address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | P | 0 1 | 1 0 0 | 1 1 1 | 0 0 1 | (D)VMIB +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | - - - - - - - - - - - - - - - | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | result address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | vector 1 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | increment 1 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | element count address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | P | 0 1 | 1 0 0 | 1 1 1 | 0 1 0 | (D)VMOV +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | - - - - - - - - - - - - - - - | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | vector 1 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | increment 1 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | vector 2 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | increment 2 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | element count address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | P | 0 1 | 1 0 0 | 1 1 1 | 0 1 1 | (D)VSWP +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | - - - - - - - - - - - - - - - | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | vector 1 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | increment 1 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | vector 2 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | increment 2 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | element count address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 0 0 1 | 1 0 0 | 1 1 1 | 1 0 0 | .ERES +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | return address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | array address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | array table address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | last subscript address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ : ... : +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | first subscript address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ : return location if error : P+n +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ : return location if page is mapped : P+n+1 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 0 0 1 | 1 0 0 | 1 1 1 | 1 0 1 | .ESEG +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | return address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | array table address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ : return location if error : P+3 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ : return location if page is mapped : P+4 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 0 0 1 | 1 0 0 | 1 1 1 | 1 1 0 | .VSET +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | return address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | input vector address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | output vector address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | map table address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | scalar count | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | vector count | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | elements per page count | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ : return location if error : P+8 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ : return location if setup is hard : P+9 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ : return location if setup is easy : P+10 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 1 0 0 | 1 1 1 | 1 1 1 | test +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ : return location if the firmware is not installed : P+1 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ : return location if the firmware is installed : P+2 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ --------------------------- SIGNAL/1000 Instruction Set --------------------------- Instr. 1000-F Description ------ ------ ---------------------------------------------- BITRV 105600 Bit reversal BTRFY 105601 Butterfly algorithm UNSCR 105602 Unscramble for phasor MPY PRSCR 105603 Unscramble for phasor MPY BITR1 105604 Swap two elements in array (alternate format) BTRF1 105605 Butterfly algorithm (alternate format) .CADD 105606 Complex number addition .CSUB 105607 Complex number subtraction .CMPY 105610 Complex number multiplication .CDIV 105611 Complex number division CONJG 105612 Complex conjugate ..CCM 105613 Complex complement AIMAG 105614 Return imaginary part CMPLX 105615 Form complex number [nop] 105616 [no operation] [test] 105617 [self test] 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 1 1 0 | 0 0 0 | 0 0 0 | BITRV +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | return address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | array base address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | index bitmap address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | count of index bits address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 1 1 0 | 0 0 0 | 0 0 1 | BTRFY +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | return address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | complex vector address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | real part address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | imaginary part address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | node address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | maximum length address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 1 1 0 | 0 0 0 | 0 1 0 | UNSCR +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | return address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | vector address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | real part address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | imaginary part address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | index 1 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | index 2 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 1 1 0 | 0 0 0 | 0 1 1 | PRSCR +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | return address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | vector address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | real part address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | imaginary part address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | index 1 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | index 2 address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 1 1 0 | 0 0 0 | 1 0 0 | BITR1 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | return address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | real array base address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | imaginary array base address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | index bitmap address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | count of index bits address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 1 1 0 | 0 0 0 | 1 0 1 | BTRF1 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | return address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | real vector part address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | imaginary vector part address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | real part address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | imaginary part address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | node address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | maximum length address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 1 1 0 | 0 0 0 | 1 1 0 | .CADD +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | result address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | augend address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | addend address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 1 1 0 | 0 0 0 | 1 1 1 | .CSUB +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | result address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | minuend address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | subtrahend address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 1 1 0 | 0 0 1 | 0 0 0 | .CMPY +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | result address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | multiplicand address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | multiplier address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 1 1 0 | 0 0 1 | 0 0 1 | .CDIV +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | result address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | dividend address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | divisor address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 1 1 0 | 0 0 1 | 0 1 0 | CONJG +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | return address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | result address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | argument address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 1 1 0 | 0 0 1 | 0 1 1 | ..CCM +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | argument address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 1 1 0 | 0 0 1 | 1 0 0 | AIMAG +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | return address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | operand address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 1 1 0 | 0 0 1 | 1 0 1 | CMPLX +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | return address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | result address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | real part address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | imaginary part address | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | 1 0 1 | 1 1 0 | 0 0 1 | 1 1 1 | test +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ : return location if the firmware is not installed : P+1 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+ : return location if the firmware is installed : P+2 +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -+