HP 21xx/1000 Hardware Notes =========================== The HP21xx/1000 family consists of the 2114, 2115, 2116, 2100, 1000-M, 1000-E, and 1000-F processors. ----------------- Central Processor ----------------- Service notes (per CE Handbook): - 2109E-01 HP 1000 E/F-Series computer's RUN light remains on when computer is halted. - 2111F-10 HP 1000 E/F-Series computer's RUN light remains on when computer is halted. - 2113E-01 HP 1000 E/F-Series computer's RUN light remains on when computer is halted. - 2117F-14 HP 1000 E/F-Series computer's RUN light remains on when computer is halted. Instruction set decoding is partly dependent on the CPU model. These firmware extensions deliver varying instructions: - IOP 2100 vs. 1000-M/E UNIT_TYPE_2100 vs. UNIT_TYPE_1000 - FP 2100 and 1000-M/E vs. FFP 1000-F not UNIT_1000_F vs. UNIT_1000_F - FFP 2100 vs. 1000-F vs. 1000-E vs 1000-M UNIT_2100 vs. UNIT_1000_F vs. UNIT_1000_E vs. other ? - DBI 1000-E vs. 1000-F UNIT_1000_E vs. UNIT_1000_F - EAU 2116 and 2100 and 1000-M vs. 1000-E/F UNIT_TYPE_21XX ? In addition, the mapping of the reserved bits to EAU instructions depends on the model. Instruction set decoding: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | I | mem op | P | memory address | MRG +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | I | mem op | R | P | memory address | MRG +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: I = direct/indirect (0/1) R = A/B register (0/1) P = base/current page (0/1) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 0 0 0 | R | 0 | E | op 1 | C | E | S | op 2 | SRG +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: R = A/B register (0/1) E = disable/enable op C = CLE S = SL* 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 0 0 0 | R | 1 | r op | e op | E | S | L | I | Z | V | ASG +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: R = A/B register (0/1) E = SEZ S = SS* L = SL* I = IN* Z = SZ* V = RSS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | R | 1 | H | i/o op | select code | IOG +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: R = A/B register (0/1) H = hold/clear flag (0/1) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | | 0 | eau op | 0 0 0 0 0 0 | EAU +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | | 0 | eau shift/rotate op | shift count | EAU +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ MAC ops decode when bits 15-12 and 10 are 1 000 0. Bits 11 and 9-0 determine the specific EAU instruction. The 2116 EAU performs the following decoding in hardware: - MPY : ~11 * 7 - DIV : ~11 * 8 - DLD : 11 * 7 - DST : 11 * 8 - ASR : ~11 * 9 * 4 * (3-0) - ASL : ~11 * ~9 * 4 * (3-0) - LSR : ~11 * 9 * 5 * (3-0) - LSL : ~11 * ~9 * 5 * (3-0) - RRR : ~11 * 9 * 6 * (3-0) - RRL : ~11 * ~9 * 6 * (3-0) 2100 EAU decoding: - MPY (RAR 210) : ~11 * ~9 * ~8 * 7 * ~6 * ~5 * ~4 - DIV (RAR 220) : ~11 * ~9 * 8 * ~7 * ~6 * ~5 * ~4 - DLD (RAR 310) : 11 * ~9 * ~8 * 7 * ~6 * ~5 * ~4 - DST (RAR 320) : 11 * ~9 * 8 * ~7 * ~6 * ~5 * ~4 - ASR (RAR 241) : ~11 * 9 * ~8 * ~7 * ~6 * ~5 * 4 - ASL (RAR 201) : ~11 * ~9 * ~8 * ~7 * ~6 * ~5 * 4 - LSR (RAR 242) : ~11 * 9 * ~8 * ~7 * ~6 * 5 * ~4 - LSL (RAR 202) : ~11 * ~9 * ~8 * ~7 * ~6 * 5 * ~4 - RRR (RAR 244) : ~11 * 9 * ~8 * ~7 * 6 * ~5 * ~4 - RRL (RAR 204) : ~11 * ~9 * ~8 * ~7 * 6 * ~5 * ~4 The 2100 microcode uses a "legal entry point" (LEP) micro-order to validate EAU ROM jumps. An invalid jump address executes microcode NOPs until either a LEP or EOP ("end of phase") micro-order is encountered. This means that while a different instruction may execute, the micromachine will not hang or execute improperly. An example is seen in the microcode for ASL (10002x), LSL (10004x), and RRL (10010x). The ROM Address Mapper, a set of discrete logic gates located on ROM Control card A2, maps these three instructions to ROM addresses 201, 202, and 204, respectively. The microcode is: 201 ASL: - - IOR - LEP - 202 LSL: F - JMP S3 ALSA - 203 - - IOR - LEP - 204 RRL: F - JMP S3 LLSA - 205 - - IOR - LEP - 206 F - JMP S3 RRLA - Note that LSL and RRL execution begins with effective NOP instructions, because the branches are NOT to instructions containing LEP. A test using this feature is mentioned in the Communicator/1000 for November 1977. The E/F-Series TIMER instruction (100060) is mapped to ROM address 203, which then executes the same as the LSL instruction, except for being slightly faster! The 1000s decode EAU instructions in firmware. The initial branch is based on bits 15-8 being 200, 201, 202, 210, or 211 octal. For the E-Series, the 200 and 202 cases then branch based on bits 7-4. However, the branch tables are only partially populated. Instructions 100120-100177 execute as NOP, 100201-100377 cause erroneous execution. 101000-101017 seem to execute the instruction in the A register via the HORI microcode routine. 101060-101077 execute as NOP. 101120-101377 cause erroneous execution. For the F-Series, 100120-100137 execute as NOP. 100140-100157 set S1 to P-1, 100160-100177 decrement S3, and 101060-101077 increment S3; all three are effectively NOPs during execution, as they are used by the halt-mode microcode. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | 0 0 0 | R | 0 1 | module | operation | UIG +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: R = A/B register (0/1) ----------- Front Panel ----------- 2116 and 2115: PRESET (lights for power fail) RUN (lights in run state) HALT (lights in halt state) LOAD MEMORY LOAD A LOAD B LOAD ADDRESS DISPLAY MEMORY SINGLE CYCLE SWITCH REGISTER (toggle) LOADER (toggle) T REGISTER (display) P REGISTER (display) M REGISTER (display) A REGISTER (display) B REGISTER (display) EXTEND (light) OVERFLOW (light) FETCH (light) INDIRECT (light) EXECUTE (light) PARITY HALT (light) 2114: MEMORY DATA (display) MEMORY ADDRESS (display) SWITCH REGISTER (and display register) PRESET RUN (lights in run state) HALT (lights in halt state) LOAD (loader) LOAD MEMORY LOAD ADDRESS DISPLAY MEMORY SINGLE CYCLE CLEAR REGISTER FETCH (light) INDIRECT (light) EXECUTE (light) OVERFLOW (light) EXTEND (light) PARITY (light) 2100: Display/Switch Register LOADER ENABLE INTERNAL PRESET EXTERNAL PRESET FETCH IND EXECUTE PARITY RUN HALT/CYCLE INSTR STEP INTERRUPT SYSTEM CLEAR DISPLAY A B M MEMORY DATA S P EXTEND OVF INCREMENT M DECREMENT M 1000 M: OVERFLOW EXTEND DISPLAY REGISTER SWITCH REGISTER RUN (button and light) HALT PRESET IBL INTERRUPT SYSTEM PARITY POWER FAIL A B M T P S < > INSTR STEP CLEAR DISPLAY INC M DEC M STORE DISPLAY 1000 E and F: OVERFLOW EXTEND DISPLAY REGISTER SWITCH REGISTER RUN (button and light) HALT PRESET IBL/TEST INTERRUPT SYSTEM PARITY POWER FAIL A/x B/y M/m T/t P/f S/s < > INSTR STEP CLEAR DISPLAY INC M/m DEC M/m STORE MODE ------------- I/O Backplane ------------- Input signals (from CPU to interface): CLC - clear the control flip-flop STC - set the control flip-flop CLF - clear the flag flip-flop STF - set the flag flip-flop SFC - skip if the flag is clear SFS - skip if the flag is set IOI - I/O data input IOO - I/O data output EDT - end of data transfer ENF - (periodic) enable flag SIR - (periodic) set interrupt request IAK - interrupt acknowledge PRH - priority high CRS - control reset POPIO - power-on preset to I/O PON - power on normal SCL* - select code least-significant digit SCM* - select code most-significant digit IOG - I/O group instruction IEN - interrupt system enable RUN - run flip-flop IOBI0-15 - I/O bus input IOG * SCM * SCL qualify all I/O signals. Output signals (from interface to CPU): PRL - priority low IRQ* - interrupt request FLG* - flag SRQ - service request SKF - skip on flag IOBO0-15 - I/O bus output _______________________ PRL = PRH * (IEN * CNTL FF * FLAG FF) IRQ and FLG are driven together. For the 2100 and 1000, the INTSYS FF drives both IEN5-up and PRH6-up. With the interrupt system off, PRH is denied to all interfaces, so ANDING PRH and IEN for interrupt qualification seems to be redundant. IEN10 and PRH10 are the same signal (connected on the CPU PCA). IEN20 and PRH20 are the same signal (connected on the I/O backplane). ____ IEN10 = PRL7 * FLG5 * PRH5 * INTSYS FF. ____ IEN20 = PRL17 * FLG5 * IEN10 * INTSYS FF. IEN5 = INTSYS FF. For the 2116, the situation is more complicated (see page 3-4 of 02116-91757). The INTSYSEN FF drives IEN6 (which is also IEN5) and is ANDed with PRH10 to drive IEN10. PRH10 is PRL7 and is unaffected by INTSYSEN. PRL17 is ANDed with PRH10 and IEN6 to drive PRH20 and IEN20. So with the interrupt system off, IEN is denied to all interfaces, PRH10-PRH17 are unaffected, but PRH20 and up are denied. For the 2114, PRL4, PRL5, and PRL6 are ANDed to drive PRH10. The INTEN FF drives IEN10-17. With the interrupt system off, the system bahaves as the 2116 does, i.e., IEN is denied, and PRH10-17 are unaffected. ------------ Boot Loaders ------------ DMA FWA Loader BOOT Offset Offset Applies to ------ ---- ------ ------ -------------------------------- 12992A DPC 76 77 7900/7901/2883 Disc 12992B DS 76 77 7905/7906/7920/7925 Disc 12992C BACI -- 77 2644/2645/2648 Cartridge Tape 12992D MS -- -- 7970B/E Magnetic Tape 12992E -- -- -- 9885 Floppy Disk 12992F DPC 76 77 7900/7901 Disc 12992H DA 76 77 7906H/7920H/7925H/9895 ICD 12992J -- 76 77 CS/80 Disc 12992K PTR -- 77 2748 Paper Tape Reader 12992L MA -- -- 7974 Magnetic Tape BBL PTR -- 72 2748 Paper Tape Reader BBDL DRC 56 55 277x Fixed-Head Disc/Drum BMDL DPC 77 34 2870 Disc BMDL DQC 76 77 2883 Disc BMDL DPC 77 34 7900/7901 Disc BMDL DS 76 34 7905 Disc PIK IPL -- 73 12875 Processor Interconnect Kit BCTL BACI -- 77 2644 Cartridge Tape BMTL MS -- -- 7970B/E Magnetic Tape BOOT 21xx 1000 Applies to ---- ------ ------ -------------------------------- DA -- 12992H 7906H/7920H/7925H/9895 ICD DPC BMDL 12992F 7900/7901 Disc DPC BMDL Note 2870 Disc DQC BMDL 12992A 2883/7900/7901 Disc DRC BBDL -- 277x Fixed-Head Disc/Drum DS BMDL 12992B 7905/7906/7920/7925 Disc IPL IOP 12992K 12875 Processor Interconnect Kit MS BMTL 12992D 7970B/E Magnetic Tape PTR BBL 12992K 2748 Paper Tape Reader Note: The Loader Loader uses the same BMDL for the 7900 and 2870 discs, which implies that the 12992F loader ROM will work for both as well. 2100 Boot Loaders ~~~~~~~~~~~~~~~~~ BBL (PTR) S-Register format: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | C | - - - - - - - - - - - - - - | V | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: C = Compare the paper tape to memory V = Verify checksums on the paper tape If neither bit 15 nor 0 is set, the BBL reads the paper tape into memory. The loader starting address is x7700. The tape format must be absolute binary. Loader execution ends with one of the following instructions: HLT 00B - comparison error (A = tape value) HLT 11B - checksum error (A = tape value, B = calculated value) HLT 55B - load address >= ROM loader address HLT 77B - end of tape with successful read BMDL (DPC, PTR) S-Register format: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - - - - - - - - - - - - - - - - | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ The paper tape loader starting address is x7700. The tape format must be absolute binary. Loader execution ends with one of the following instructions: HLT 11B - checksum error (A = tape value, B = calculated value) HLT 55B - load address >= ROM loader address HLT 77B - end of tape with successful read The disc loader starting address is x7750. The word at x7750 specifies the surface containing the operating system. For the 7900, the value 030000 reads from the removable platter (subchannel 1), and the value 031000 reads from the fixed platter (subchannel 0). For the 7901, the value must be 030000. The loader reads 6144 words from cylinder 0 sector 0 of the specified subchannel into memory starting at location 2011 octal. Loader execution ends with the following instruction: JSB 2055B,I - the disc read completed Normal completion status is End of Cylinder and Any Error (000041). BMDL (DQC, PTR) S-Register format: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - - - - - - - - - - - - - - - - | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ The paper tape loader starting address is x7700. The tape format must be absolute binary. Loader execution ends with one of the following instructions: HLT 11B - checksum error (A = tape value, B = calculated value) HLT 55B - load address >= ROM loader address HLT 77B - end of tape with successful read The disc loader starting address is x7750. The loader reads 128 words from cylinder 0 head 0 sector 0 into memory starting at location 2011 octal. Loader execution ends with the following instruction: JMP 2055B,I - the disc read completed Note that the BMDL does a JMP 2055,I and the 12992A does a JSB 2055,I. BBDL (DRC, PTR) S-Register format: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - - - - - - - - - - - - - - - - | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ The paper tape loader starting address is x7700. The tape format must be absolute binary. Loader execution ends with one of the following instructions: HLT 11B - checksum error (A = calculated value, B = tape value) HLT 55B - load address >= ROM loader address HLT 77B - end of tape with successful read The disc loader starting address is x7760. The loader stores a JMP * instruction into location 77 octal and then reads 64 words from track 0 sector 0 into memory starting at location 0. Loader execution ends when the JMP * is overlaid with a JMP to the address of the start of the bootstrap extension just read. BMDL (DS, PTR) S-Register format: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - - - - - - - - - - - - - - | head | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ The paper tape loader starting address is x7700. The tape format must be absolute binary. Loader execution ends with one of the following instructions: HLT 11B - checksum error (A = calculated value, B = tape value) HLT 55B - load address >= ROM loader address HLT 77B - end of tape with successful read The disc loader starting address is x7750. The S register specifies the head to use. The loader stores the value 002055 into location 2055 octal, stores a HLT 11B into location 2056 octal, and then reads 2047 words from cylinder 0 sector 0 of the specified head into memory starting at location 2011 octal. Loader execution ends with one of the following instructions: HLT 11B - the disc read failed JSB 2055B,I - the disc read succeeded Special BBL (IPLI, PTR) S-Register format: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - - - - - - - - - - - - - - - - | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ The processor interconnect cross-loader starting address is x7700. The paper tape loader starting address is x7750. For both devices, the input format must be absolute binary. Loader execution ends with one of the following instructions: HLT 11B - checksum error (A = calculated value, B = tape value) HLT 55B - load address >= ROM loader address HLT 77B - end of input with successful read (A = paper tape select code, B = processor interconnect select code) BMTL (MSC) S-Register format: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - - - - - - - - - - | file number | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ The magnetic tape loader starting address is x7700. The tape format must be absolute binary, and a tape mark must end the file. If S-register bits 5-0 are zero, the file located at the current tape position is read. If the bits are non-zero, the tape is rewound, and the file number (1 - n) specified by the bits is read. Loader execution ends with one of the following instructions: HLT 00B - tape read (parity) error HLT 11B - checksum error (A = calculated value, B = tape value) HLT 77B - end of file with successful read ----------------------- Power Fail/Auto Restart ----------------------- The 1000 power supply provides PON (power on), PWU (power up), and -MLOST (memory lost) signals to the CPU. When main power is first applied, PON and PWU are denied. When AC power is valid, PWU asserts and PON remains denied. When DC power is valid, PON asserts. If -MLOST is low, memory contents are not valid, so the CPU firmware performs a memory clear and does NOT issue a power-restore interrupt. If -MLOST is high, memory is still valid, so the firmware bypasses the memory clear and issues a power-up interrupt if ARS is enabled. When AC power fails, PWU denies and PON remains asserted. This causes a power-fail interrupt if ARS is enabled. After 500 microseconds, PON denies in advance of DC power failure. The CPU halts when PON denies if the power-fail routine has not halted already or ARS is disabled. The CPU tracks power with a four-state machine. The two state flip-flops control the interrupt request and the flag indication (fail or restore) for select code 4. The machine powers up in state 00, and it remains in state 00 if ARS is disabled, inhibiting the power-restore interrupt request. If ARS is enabled, then if the operator is holding the PRESET button down, state 00 transitions to state 01 when PWU and PRHS assert, bypassing the power-restore interrupt request. If the operator is not holding PRESET down, then state 00 transitions to state 11, generating a power-restore interrupt and a run signal (-PWUST). Once IAK4 is received, state 11 transitions to state 01. This is the operational state. When PWU denies, state 01 transitions to state 10, generating the power-fail interrupt. When IAK4 asserts, state 10 transitions to state 00, where it remains until power fades out. With ARS enabled, if the CPU is halted when power fails, the interrupt is still generated. However, it is not serviced because the CPU is not running. When power is restored, the IRQ4 handler is executed. RTE driver DVP43 tests for a power up with no prior power down (i.e., the CPU was halted when power failed) and executes a HLT 04,C within the driver if the condition is true. IA 4-26 2116: 12588A Power Failure Auto-Restart option RESTART/HALT switch on 12588-6001 PF/AR card "at least 1 msec" available before DC power loss 2100: standard equipment 550 usec available before DC power loss 1000: 12944B (2108/2109) or 12991B (2112/2113) Power Fail Recovery System ~ARS/ARS switch on CPU main board 500 usec available before DC power loss ------------------------------------------------------------ 12578A/12607B/12895A DMA Controllers, 12897B DCPC Controller ------------------------------------------------------------ SC 06 Control Word 1 format (OTA and OTB): 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | S | B | C | - - - - - - - | device select code | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: S = assert STC during each cycle B = enable byte packing and unpacking C = assert CLC at the end of the block transfer SC 02 Control Word 2/3 format (OTA and OTB): 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | D | starting memory address | word 2 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | negative word count | word 3 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: D = transfer direction is out of/into memory (0/1) Control word 2 is stored if the control flip-flop is clear, i.e., if the OTA/B is preceded by CLC; control word 3 is stored if the flip-flop is set by a preceding STC. The 12607B supports 14-bit addresses and 13-bit word counts. The 12578A supports 15-bit addresses and 14-bit word counts. The 12895A and 12897B support 15-bit addresses and 16-bit word counts. >>DCPC1 cmd: Channel transfer of 27 words from select code 23 to address 12700 started >>DCPC1 cmd: Channel transfer completed >>DCPC1 cmd: Channel transfer aborted >>DCPC1 csrw: Control word 1 is STC | CLC | select code 23 >>DCPC1 csrw: Control word 2 is input to address 12700 >>DCPC1 csrw: Control word 3 is word count 27 >>DCPC1 csrw: Remaining word count is 13 >>DCPC1 sr: Select code 23 asserted SRQ >>DCPC1 iobus: Received data 000000 with signals IOO ----------------------------- 12845B Line Printer Interface ----------------------------- Printers supported: - 2607A - 2610A - 2614A - 2613A - 2617A - 2618A Output Data Word format (OTA and OTB): 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | - - - - - - - - | ASCII character | character +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | - - - - - - - - | format word | format +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ The printer only uses seven data bits, so the MSB of each byte is ignored. The format commands recognized by the printer are: 0 0 0 0 0 0 0 -- slew 0 lines (suppress spacing) after printing * ... 0 0 0 1 1 1 1 -- slew 15 lines after printing 0 0 1 0 0 0 0 -- slew 16 lines after printing ** ... 0 1 1 1 1 1 1 -- slew 63 lines after printing ** * slew 1 line on the 2607A, which cannot suppress printing. ** available only on the 2610A and 2614A and: 1 x x 0 0 0 0 -- slew to VFU channel 1 after printing ... 1 x x 0 1 1 1 -- slew to VFU channel 8 after printing 1 x x 1 0 0 0 -- slew to VFU channel 9 after printing * ... 1 x x 1 0 1 1 -- slew to VFU channel 12 after printing * * available only on the 2613A, 2617A, and 2618A Input Data Word format (LIA and LIB): 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | L | R | V | U | - - - - - - - - - - - | D | status +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: L = Online R = Not ready V = VFU channel 9 U = VFU channel 12 D = Demand Manual Note: "2-33. PAPER OUT SIGNAL. [...] The signal is asserted only when the format tape in the line printer has reached the bottom of form." 02607-90901 pdfp 64 shows REDY input becomes ONLINE output, and ON input becomes READY output. ON is simply the power-on switch, so READY is asserted whenever the printer is on. 2607 says: - buffer ROM PCA J3-30 (ON) is the power-on switch on the swtich PCA - buffer ROM PCA J3-25 (REDY) asserts when ~PAPEROUT * PRINTSWITCH * ~MFF (form-feed is executing) denies when PAPEROUT * TOF + ~PRINTSWITCH - interface PCA J2-30 (ON) is passed to J7-T/16 (READY) - interface PCA J2-25 (REDY) is passed to J7-S/15 (ONLINE) - interface T/16 (READY) connects to cable r/s - interface S/15 (ONLINE) connects to cable j/h 1000 says: - cable j/h (ONLINE) connects to PCA 26A/B to status bit 15 - cable r/s (~READY) connects to PCA 27A/B to status bit 14 3000 says: - bit 11 (READY) is asserted when power is on - bits 9-10 (ONLINE) are asserted when - power is on - PRINT button is down - paper is installed - platen is closed - no electronic (VFU) fault CRS clears the control FF and (as master clear) clears the printer line buffer. Except for the 2613, it aborts any paper advance in progress. It does not abort a print in progress. POPIO clears the output data register and sets the flag buffer FF and (via ENF) the flag FF. STC sets Control FF unconditionally. STC sets Information Ready FF if ONLINE is asserted, which leads to STROBE asserted; otherwise, STC is ignored. ONLINE is denied if offline or out of paper or gate/platen open. DEMAND asserts when these conditions are removed, so Flag Buffer FF sets. Normal handshake (assuming ONLINE asserted): 1. STROBE denied, DEMAND asserted -> STC, INFRDY sets, STROBE asserts 2. STROBE asserted, DEMAND asserted -> DEMAND denies, Control one-shot fires 3. STROBE asserted, DEMAND denied -> INFRDY resets, STROBE denies 4. STROBE denied, DEMAND denied -> DEMAND asserts, Flag one-shot fires, Flag Buffer FF sets Conditions: STC with power off (140001) : INFRDY sets, STROBE asserts STC with paper out (000000) : INFRDY remains clear, STROBE remains denied STC with printer offline (000000) : INFRDY remains clear, STROBE remains denied power off to power on (140001 -> 100001) : no change? paper out to ready (000000 -> 100001) : DEMAND asserts, Flag one-shot fires, Flag Buffer FF sets printer offline to online (000000 -> 100001) : DEMAND asserts, Flag one-shot fires, Flag Buffer FF sets If Flag FF is clear, DEMAND asserting sets Flag Buffer FF. If Flag FF is already set, DEMAND assertion is ignored. For status, ONLINE and READY are set at point of use, while DEMAND is set in the IOI handler. -------------------------------- Media III Line Printer Interface -------------------------------- Printers supported: - Tally 2000 Output Data Word format (OTA and OTB): 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - - - - - - - - - | ASCII character | character +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ The printer only uses seven data bits, so the MSB of each byte is ignored. There are no format codes. Instead, the interface responds to CR, LF, FF, and VT. CR is ignored. LF causes a print operation and slew to the next line. FF causes a print operation and slew to the top-of-form. VT causes a slew to the VFU channel specified by the three LSBs of the succeeding character. Input Data Word format (LIA and LIB): 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | L | - - - - - - - - - - - | R | S | - | B | status +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: L = Online R = Ready (not out of paper) S = Printer Slewing B = Printer Busy ----------------------------- 12653A Line Printer Interface ----------------------------- Printers supported: - 2767A Differences between the 12653A vs 12566 interfaces: - eliminates the Data flip-flop and the pulsed input register option - different ICs (12653A is older) - jumpers are preinstalled The HP 2767A is a rebadged Data Products model 2310 line printer. It has a 20-character buffer and an 80-column print drum, divided into four "print zones" of 20 characters each. Printing starts with zone 1. When the buffer fills, the last received character causes the buffer to be printed in the current zone before the buffer is cleared and the next character is accepted. Printing by buffer filling increments the zone counter and clears the column counter. The 2767A does not support a VFU or use a print command. Instead, it reacts to three control characters in the output stream. Each control character prints the characters in the current zone, clears the buffer memory, and then: * CR -- resets to zone 1, column 1. * LF -- resets to zone 1, column 1 and advances the paper one line. * FF -- resets to zone 1, column 1 and advances to the top of the next form. Normal lines are terminated with LF to print, reset to zone 1, and advance the paper. Bare LFs can be sent to skip lines. Because all control characters reset to zone 1, there is no way to "stair step" the output with embedded LFs. The printer automatically skips the page perforation by advancing the paper six lines (three before and three after the perf) after the last line is printed on the page. The drum contains a 64-character print set and rotates at 1760 RPM. Slew speed is 13 inches per second. Line advance time is 20 milliseconds, although once moving, additional slewing is continuous is LF characters arrive quickly enough. The printer cable to the interface consists of 7 data lines and a strobe line to the printer, and a ready, online, and demand line from the printer. The character set is the standard upper-case ASCII set but with an up-arrow (U+2191) replacing the caret (^) and a back-arrow (U+2190) replacing the underscore (_). When the printer is READY, ON LINE, and idle, the DEMAND line is asserted. A character is transferred on the data lines by asserting STROBE. In response, DEMAND is denied, the character is transferred to the 20-character buffer, and DEMAND is reasserted. If the character was the 20th, a print cycle is started, and DEMAND remains denied until the cycle is complete and the buffer is cleared. Non-printable characters are erased (i.e., the print as spaces). STROBE may assert as soon as DEMAND asserts. DEMAND denies 1 uS after STROBE assertion. STROBE must then deny within 200 nS to avoid reducing the transfer rate. DEMAND reasserts 1.5 uS later if a print cycle is not started. At power on, there is a 10 second delay to allow the drum to come up to speed before the printer asserts READY. The printer must be set ON LINE manually. Front-panel controls are: * POWER indicator * READY indicator * ON LINE indicator * TOP OF FORM momentary switch * PAPER STEP momentary switch * OFF LINE / ON LINE toggle switch The TOP OF FORM and PAPER STEP switches are disabled when the printer is online. Per SM, p 4-60, para 4-261, the printer cannot be set offline with data in the print buffer. TOF and PAPER STEP are normally inoperative when online. With data in the print buffer, the sequence is: - switch set to OFFLINE - TOF or PAPER STEP toggled - buffer prints, paper advances - printer goes offline (ONLINE indicator goes out) Normal sequence is: - switch set to OFFLINE (ONLINE indicator goes out) - TOF or PAPER STEP toggled - paper advances If STROBE is asserted while the unit is offline, it looks as though it will start the load sequence when it goes online, which asserts DEMAND, which causes STROBE to deny. It's the trailing edge of STROBE that initiates the data load. Output Data Word format (OTA and OTB): 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - - - - - - - - - | ASCII character | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Input Data Word format (LIA and LIB): 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | N | - - - - - - - - - - - - - - | B | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: N = Not Ready B = Busy (~Demand?) Notes: * RTE DVR12 discards characters after 80, suggesting that they'd overprint. The printer self-test option card sends an LF after printing an 80-character test pattern. Also, it can be set to print in zone order 4, 1, 2, 3. So there's no auto-paper-advance after zone 4 prints from a buffer full condition. * DVR12 checks status three instructions after OTx/STC to output character. * DVR12 changes non-printable character to "@" (otherwise prints as blank). -------------------------------------------------- 13181B/13183B Digital Magnetic Tape Unit Interface -------------------------------------------------- Output Data Word format (OTA and OTB): 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - - - | unit select | C | command code | command +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | write data | data +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: C = Change Unit Select Command Codes: 003 = FSR (Forward Space Record) 015 = GAP (Write Gap) 023 = RRF (Read Record Forward) 031 = WCC (Write Record) 041 = BSR (Backspace Record) 101 = REW (Rewind) 105 = RWO (Rewind Offline) 110 = CLR (Clear Controller) 203 = FSF (Forward Space File) 211 = WFM (Write File Mark) 215 = GFM (Write Gap and File Mark) 241 = BSF (Backspace File) Input Data Word format (LIA and LIB): 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - | - | - | - | O | R | U | I | K | L | E | T | R | P | D | F | 13181 status +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | H | unit | S | O | R | U | I | K | L | E | T | R | P | D | F | 13183 status +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | read data | data +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: H = 1600 BPI S = Single Track Error O = Odd Byte Count R = Rewinding U = Tape Unit Busy I = Interface Busy K = Tape Mark (End of File) L = Load Point E = End of Tape T = Timing Error R = Command Rejected P = Write Protected D = Data Error F = Offline Boot Loader ROM S-Register format (12992D): 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | ROM # | 0 0 | select code | 0 0 0 0 0 | F | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: F = Read current/specified file (0/1) If bit 0 is 0, the file located at the current tape position is read. If bit 0 is 1, the tape is rewound, and the file number (1 - n) specified by the A-register content is read. The tape format must be absolute binary, and a tape mark must end the file. Loader execution ends with one of the following instructions: HLT 00B - tape read (parity) error HLT 11B - checksum error (A = calculated, B = expected) HLT 77B - end of file with successful read ------------------------------------------- 12559A 9-Track Magnetic Tape Unit Interface ------------------------------------------- Output Data Word format (OTA and OTB): 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - - - - - - - - | command code | command +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - - - - - - - - | write data | data +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Command Codes: 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+ | W | S | V | X | W | T | F | M | +---+---+---+---+---+---+---+---+ W = Rewind S = Rewind and Standby V = Reverse X = Transfer Data W = Write T = Tape Mark F = Forward M = Motion 003 = FSR (Forward Space Record) = 00 000 011 011 = GAP (Write Gap) = 00 001 001 023 = RC (Read Record) = 00 010 011 031 = WC (Write Record) = 00 011 001 035 = WFM (Write File Mark) = 00 011 101 041 = BSR (Backspace Record) = 00 100 001 101 = RWS (Rewind and Standby) = 01 000 001 201 = REW (Rewind) = 10 000 001 300 = CLR (Clear Controller) = 11 000 000 Input Data Word format (LIA and LIB): 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - - - - - - - | F | K | L | E | T | R | P | D | B | command +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - - - - - - - - | read data | data +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: F = Offline K = Tape Mark (End of File) L = Load Point E = End of Tape T = Timing Error R = Command Rejected P = Write Protected D = Data Error B = Busy -------------------------------- 12597A-002 Tape Reader Interface -------------------------------- Output Data Word format (OTA and OTB): 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - - - - - - - - - - - - - - - - | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ An IOO signal clocks the lower eight bits into the output register, but the output lines are not connected to the tape reader. Input Data Word format (LIA and LIB): 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - - - - - - - - | tape data | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ The presence of a feed hole clocks the data byte into the input register. An IOI signal enables the input register to the I/O Data Bus. Boot Loader ROM S-Register format (12992K): 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | ROM # | 0 0 | select code | 0 0 0 0 0 0 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ The tape format must be absolute binary. Loader execution ends with one of the following instructions: HLT 11B - checksum error (A = calculated, B = expected) HLT 55B - load address >= ROM loader address HLT 77B - end of tape with successful read ------------------------------- 12597A-005 Tape Punch Interface ------------------------------- Output Data Word format (OTA and OTB): 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - - - - - - - - | tape data | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ An IOO signal clocks the lower eight bits into the output register. The data is punched when the STC signal sets the command flip-flop, which asserts the PUNCH signal to the tape punch. Input Data Word format (LIA and LIB): 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - - - - - - - - - - | L | - - - - - | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: L = Tape Supply is Low Pin 21 of the interface connector is grounded, so the input register is transparent, and bit 5 reflects the current state of the the tape low signal. An IOI signal enables the input register to the I/O Data Bus. --------------------------- 13210A Disc Drive Interface --------------------------- Output Data Word format (OTA and OTB): 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | command | - - | P | D | - - - - - - | unit | command +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | write data | data +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - - - - - - - - | cylinder address | data +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - - - - - - | head | - - - | sector address | data +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - - - - - - - - - - | sector count | data +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: D = Defective Track P = Protected Track Command: 0000 = Status Check 0001 = Write Data 0010 = Read Data 0011 = Seek Record 0101 = Refine Sector 0110 = Check Data 1001 = Initialize Data 1011 = Address Record Input Data Word format (LIA and LIB): 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - - - - - - - - - - - - | attention | command +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | read data | data +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - | F | O | - | U | P | - | S | - | N | C | A | G | B | D | E | data +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: F = First Status O = Overrun U = Drive Unsafe P = Data Protect S = Seek Check N = Not Ready C = End of Cylinder A = Address Error G = Flagged Cylinder B = Drive Busy D = Data Error E = Any Error Boot Loader ROM S-Register format (12992F): 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | ROM # | 0 0 | select code | reserved | 0 0 | S | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: S = Subchannel number Bit 0 specifies the subchannel containing the operating system. For the 7900, either the fixed (0) or removable (1) platter may be specified. For the 7901, bit 0 must be 1. Bits 5-3 are nominally zero but are reserved for the target operating system. For example, RTE uses bit 5 to indicate whether a standard (0) or reconfiguration (1) boot is desired. The loader reads 6144 words from cylinder 0 sector 0 of the specified surface into memory starting at location 2011 octal. Loader execution ends with one of the following instructions: HLT 30B - the drive is not ready JSB 2055B,I - the disc read succeeded The 7900A disc drive accepts these inputs (all signals are ground-true): - SELECT 1 - SELECT 2 - SET CYLINDER - SET HEAD - CONTROL - OUTBUS0-7 The drive asserts these outputs (the first two signals are positive-true; the other signals are ground-true): - SECTOR PULSE - SECTOR COMPARE - DRIVE READY - ACCESS READY - INBUS0-5 The SELECT 1 and SELECT 2 lines form the MSB and LSB, respecively, of a two-bit disc unit number. Only the selected drive responds to the remaining signals. A SET CYLINDER pulse stores the 8-bit cylinder number present on OUTBUS0 (MSB) through OUTBUS7 (LSB) into the selected drive's Cylinder Address Register. A SET HEAD pulse stores the 2-bit head number present on OUTBUS0 (MSB) and OUTBUS1 (LSB) into the selected drive's Head Address Register and the 5-bit sector present on OUTBUS3 (MSB) through OUTBUS7 (LSB) into the Sector Address Register. The CONTROL line enables the selected drive to execute the command present on OUTBUS0-2. If OUTBUS7 is also asserted, the CLEAR STATUS signal is asserted, which clears the selected drive's Attention and First Status flip-flops. Asserting OUTBUS6 places the drive's Attention flip-flop output on the INBUS line (0-3) corresponding to the drive select number. No additional command qualification is needed. Asserting OUTBUS7 places the selected drive's First Status, Seek Check, Data Protected, Format Override, and Drive Unsafe (i.e., drive fault) status values on INBUS0 through INBUS4, respectively. No additional command qualification is needed. The Data Protected signal asserts if the Upper Data Protect or Lower Data Protect switch associated with the currently selected head is on. INBUS5 asserts when the drive is selected. The First Status flip-flop sets when the HEADS LOADED (i.e., DRIVE READY) signal first asserts. It clears when the CLEAR STATUS signal asserts. The Attention flip-flop sets when the ACCESS READY (i.e., a seek completes) or DRIVE UNSAFE signals assert. It clears when the CLEAR STATUS or DRIVE SET CYLINDER (i.e., SET CYLINDER * DRIVE SELECT) signals assert. The Status Register on the 13210A interface is implemented in an unusual way. It consists of a set of D-type flip-flops whose D inputs are grounded, and whose individual asynchronous presets are tied to the various controller and currently selected disc drive status lines. The register is clocked, and therefore cleared synchronously, when any command OTHER than Status Check is issued. A Status Check command (as well as a Write, Read, Check Data, or Initialize command) gates the status signals to the preset inputs. The register is therefore "ones-catching," and one-to-zero transitions will not be seen by repeated Status Check commands unless some other command intervenes to clear the register first. When the selected drive receives a Status Check command, it also asserts the CLEAR STATUS signal. This clears the Attention and First Status flip-flops on the drive after they are reported to the controller. But because of the one-catching nature of the Status Register, another Status Check command immediately following the first will return Attention and First Status again, even though the corresponding signals from the drive are now clear. RTE's DVR31 handles this condition when First Status is seen by sending an incomplete Seek command to drive 0 to clear the register between successive Status Check commands. --------------------- 12565A Disc Interface --------------------- Output Data Word format (OTA and OTB): 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | command | - - - - - - - - - - - | U | command +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | write data | data +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | T | - - - - - - - | cylinder address | data +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - - - | head address | - - - | sector address | data +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - - - - - - - | sector count | data +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: U = Drive unit number T = Track condition (flagged track) Command: 0001 = Status Check 0010 = Recalibrate 0011 = Position 0100 = Read Data 0101 = Write Data 0110 = Read Address 0111 = Write Address 1000 = Cyclic Check 1011 = Load Address 1100 = Address Skip Input Data Word format (LIA and LIB): 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | read data | data +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - - - - - - - - | I | N | C | R | F | B | D | E | data +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: I = Drive ID N = Not Ready C = End of Cylinder R = No Record Found F = Flagged Track B = Positioner Busy D = Data Error E = Any Error A protected track is indicated by F = 1 and R = 0. A defective track is indicated by F = 1 and R = 1. A good track is indicated by F = 0 and R = 0. A bad seek, i.e., the sector address does not compare with the record address register, is indicated by F = 0 and R = 1. The command channel input buffer register lines are not connected to the disc drive controller. Pullups on the lines and an inversion mean that reading the command channel results in an all-zeros word. Boot Loader ROM S-Register format (12992A): 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | ROM # | 1 0 | select code | reserved | 0 0 0 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Bits 5-3 are nominally zero but are reserved for the target operating system. For example, RTE uses bit 5 to indicate whether a standard (0) or reconfiguration (1) boot is desired. The loader reads 6144 words from cylinder 0 head 0 sector 0 into memory starting at location 2011 octal. Loader execution ends with a JSB indirect through location 2055 octal. The success or failure of the transfer is not checked. -------------------------------- 13175D Disc Controller Interface -------------------------------- Boot Loader ROM S-Register format (12992B): 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | ROM # | 0 1 | select code | reserved | head | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Bit 12 must be 1 for a manual boot. Bits 5-3 are nominally zero but are reserved for the target operating system. For example, RTE uses bit 5 to indicate whether a standard (0) or reconfiguration (1) boot is desired. The loader reads 6144 words from cylinder 0 sector 0 of the specified head into memory starting at location 2011 octal. Loader execution ends with one of the following instructions: HLT 30B - the drive is not ready JSB 2055B,I - the disc read succeeded --------------------- 12821A Disc Interface --------------------- Boot Loader ROM S-Register format (12992H): 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | ROM # | 0 1 | select code | reserved | head | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Bit 12 must be 1 for a manual boot. Bits 5-2 are nominally zero but are reserved for the target operating system. For example, RTE uses bit 5 to indicate whether a standard (0) or reconfiguration (1) boot is desired. The loader reads 256 words from cylinder 0 sector 0 of the specified head into memory starting at location 2011 octal. Loader execution ends with one of the following instructions: HLT 11B - the drive aborted the transfer due to an unrecoverable error JSB 2055B,I - the disc read succeeded ---------------------------- 12610B Drum Memory Interface ---------------------------- Output Data Word format (OTA and OTB): 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | W | starting track | starting sector | command +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | write data | data +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: W = Write Transfer Input Data Word format (LIA and LIB): 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | S | - - | next sector | R | - | C | - | A | W | P | B | command +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | read data | data +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: S = Sector Flag R = Drum Ready C = Sector Address Coincidence A = Abort Flag W = Writing Enabled (not protected) P = Parity Error B = Busy ---------------------------- 12606B Disc Memory Interface ---------------------------- Output Data Word format (OTA and OTB): 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | W | - | starting track | starting sector | command +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | write data | data +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: W = Write Transfer Input Data Word format (LIA and LIB): 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | S | next sector | R | I | C | - | A | W | P | B | command +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | read data | data +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: S = Sector Flag R = Disc Ready I = Read Inhibit C = Sector Address Coincidence A = Abort Flag W = Writing Enabled (not protected) P = Parity Error B = Busy ----------------------------------------------------- 12966A Buffered Asynchronous Communications Interface ----------------------------------------------------- Output Data Word format (OTA and OTB): 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | R | 0 0 0 | - - - - | output data byte | transmit +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | R | 0 0 1 | - - - - - - | M | C | D | R | L | X | enab irq +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | R | 0 1 0 | - - - - - - | D | C | D | R | L | X | stat ref +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | R | 0 1 1 | - - - - - - | S | E | P | N | size | chr cntl +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | R | 1 0 0 | - - - | T | A | D | S | M | baud rate | i/f cntl +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | R | 1 0 1 | - - - - - - | S | H | F | E | B | P | stat rst +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | R | 1 1 0 | - - - | S | special character | spec chr +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: R = Master Reset For the Enable Device Status Interrupt command: M = Enable flag-per-character mode C = Enable interrupt on CB (CTS) miscompare D = Enable interrupt on CC (DSR) miscompare R = Enable interrupt on CE (RI) miscompare L = Enable interrupt on CF (RLSD) miscompare X = Enable interrupt on SBB/SCF miscompare For the Device Status Reference command: D = Diagnostic test bit C = Reference CB (CTS) value D = Reference CC (DSR) value R = Reference CE (RI) value L = Reference CF (RLSD) value X = Reference SBB/SCF value For the Character Frame Control command: S = 1/2 stop bits (0/1) E = Disable/enable echo (0/1) P = Disable/enable parity (0/1) N = Odd/even parity (0/1) Size: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits For the Interface Control command: T = Receive/transmit mode (0/1) A = CA (RTS) off/on (0/1) D = CD (DTR) off/on (0/1) S = SBA/SCA off/on (0/1) M = Program/DMA data transfer (0/1) Baud Rate: 00 = external x16 clock 01 = 50 baud 02 = 75 baud 03 = 110 baud 04 = 134.5 baud 05 = 150 baud 06 = 300 baud 07 = 600 baud 10 = 900 baud 11 = 1200 baud 12 = 1800 baud 13 = 2400 baud 14 = 3600 baud 15 = 4800 baud 16 = 7200 baud 17 = 9600 baud For the Interrupt Status Reset command: S = Clear special character status H = Clear buffer half-full status F = Clear buffer full status E = Clear buffer empty status B = Clear break status P = Clear overrun/parity error status For the Special Character command: S = character is not/is special (0/1) Input Data Word format (LIA and LIB): 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | V | S | buffer count | input data byte | data +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | I | S | - | R | T | - | H | F | E | B | P | C | D | R | L | X | status +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: V = input data byte is not/is valid (0/1) S = input data byte is not/is special (0/1) I = device interrupt occurred S = special character received R = spare receiver T = test (received data) H = buffer is half-full F = buffer is full E = buffer is empty B = break detected P = parity error or data buffer overrun C = CB (CTS) line status D = CC (DSR) line status R = CE (RI) line status L = CF (RLSD) line status X = SBB/SCF line status ------------------------------ 12732A Flexible Disc Subsystem ------------------------------ Documentation: - 12732A/12733A Flexible Disc Subsystem Diagnostic Reference Manual 12732-90003 December 1977 - HP 12732A/12733A Flexible Disc Subsystem Operating and Service Manual 12732-90005 October 1978 - RTE Driver DVR33 for HP 12732A/HP 12733A Disc Drives Programming Manual 12732-90001 October 1979 - 9885M/S Flexible Disk Drive Installation Manual 09885-90010 May 1978 - HP 9885M/S Flexible Disk Drive Service Manual 09885-90031 September 1978 The 12732A Flexible Disc Subsystem consists of: - one 9885M Master 8" Flexible Disc Drive - zero to three 9885S Slave 8" Flexible Disc Drives - one 12735A Flexible Disc Interface - one 12992E Flexible Disc Loader ROM 9885 Specifications: - 67 tracks per disc - 1 head per track (single sided) - 30 sectors per head - 128 words per sector - 514,560 bytes per disc - write-protect tab - self-test switch - drive-select switch (0-3) - 360 rpm - 5.56 ms latency per sector - 50 ms head load - 10 ms track-to-track step - 10 ms head settling time - 32.0 us per data word transfer time - 1.46 ms sector-address field overhead The 12735A Flexible Disc Interface consists of: - one 12735-60001 Control Interface - one 12735-60002 Data Interface - one 12735-60003 Interface Cable The interfaces are 12566 Microcircuit interfaces with different pullup resistors for the device interface. Jumpers are preset as: Jumper Cntl Data ----- ---- ---- W1 A A W2 B A* W3 B B W4 B B W5 IN IN W6 IN IN W7 IN IN W8 OUT IN W9 B B * For the General-Purpose Register Diagnostic, this jumper must be moved to position B (Device Command FF resets on leading/trailing edge of Device Flag). Unusually, the control interface is installed in the higher-priority (lower select code) slot, and the data interface is installed in the lower-priority (higher select code) slot. Connections between the interfaces and the disc drives are: Signal Pins Control Description -------- ----- ------------- ------------ PRESET A BIT 0 OUT Preset -CTL0 B BIT 1 OUT Control -PSTS 16 BIT 15 IN Status -EIR AA,23 DEV FLG IN Error Flag PRESET is asserted by the CPU to clear all drives to the "power on" state. This clears the internal registers and buffers, returns the heads of all drives to track 0, and sets the "media changed" bit in the status word. The data flag sets when the command completes. -CTL0 is asserted by the CPU when less than 128 words per sector are transferred. This suppresses the Error Status signal generated by the drive when the word count does not end at 128. The diagnostic manual says that this bit is set "after the last word has been transferred," but the driver actually sets this bit /before/ a read or write command is issued when the word count indicates a partial sector transfer. -PSTS is asserted by the drive when "power up" and "ready" conditions occur. -EIR is asserted by the drive when an error occurs during a data transfer. Examples are "door opened during transfer" and "data overrun." The control interface ENCODE (DEF CMD OUT) signal is not used. STC sets the control flip-flop to enable interrupts but otherwise performs no action. Signal Pins Data Description -------- ----- ------------- ------------ -DIO 00 A,1 BIT 0 IN/OUT Data -DIO 01 B,2 BIT 1 IN/OUT Data -DIO 02 C,3 BIT 2 IN/OUT Data -DIO 03 D,4 BIT 3 IN/OUT Data -DIO 04 E,5 BIT 4 IN/OUT Data -DIO 05 F,6 BIT 5 IN/OUT Data -DIO 06 H,7 BIT 6 IN/OUT Data -DIO 07 J,8 BIT 7 IN/OUT Data -DIO 08 K,9 BIT 8 IN/OUT Data -DIO 09 L,10 BIT 9 IN/OUT Data -DIO 10 M,11 BIT 10 IN/OUT Data -DIO 11 N,12 BIT 11 IN/OUT Data -DIO 12 P,13 BIT 12 IN/OUT Data -DIO 13 R,14 BIT 13 IN/OUT Data -DIO 14 S,15 BIT 14 IN/OUT Data -DIO 15 T,16 BIT 15 IN/OUT Data -PCTL Z,22 DEV CMD OUT Data Control -PFLAG AA,23 DEV FLG IN Data Flag -DIOnn transfer commands and data to the drive and receive status and data from the drive. Because the bus is bidirectional, a zero word must be written to the interface prior to receiving data from the drive (the output inverting buffers are open-collector, so writing a zero floats the data lines). -PCTL and -PFLAG handshake data between the interface and the drive. Output Data Word format (OTA and OTB): 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | - - - - - - - - - - - - - - | C | P | control +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | command | data +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | write data | data +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: C = Control (less than 128 words will be output) P = Preset to power-on condition Commands: 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 0 | drive | sector count | Read +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 1 | drive | sector count | Verify +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 0 | drive | sector count | Write +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 1 | drive | track | sector | Seek +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 1 | drive | track | 1 1 1 1 | 0 | Format +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 1 | drive | 1 1 1 1 1 | 0 0 | 1 1 1 1 | 1 | Step +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 1 | drive | 1 1 1 1 1 | 0 1 | 1 1 1 1 | 1 | Mark +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 1 | drive | 1 1 1 1 1 | 1 0 | 1 1 1 1 | 1 | Dump +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 1 | drive | 1 1 1 1 1 | 1 1 | 1 1 1 1 | 1 | Status +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ READ permits a zero sector count. This causes the head movement specified by the SEEK command (which just loads the values into registers but does not move the heads). WRITE and VERIFY with zero sector counts are illegal. READ, VERIFY, and WRITE expect to transfer 128 words per sector and will report "data overrun" for a partial sector unless CTL0 is asserted after the last word is transferred to indicate the end of the data. VERIFY reads with close flux transition tolerance. Data is read in as with READ. SEEK example on diag page E-3 says, "No head movement occurs until data transfer command is output." DVR33 seems to agree; the long flag wait occurs after the READ or WRITE command, not after the SEEK. FORMAT command is followed by a 30-word data transfer specifying the sector numbering order. The specified track number is used for the sector headers, and formatting operates on the current head position (so physical track and logical track need not agree). STEP moves the head one track higher. This permits positioning over a bad or unformatted track. MARK marks a track defective. The controller will automatically skip this track when seeking. DUMP reads from the sector physically following the current (last seek) sector. It is used to recover data from a sector whose header is unreadable. All commands except Seek cause an automatic status return at completion of the operation. The controller has two internal states: command acceptance and command execution. Presetting the controller puts it in the command acceptance state. Before any command is recognized, a password of 127207 octal must be output to the data channel, followed by the command and any required data. The data channel flag sets after every data word. Most error conditions set the control channel flag and return automatic status. A partial sector write is terminated by setting the C bit of the control channel word after the last data word has been sent. Automatic status is then returned by the controller. Input Data Word format (LIA and LIB): 15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | S | - - - - - - - - - - - - - - - | control +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | P | - - - | error code | - | T | S | R | W | C | drive | data +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | read data | data +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Where: S = Power on and ready P = Power off or current operation unsuccessful T = Transfer complete S = Seek complete R = Not ready W = Write protected C = Media changed Error Code: 00 = no error 01 = no drive power 02 = door open 03 = no disc 04 = invalid command 05 = sector not found 06 = track not found 07 = data CRC error 10 = data overrun 11 = verify error All controller commands except Seek return status in bits 15-0 of the data channel. Status P is signal -PSTS (control channel bit 15) inverted. The standard disc format uses a sector interleave of 5 (i.e., sequential sectors are numbered 0, 6, 12, 18, 24, 1, 7, 13, 29, 25, 2, etc.). This presents a 22 ms delay between the end of one sector and the beginning of the next. The fast disc format uses a sector interleave of 0. Supported interleaves are 0, 1, 2, 4, 5, 9, and 14. Track-to-track sector offsets corresponding to these interleaves are 4, 4, 4, 5, 6, 10, and 15. The MARK command is used to mark defective tracks. When formatting a disc, defective tracks are marked and skipped, i.e., the next good physical track is initialized with the next logical track number. This implies: - A disc may contain fewer than 67 tracks. - A track or sector may not exist if it was not specified in a FORMAT command; there is no guarantee of logical integrity. - Attempting to read a defective track causes an auto-seek to the next track and a retry; this continues until a good track is found or the end of the disc is reached. - A seek to a given track will not reach the expected track if there are intervening defective tracks; an auto-seek to the moved location (as calculated by the expected and actual track numbers) and a retry are performed. -------- Software -------- The RTE driver issues all commands except DUMP. The driver depends on word 0 of track 0 sector 0 being set to the number of good tracks on the disc when the disc is formatted. Prior to the value being read, the driver assumes 67 tracks are available on each drive. At each initiation, the driver sends a zero-word to the control channel and sets control. Clear (Control 0) ----------------- A controller preset is performed by toggling control channel output bit 0 with successive OTAs (0 -> 1 -> 0) and then sending an all-zeros word to the data channel (to float the data bus), setting control, and waiting for the data flag to set. Read or Write ------------- Before sending a command, a password is sent. First, control channel status is checked for bit 15. If it is 0 (power off or controller not ready), then the controller is preset but without waiting for the flag. Bit 15 is checked again, and if it is still 0, the not-ready exit is taken. If the controller is ready, then if this is the first entry, the controller is preset again (with the wait for the flag). Finally, the password (127207B) is output to the data channel, control is set, and the routine waits for the data flag before returning. If the transfer involves a partial sector, control channel output bit 1 (CTL0) is set. Then a SEEK to the starting track and sector is issued to the data channel, and the routine waits for the data flag. The password is sent again, and then the READ/VERIFY or WRITE command is sent to the data channel and control is set. For a READ/VERIFY, the routine waits (in a simple SFS loop) for the data channel flag to set, then sends an all-zeros word to the data channel (to float the data bus in preparation for reception) and sets control again. For a WRITE, this second operation is omitted. Finally, DMA is started, command channel control is set to enable error interrupts, and the driver exits with a 5-second timeout. When the DMA completion interrupt occurs, then if a WRITE was done, the driver waits for the data channel flag (last word acknowledged). Then it sends an all-zeros word to the data channel, sets control, and waits for the data flag. Then it reads the (automatic) status from the data channel, sets control (to "tell the controller that we have the status"), and waits for the data flag. The driver expects T = 1, R = 0, and error code = 0 for a good transfer. Format (Write 23B, 0) --------------------- This is handled as a normal write operation, except that the FORMAT command is output to the data channel instead of the WRITE command. DMA is used to transfer the 30 words that describe the sector layout. Step (Write 23B, 7600B) ----------------------- The password is sent, then the command is sent to the data channel, control is set, and the routine waits for the flag. On completion, the controller status is obtained. Mark (Write 23B, 7640B) ----------------------- Same actions as STEP. Status (Write 23B, 7440B) ------------------------- Same actions as STEP. The DSKET (disc formatting) program issues these driver calls: - Clear (EXEC 3, 0) - FORMAT (EXEC 2, 23B, 0) - WRITE 0 (EXEC 2, 23B, 7630B) - WRITE (EXEC 2, 0) - VERIFY (EXEC 1, 30B) - MARK (EXEC 2, 23B, 7640B) but only if VERIFY returns an error - STEP (EXEC 2, 23B, 7600B) DSKET must be run to initialize a new diskette image, as it writes the number of good tracks to track 0 sector 0 and also writes the FMGR directory to the last good track and preallocates the FLOPLK file that occupies and protects the first sector. The diagnostic tests the status returns for: * Power off and on. Power on the controller presents a different status than power on the drive. Unit 0 (master) power off drops -PSTS and returns "no drive power" for drive 0. Units 1-3 (slaves) power off returns "no drive power" for drives 1-3. * Door open and closed. * Protected and unprotected discs. * Illegal commands (WRITE or VERIFY with sectors = 0, SEEK or FORMAT to track > 66 or sector > 29, and undefined command bit patterns). * Data overrun (by not setting CTL0 on a partial-sector read and write). * "Track not found" by marking track 2 defective and issuing a zero-sector read at track 2 sectors 0, 15, and 29, and then "Seek complete" by issuing zero-sector reads at track 1 sector 29 and track 3 sector 0. * "Sector not found" by formatting track 3 with all sector numbers = 29 and issuing a zero-sector read at track 3 sectors 1, 15, and 29, and then "Seek complete" by issuing a zero-sector read at track 3 sector 0 (READ verifies the preceding sector on the track). The diagnostic cannot check the "Data checkword error" and "Verify error" status codes. -------------- Implementation -------------- Implementation is straightforward, except for the FORMAT, MARK, and DUMP commands, which operate on the sector address headers, and realistic timing, which depends on the interleave chosen. There are three possible implementation approaches: 1. Operational. This approach would work correctly with the RTE driver and formatting programs but would not pass the diagnostic tests that check FORMAT, MARK, and DUMP operation. The image file would contain only data, and sector interleave and track offset would be ignored. The FORMAT command would absorb the 30 sector-order words but otherwise would do nothing. The MARK command would do nothing. The DUMP command would return the next logical sector instead of the next physical sector, as all images would behave as though they were set for no interleave. The implementation would never return Sector Not Found, Track Not Found, or Verify Error; Data CRC Error would occur only if a host file system error occurred. REALTIME mode would consider only seek and rotation times. 2. Rigged. This approach would work identically with the driver and formatter and, in addition, also pass the diagnostic. It would do the latter by detecting the specific tests applied and providing the expected responses. Consequently, it would fail to operate properly with other combinations of the FORMAT, MARK, and DUMP commands -- for instance, operator design programs using these commands would fail. As above, the image file would contain only data, and REALTIME mode would consider only seek and rotation times. 3. Emulated. This approach would attempt to emulate the hardware fully. The track and sector data supplied with FORMAT command would be saved with the data in the image file (probably at the end) and would be used to provide accurate REALTIME timings. The image file would be stored sequentially and contiguous; only the timing and access legality would be affected by the FORMAT settings. The DUMP command would return the next physical sector, based on the interleave specified by FORMAT for that track, and the Sector Not Found and Track Not Found errors would occur if the disc was formatted and accessed in a way that would produce them in hardware. The MARK command would mark a track as bad, so that access would skip to the next physical track (which may not be the next logical track). Verify Error would not occur. This simulation is implemented with the HP disc library (hp_disclib.c). Flexible disc commands are translated into their 13037 equivalents, as follows: Floppy Command 13037 Command -------------- --------------------------------------------------- PRESET Recalibrate READ Read VERIFY Read WRITE Write SEEK Address Record FORMAT (none) STEP Request Disc Address + Seek MARK (none) DUMP Request Disc Address + Address Record + Read (or Verify + Read) STATUS Request Status PRESET issues a Recalibrate to each mounted unit. The SEEK command does not move the heads until a READ, VERIFY, or WRITE is done, so we implement this by using Address Record to record the SEEK parameters and then depending on address verification to perform an auto-seek when the following READ or WRITE is issued. The STEP command does move the heads, so it is implemented by a Request Disc Address to get the current cylinder address and then a Seek to position to the next cylinder address. FORMAT and MARK write just the sector address fields. As these are not simulated, they effectively do nothing but set the flag after the appropriate time. DUMP reads from the next physical sector after the last sector addressed, so a Request Disc Address command is used to pick up the sector address, which is then incremented. An Address Record is performed to set the target address, and then a Read is performed to transfer the data. STATUS issues a Request Status to get the last controller status, but the result is reformatted and augmented before returning it to the CPU. ---------------------- Reset, preset, shmeset ---------------------- 21xx/1000 systems provide four I/O device reset events: power on, front panel PRESET, programmed CLC 0, and programmed CLC . Each of these events asserts a different combination of physical I/O backplane signals: * power-on -- deny PON and assert POPIO and CRS, then assert PON. * PRESET -- assert POPIO and CRS. * CLC 0 -- assert CRS. * CLC -- assert CLC. These combinations of signals allows an interface to take up to four separate clearing actions, although many cards will combine two or more of the events, e.g., taking the same action in response to PRESET and power-on by ignoring the PON signal. The programmed events are simulated directly. The power-on event is initiated in the simulator with the RESET -P command. The preset event is initiated with the RESET command. The current RESET semantics do not match those of the HP hardware PRESET button function. On the 2100 system, the PRESET function is split into two buttons: INTERNAL PRESET and EXTERNAL PRESET. The former asserts POPIO and CRS for device select codes 00-05, and the latter asserts for select codes 06-77. On the 2116/21MX, these functions are combined into a single PRESET button that asserts for all select codes. Moreover, the hardware PRESET has no analog to RESET , i.e., there is no way to preset a single card. A better solution, then, would be to add a new, VM-specific command that implements the HP semantics exactly: PRESET -- preset SC 00-77 PRESET -I -- preset SC 00-05 (illegal on 21MX) PRESET -E -- preset SC 06-77 (illegal on 21MX) The first command would be legal on both the 2116/21MX and the 2100. On the latter, it would be equivalent to PRESET -I followed by PRESET -E. ----------------------------- PON, POPIO, and CRS responses ----------------------------- As part of the foregoing modifications, device responses to the three new I/O backplane signals must be modelled. Here are the responses as indicated by the device documentation: CPU (21MX) PON: POPIO: CRS: CLC: DMS (12731A MEM) PON: (unused) POPIO: clr memenb, set sysmap, clr status reg, clr viol reg, clr fence reg CRS: (unused) CLC: (unused) DMA (12897B DCPC) PON: (unused) POPIO: set fbf 6/7, set flg 6/7 CRS: clr ctl 2/3, clr ctl 6/7 CLC: clr ctl sc MP (12892B) PON: (unused) POPIO: clr mev FF, set evr FF, clr fbf, clr flg, clr ctl, set parenb FF, clr parerr FF, clr mpv FF CRS: (unused) CLC: (unused) DP (12557A) PON: POPIO: CRS: CLC: DP (13210A) PON: (unused) POPIO: Set DC flg, set CC flg CRS: Clr DC ctl (encode), clr CC ctl, clr attn reg, xfer cyl 0 to drive CLC: Clr CC ctl (CLC DC is NOP) BUG NOTE: IOO to CC clears CC cmd! DQ (12565A) PON: POPIO: CRS: CLC: DR (12606B) PON: POPIO: CRS: CLC: DR (12610B) PON: POPIO: CRS: CLC: DS (13037A) PON: Clr I/F selected FF (same as DSCIF cmd) POPIO: Set flg, clr cmrdy FF CRS: Clr ctl, clr cmd-follows, set CLEAR to 13037 CLC: Clr ctl, set cmd-follows, set EOD to 13037, clr fifo ptr, clr fifo data IPL (12566B) PON: (unused) POPIO: Set flg, set fbf, clr output reg CRS: Clr ctl, clr cmd CLC: Clr ctl, clr cmd (W9 in pos A) LPS (12653A) PON: POPIO: CRS: CLC: LPT (12845A) PON: (unused) POPIO: Set fbf, set flg, clr output reg CRS: Clr ctl CLC: Clr ctl MS (13181A) PON: (unused) POPIO: Execute CLR cmd, clear reject FF CRS: Clr DC ctl, clr CC ctl, set DC fbf, set D flg, set CC fbf, set CC flg, set GAP FF CLC: Clr DC/CC ctl MS (13183A) PON: (unused) POPIO: Execute CLR cmd CRS: Clr DC ctl, clr CC ctl, set DC fbf, set D flg, set CC fbf, set CC flg CLC: Clr DC/CC ctl MT (12559A) PON: POPIO: CRS: CLC: MUX (12920A) PON: (unused) POPIO: Set DC fbf, set DC flg, set CC fbf, set CC flg, set master reset ff CRS: [UD] clr buf reg (2), clr echo/par ff, clr config ff, clr enab ff, clr diag ff, clr char size reg, clr samp count reg, clr baud rate reg, clr char lost ff, clr break ff, clr start bit ff, clr buffer flg ff [LD] Clr DC ctl, clr tflg, clr stcbf, clr stcff, clr addr cntr, clr field cntr, clr addrff, clr main buf ff, clr aux chan ff, clr chan ffs (16) [CN] clr CC ctl CLC: Clr DC ctl, clr CC ctl NOTE: incr sc for upper data, lower data, control PTR (12597A) PON: (unused) POPIO: Set flg, set fbf, clr output reg CRS: Clr ctl, clr cmd CLC: Clr ctl, clr cmd PTP (12597A) PON: (unused) POPIO: Set flg, set fbf, clr output reg CRS: Clr ctl, clr cmd CLC: Clr ctl, clr cmd TTY (12531C) PON: (unused) POPIO: Set fbf, set flg CRS: Clr ctl, clr clk enb, clr read, set input, clr print, clr punch, clr dividers, set fbf, set flg CLC: Clr ctl CLK (12539C) PON: (unused) POPIO: Set flg, fbf CRS: Clr ctl CLC: Clr ctl --------------------- P and M Register Size --------------------- On the 1000, the P register is part of the 16-register RAM in the ALU. It is a full 16 bits in size. One may store and retrieve bit 15. Single-stepping from P = 077777 will result in P = 100000. If memory is cleared, P cycles through all 65536 values. The M register resides on the memory controller card and is 15 bits in size. Bit 15 is not stored. Although P is 16 bits, effective execution wraps around from P = 077777 to P = 000000, because when P = 100000 is copied to the M register, bit 15 is lost. On the 2100, P is a hardware register on the ALU card and is a full 16 bits. Incrementing from P = 077777 will result in P = 100000. M is a 15-bit register on the memory data control card. Bit 15 is not stored. On the 2116, P and M are hardware registers on the ALU cards and are both a full 16 bits. However, the memory logic only uses MR14-0, so bit 15 is effectively ignored. In SIMH, P is always masked to VAMASK (077777), which is technically incorrect. However, as there are no instructions that load P into a visible register (e.g., into A or B), this probably does not matter. Technically, it is the P-to-M transfer that should be masked to VAMASK.