FPP Notes: ---------- - base set jump table: 0527 01000 320 060004 LB01000 JMP RJ30 LB01400 ; 105000-105017 (add) 0528 01001 320 060004 JMP RJ30 LB01400 ; 105020-105037 (sub) 0529 01002 320 060004 JMP RJ30 LB01400 ; 105040-105057 (mpy) 0530 01003 320 060004 JMP RJ30 LB01400 ; 105060-105077 (div) 0531 01004 343 130507 IMM LOW L 354B ; 105100-105117 (fix) 0532 01005 320 061004 JMP RJ30 LB01420 ; 105120-105137 (flt) - FPP jump table: 0783 01400 320 063707 LB01400 JMP LB01476 ; 105000, 20, 40, 60 (2 word fp) 0784 01401 320 062007 JMP LB01440 ; 105001, 21, 41, 61 (3 word fp) 0785 01402 324 041307 JMP 21026B ; 105002, 22, 42, 62 (4 word fp) 0786 01403 320 062017 JMP STFL LB01440 ; 105003, 23, 43, 63 (5 word fp) 0787 01404 320 072207 JMP LB01644 ; 105004, 24, 44, 64 (test) 0788 01405 320 071647 JMP LB01635 ; 105005, 25, 45, 65 (exponent) 0789 01406 370 036772 RTN MPP1 ; 105006, 26, 46, 66 (reset) 0790 01407 320 074747 JMP LB01717 ; 105007, 27, 47, 67 (stack) 0791 01410 320 077407 JMP LB01770 ; 105010, 30, 50, 70 (?) 0792 01411 230 036740 READ RTN ; 105011, 31, 51, 71 (nop) 0793 01412 230 036740 READ RTN ; 105012, 32, 52, 72 (nop) 0794 01413 230 036740 READ RTN ; 105013, 33, 53, 73 (nop) 0795 01414 324 041005 JMP J74 21020B ; 105014, 34, 54, 74 (double int) 0796 01415 230 036740 READ RTN ; 105015, 35, 55, 75 (nop) 0797 01416 230 036740 READ RTN ; 105016, 36, 56, 76 (nop) 0798 01417 230 036740 READ RTN ; 105017, 37, 57, 77 (nop) 0799 01420 320 064607 LB01420 JMP LB01514 ; 105100, 20 (2 word int*1) 0800 01421 320 065047 JMP LB01521 ; 105101, 21 (3 word int*1) 0801 01422 320 065047 JMP LB01521 ; 105102, 22 (4 word int*1) 0802 01423 320 065057 JMP STFL LB01521 ; 105103, 23 (5 word int*1) 0803 01424 320 065447 JMP LB01531 ; 105104, 24 (2 word int*2) 0804 01425 320 065647 JMP LB01535 ; 105105, 25 (3 word int*2) 0805 01426 320 065647 JMP LB01535 ; 105106, 26 (4 word int*2) 0806 01427 320 065657 JMP STFL LB01535 ; 105107, 27 (5 word int*2) 0807 01430 230 036740 READ RTN ; 105110, 30 (nop) 0808 01431 230 036740 READ RTN ; 105111, 31 (nop) 0809 01432 230 036740 READ RTN ; 105112, 32 (nop) 0810 01433 230 036740 READ RTN ; 105113, 33 (nop) 0811 01434 324 041005 JMP J74 21020B ; 105114, 34 (double int) 0812 01435 230 036740 READ RTN ; 105115, 35 (nop) 0813 01436 230 036740 READ RTN ; 105116, 36 (nop) 0814 01437 230 036740 READ RTN ; 105117, 37 (nop) * F-Series .DMP, .DDI, and .DDIR are implemented by floating operands to extended-precision format, executing a .XMPY or .XDIV, and fixing operands back to double-integer format. This is faster than firmware and is OK because all 32-bit integer values are represented exactly in the 40-bit XP mantissas. ---------------------------------------------------------------------------------- Guard, sticky, and bits < LSB ============================= Rounding is handled differently in the M/E-Series firmware and the F-Series FPP. In firmware, the eight bits vacated by the exponent provide eight "guard" bits that aid the rounding decision. Because shifts are done in two- or three-integer chunks, values shifted more than eight bits to the right lose precision. Therefore, to mimic this action under simulation, we must mask the 64-bit mantissas to 32 (if single-precision) or 48 (if double-precision) bits before normalization to remove bits that would have been lost by shifting, thus ensuring that normalization shifts in zeros and not the purportedly lost bits. Rounding then takes place on the eight bits to the right of the LSB by adding 10000000 (+) or 01111111 (-) to the mantissa, depending on the sign. In hardware, a 56-bit mantissa register is extended by a four-bit "rounding register." This register provides three guard bits and a sticky bit. The latter is set if a 1 is shifted into the fourth position. Note, though, that the register holds four significant bits; the sticky bit is really a flag that is used in rounding. All bits of the combined mantissa and rounding registers are left- and right-shifted as required by operations, regardless of precision. That means, for example, that a single-precision value (24-bit mantissa) can be right-shifted 36 bits (32 + 4) and then reversed without losing any precision. However, for single- and extended-precision values, the rounding register is loaded with bits from the end of the respective mantissas, i.e., from the 24th or 40th bit, respectively. So the sticky-bit flag is set if a 1 is shifted out of effective bits 27 or 43. Normalization uses all available mantissa bits, so 60 bits of precision are maintained. The rounding decision is then made on the basis of the guard bit after normalization, i.e., after any needed left-shifts. For example, if a single-precision mantissa contains a 1 bit in the LSB, and it is shifted right (during addition) by 20 bits and then left by 20 during normalization, the LSB would again be a 1, the guard bit for rounding would be a 0, and the stiky bit would be set (because the 1 bit passed "through" the sticky bit position in the rounding register). In the single- and extended-precision cases, right-shifts cause bits to pass through the rounding register in addition to passing through the unused mantissa bits. So unlike the firmware case, bits shifted beyond the guard position(s) may still be recoverable during normalization. They are not recoverable in the double-precision case, as all bits of the mantissa are significant. For left-shifting 56-bit operands, the four bits of the rounding register are shifted into the LSB. Additional shifts supply zeroes. For 24 and 40-bit operands, zeros are shifted into bit 56 (because the rounding register contains bits from positions 24 and 40, respectively). In simulation, the sticky bit flag is set if the shift count is >= 4 and any of the bits between mantissa bit 0 and bit (shift count - 4) are set to 1. Masking before normalization, therefore, preserves the upper 60 bits (for double-precision) or 56 bits (for single- or extended-precision). After normalization, the guard bit is bit 57, 41, or 25. The sticky bit is ORed into bit 0, and the rounding constants used by the firmware implementation are then employed.